Missing RAW for some branches

[lupino3]

Consider the following

.code
        slt r1, r2, r4
        beqz r1, finish
finish: nop

With forwarding enabled, EduMIPS64 does not show any stalls, because - in the internal implementation - the semaphore for r1 that is locked by slt for writing to it is unlocked before beqz needs to read it.

This is not consistent with the description in Hennessy & Patterson, which says that the ID cycle of the branch will be executed before the EX stage of the ALU instruction (slt).

In terms of implementation, it would be very hard to change the execution order of stages in EduMIPS64 without introducing bugs. I think a practical solution may be to delay unlocking the registers until the end of the cycle execution (the IF stage).

Thanks to Dr. Sergio Santander Jiménez for raising this problem and providing examples and references for me to understand it.

[lupino3]

All the calls to decrWriteSemaphore are in this form:

    cpu.getRegisterFP(params.get(FD_FIELD)).decrWriteSemaphore();

In order to have the register unlocked at the end of the current CPU cycle, we need to add a new method to the CPU to schedule the register for unlocking at the end of the cycle.

In short, instructions won't be able to handle unlocking directly. They'll need to defer to the CPU.