-
Notifications
You must be signed in to change notification settings - Fork 1
/
Copy pathverification.cr.mti
81 lines (58 loc) · 3.5 KB
/
verification.cr.mti
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
/home/ntu-nikesh/Desktop/network/verilogModules/File_load.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/File_load.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module File_load
Top level modules:
File_load
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/testbench.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/testbench.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module testbench
Top level modules:
testbench
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/Output_encoder.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/Output_encoder.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module Outport_encoder
Top level modules:
Outport_encoder
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/OutPortFIFO.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/OutPortFIFO.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module OutPortFIFO
Top level modules:
OutPortFIFO
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/Network.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/Network.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module Network
Top level modules:
Network
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/parameters.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/parameters.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/InputQueue.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/InputQueue.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module InputQueue
Top level modules:
InputQueue
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/InputArbiter.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/InputArbiter.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module InputArbiter
Top level modules:
InputArbiter
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/OutputArbiter.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/OutputArbiter.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module OutputArbiter
Top level modules:
OutputArbiter
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/RouterAllocator.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/RouterAllocator.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module RouterAllocator
Top level modules:
RouterAllocator
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/RouterCore.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/RouterCore.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module RouterCore
Top level modules:
RouterCore
} {} {}} /home/ntu-nikesh/Desktop/network/verilogModules/RegFile_1port.v {1 {vlog -work work -stats=none /home/ntu-nikesh/Desktop/network/verilogModules/RegFile_1port.v
Model Technology ModelSim ALTERA vlog 10.3c Compiler 2014.09 Sep 20 2014
-- Compiling module Register
Top level modules:
Register
} {} {}}