From b1c943f72de2c275f17e7516b4a86f4e82eabde9 Mon Sep 17 00:00:00 2001 From: b Date: Mon, 19 Aug 2024 10:22:07 +0100 Subject: [PATCH 1/4] Fix LQ instruction to support signed offsets Based on the Power ISA manual sign extended DQ<<4 is added to RA to get source EA. --- Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc | 1 + Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc index aaa76cc4acd..5947bdf859e 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc @@ -1983,6 +1983,7 @@ dUI16PlusRAOrZeroAddress: val^"("^RA_OR_ZERO^")" is RA_OR_ZERO & UI_16_s8 [ val @ifdef BIT_64 dsPlusRaAddress: simm_ds(A) is SIMM_DS & A [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + A;export tmp;} dsPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO) is SIMM_DS & RA_OR_ZERO [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} +dqPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO) is DQs & RA_OR_ZERO [simm_ds = DQs << 4;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} @endif diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc index ce9a52cc896..0b1675e6643 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc @@ -1609,8 +1609,8 @@ define pcodeop stdcixOp; # ISA-info: lq - Form "DQ" Page 751 Category "LSQ" # binutils: power4.d: +0: e0 83 00 00 lq r4,0\(r3\) # binutils: power4.d: +4: e0 83 00 00 lq r4,0\(r3\) -:lq RT,A,DQ is $(NOTVLE) & OP=56 & RT & Dp & A & DQ & BITS_0_3=0 & regp [regpset = Dp+1;] { - ea:$(REGISTER_SIZE) = A + sext(DQ:2 << 4); +:lq RT,dqPlusRaOrZeroAddress, BITS_0_3 is $(NOTVLE) & OP=56 & RT & Dp & RA & DQs & dqPlusRaOrZeroAddress & BITS_0_3 & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = RA + sext(DQs:2 << 4); @if ENDIAN == "big" RT = *:$(REGISTER_SIZE) ea; regp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); From 2034c0213102c34db95a6131325125303cd83304 Mon Sep 17 00:00:00 2001 From: b Date: Sun, 24 Nov 2024 14:27:16 +0100 Subject: [PATCH 2/4] Removed PPCAS-specific decoding --- Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc index 0b1675e6643..7e6e58203c0 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc @@ -1609,7 +1609,7 @@ define pcodeop stdcixOp; # ISA-info: lq - Form "DQ" Page 751 Category "LSQ" # binutils: power4.d: +0: e0 83 00 00 lq r4,0\(r3\) # binutils: power4.d: +4: e0 83 00 00 lq r4,0\(r3\) -:lq RT,dqPlusRaOrZeroAddress, BITS_0_3 is $(NOTVLE) & OP=56 & RT & Dp & RA & DQs & dqPlusRaOrZeroAddress & BITS_0_3 & regp [regpset = Dp+1;] { +:lq RT,dqPlusRaOrZeroAddress is $(NOTVLE) & OP=56 & RT & Dp & RA & DQs & dqPlusRaOrZeroAddress & regp [regpset = Dp+1;] { ea:$(REGISTER_SIZE) = RA + sext(DQs:2 << 4); @if ENDIAN == "big" RT = *:$(REGISTER_SIZE) ea; From 2f88e9c5f7bf32389ec5bcd0dd07a7f76eb6bb8f Mon Sep 17 00:00:00 2001 From: b Date: Sun, 24 Nov 2024 14:44:21 +0100 Subject: [PATCH 3/4] Reusing dqPlusRaOrZeroAddress for EA calculation --- Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc index 7e6e58203c0..68d16db46c6 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc @@ -1610,7 +1610,7 @@ define pcodeop stdcixOp; # binutils: power4.d: +0: e0 83 00 00 lq r4,0\(r3\) # binutils: power4.d: +4: e0 83 00 00 lq r4,0\(r3\) :lq RT,dqPlusRaOrZeroAddress is $(NOTVLE) & OP=56 & RT & Dp & RA & DQs & dqPlusRaOrZeroAddress & regp [regpset = Dp+1;] { - ea:$(REGISTER_SIZE) = RA + sext(DQs:2 << 4); + ea:$(REGISTER_SIZE) = dqPlusRaOrZeroAddress; @if ENDIAN == "big" RT = *:$(REGISTER_SIZE) ea; regp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)); From fc04c37a1a66dd245ee39d82dea0e276fd14d5d4 Mon Sep 17 00:00:00 2001 From: b Date: Sun, 24 Nov 2024 14:55:06 +0100 Subject: [PATCH 4/4] Fix PPC STQ negative offsets --- Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc index 68d16db46c6..6ed52057f1c 100644 --- a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc +++ b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc @@ -1925,8 +1925,8 @@ define pcodeop stfdpOp; # binutils: power4.d: +58: f8 c7 ff f2 stq r6,-16\(r7\) # binutils: power4.d: +5c: f8 c7 80 02 stq r6,-32768\(r7\) # binutils: power4.d: +60: f8 c7 7f f2 stq r6,32752\(r7\) -:stq RS,RA_OR_ZERO,DS is $(NOTVLE) & OP=62 & RS & Dp & RA_OR_ZERO & DS & BITS_0_1=2 & regp [regpset = Dp+1;] { - ea:$(REGISTER_SIZE) = RA_OR_ZERO + sext(DS:2 << 2); +:stq RS,dsPlusRaOrZeroAddress is $(NOTVLE) & OP=62 & RS & Dp & dsPlusRaOrZeroAddress & BITS_0_1=2 & regp [regpset = Dp+1;] { + ea:$(REGISTER_SIZE) = dsPlusRaOrZeroAddress; @if ENDIAN == "big" *:$(REGISTER_SIZE) ea = RS; *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE)) = regp;