You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
I am relatively new to Verilog and FPGA development, and I find your work in this field particularly inspiring.
Currently, I am encountering some challenges with the synthesis of your code. Unfortunately, the synthesis process fails, and I'm presented with several error messages. I have attached images of these errors for your reference.
I am very interested in successfully implementing the HDMI interface as part of my learning journey. I would greatly appreciate any guidance or advice you could provide to help me resolve these issues.
The text was updated successfully, but these errors were encountered:
Hi, thanks for checking in. Always great to hear that this project is actively used 🙂
All the repos in this organization are meant to be built with hdlmake which pulls the necessary dependency repos, see in Manifest.py. If you don't want to use hdlmake you can just manually add the sawtooth file to your project from here: https://github.com/hdl-util/sound
Sameer , thanks for the great project.
I am relatively new to Verilog and FPGA development, and I find your work in this field particularly inspiring.
Currently, I am encountering some challenges with the synthesis of your code. Unfortunately, the synthesis process fails, and I'm presented with several error messages. I have attached images of these errors for your reference.
I am very interested in successfully implementing the HDMI interface as part of my learning journey. I would greatly appreciate any guidance or advice you could provide to help me resolve these issues.
The text was updated successfully, but these errors were encountered: