tCL tCWL dependency

[ghost]

Currently, tCWL depends on tCL as the following is stated:

Timing	Safe	Tight	Extreme
tCWL1	tCL	tCL - 1	tCL - 2

The problem is that tCL is changed after tCWL is tuned. Then there is no mention of tuning tCWL again. To fix this, we can simply tune tCL before tCWL but i'm not sure if that will have a negative outcome.

I'm open to discussion. What do you think of this solution?

[derinsh]

I just came to state the same observation. I think there should be a reminder at the tCL step to go back. According to this setting tCWL to tCL comes with low risk, but I cannot judge on that.

But your idea of tuning tCWL right after tCL seems more logical if it indeed is that easy.

[ghost]

I think it should be the other way around (placing the tCL step before that table where the tCWL recommendations are in step 3) since the intention is to tune secondaries to speed up memory testing.

Are there any disadvantages to tuning tCL as the first step generally speaking?

[claudiubalogh]

I just noticed the same. I chose to set tCWL relative to the XMP value for tCL, in my case XMP tCL = 14, so I set tCWL = 12, then run TM5+OCCT VRAM, OCCT SSE, OCCT AVX and Prime95 successfully. I guess if it had failed I would've just bumped tCWL up and run the tests again.

[IslamGhunym]

perhaps I am late to this issue, but the whole timing tuning arrangement in this guide isn't right to put it in clear words, and there are misleading steps to not achieve good overclocking too, but I decided not to help improving this guide further when I got screwed once by the people running it. the drama was about me configuring a system with a certain timing configuration against another using Micron E dies to show off that tRTP must be half tWR. previously some others said it as it is mentioned in the official micron sheet, but since they wanted a prove for it, I did it, and provided an image showing the instability with over 6 hours of tests when tWR is loosened. after that they immediately edited and corrected the guide and gave credits for someone else! (Junkman) who didn't pay any efforts for that, and archived my efforts and didn't value them. I am not asking for anything, but some thanks / appreciation would have been nice, and it won't hurt anyone. If they gave no credits/thanks to anyone that would have been fine to me.

Anyway, here are my recommendations for a more proper tuning (try to understand it yourself I won't be detailing much is just a reply and I won't include everything):

Intel
1Core
2cache
3Mem Hz (CR2)
4CR1
5Mem Hz (retuning with CR1)
6 choose CR1 or CR2 depending on results prioritizing 200+ MT/s higher than CR1
7 tRRDS/L
8 tFAW
9 tRFC (check for freezes and BSOD after hours of system shutdown up to 5 times for secret reasons)
10 tCL (set tCWL=tCL if tCL is even and tCWL= tCL-1 by one clk if tCL is odd)
11 RTL/I-OL
12 tRCD/tRP
13 tWR/tRTP (if tRTP=6/7, accept tRCD/tRP - if tRTP>7 add 1 clk to tRCD/tRP and try tRTP 7 failure again means u need to revert back to lower tRCD/tRP and accept tRTP>7 this is only for micron rev E. different rules apply for other ICs, but applies similar method I won't mention loads of details.
14 tCWL
15 tWRRD-sg/dg
16 tRDRD
17 tREFI/REFIx9
18 tRAS
19 tWRWR
20 tRDWR (check for freezes outside memory testers after hours of shutdown system up to 5 times)
21 tCKE
22 tXP
23 tXPDLL

AMD
Hz
CR
Hz
CR
tRRDS/L
tFAW
tRFC
tCL
tRCD
tRP
enable gear down mode if CR2 was chosen while tRP and tRCD are even (test to verify performance difference if tRP/RCD were odd as they will get higher to even number)
tWR/tRTP same as Intel way with some differences I won't mention
tRCD
tRP
tWTRS/L
tRDRDSCL
tWRWRSCL
tCWL (tWRRD<9)
rest of territories
tRAS
tRC

[tehybel]

@IslamGhunym Nice order. I adapted it here, I hope that's OK with you? Otherwise let me know, also if you want me to credit you some other way than I did.

Integralfx: feel free to copy or adapt what I wrote as well, if you feel it can be used to resolve this GitHub issue :-)