From 8350262f87dd4a14c35bf32f9f83b7a819ed9f66 Mon Sep 17 00:00:00 2001 From: Monika Singh Date: Mon, 12 Aug 2024 17:42:14 +0000 Subject: [PATCH 01/15] Update libraries to LTS version --- FreeRTOS-Plus/Source/AWS/device-defender | 2 +- FreeRTOS-Plus/Source/AWS/device-shadow | 2 +- FreeRTOS-Plus/Source/AWS/fleet-provisioning | 2 +- FreeRTOS-Plus/Source/AWS/jobs | 2 +- FreeRTOS-Plus/Source/AWS/sigv4 | 2 +- .../Source/Application-Protocols/coreHTTP | 2 +- .../Source/Application-Protocols/coreMQTT | 2 +- .../Source/Application-Protocols/coreSNTP | 2 +- .../Source/FreeRTOS-Cellular-Interface | 2 +- FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP | 2 +- .../Source/Utilities/backoff_algorithm | 2 +- FreeRTOS-Plus/Source/coreJSON | 2 +- FreeRTOS-Plus/Source/corePKCS11 | 2 +- FreeRTOS/Source | 2 +- manifest.yml | 28 +++++++++---------- 15 files changed, 28 insertions(+), 28 deletions(-) diff --git a/FreeRTOS-Plus/Source/AWS/device-defender b/FreeRTOS-Plus/Source/AWS/device-defender index 9dbf7ba0d4b..7059e199149 160000 --- a/FreeRTOS-Plus/Source/AWS/device-defender +++ b/FreeRTOS-Plus/Source/AWS/device-defender @@ -1 +1 @@ -Subproject commit 9dbf7ba0d4bae6c8cabdb7732289942f5a23507c +Subproject commit 7059e199149a540471b484b710a51fc665636f22 diff --git a/FreeRTOS-Plus/Source/AWS/device-shadow b/FreeRTOS-Plus/Source/AWS/device-shadow index 2f16e7c12d9..268a5a276d3 160000 --- a/FreeRTOS-Plus/Source/AWS/device-shadow +++ b/FreeRTOS-Plus/Source/AWS/device-shadow @@ -1 +1 @@ -Subproject commit 2f16e7c12d9a585d2aa9071e53ed8a346d076005 +Subproject commit 268a5a276d3c3f451575b5a042b4e8ad53f134b6 diff --git a/FreeRTOS-Plus/Source/AWS/fleet-provisioning b/FreeRTOS-Plus/Source/AWS/fleet-provisioning index daf174d3b93..a97d53af335 160000 --- a/FreeRTOS-Plus/Source/AWS/fleet-provisioning +++ b/FreeRTOS-Plus/Source/AWS/fleet-provisioning @@ -1 +1 @@ -Subproject commit daf174d3b934d550492e775650137b8bb1b63545 +Subproject commit a97d53af335f135c6ee9d608a3e80be8a3009a89 diff --git a/FreeRTOS-Plus/Source/AWS/jobs b/FreeRTOS-Plus/Source/AWS/jobs index f1c3bd68298..3ce91f56427 160000 --- a/FreeRTOS-Plus/Source/AWS/jobs +++ b/FreeRTOS-Plus/Source/AWS/jobs @@ -1 +1 @@ -Subproject commit f1c3bd68298a9c997f1709f48e61ca3f22dc8ed0 +Subproject commit 3ce91f56427653705891a8668568cb247b97905f diff --git a/FreeRTOS-Plus/Source/AWS/sigv4 b/FreeRTOS-Plus/Source/AWS/sigv4 index 9d9f95a95ac..68e0364a883 160000 --- a/FreeRTOS-Plus/Source/AWS/sigv4 +++ b/FreeRTOS-Plus/Source/AWS/sigv4 @@ -1 +1 @@ -Subproject commit 9d9f95a95acdf3e1428df803cec79e65e2da81f0 +Subproject commit 68e0364a883f0ededb6b43af9e271e469065dac3 diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP b/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP index dc94df08e48..12adee81dde 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreHTTP @@ -1 +1 @@ -Subproject commit dc94df08e4819471b73858b863fddd50c0ca38c6 +Subproject commit 12adee81ddef588abada91672b34fd997b2a27ac diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT b/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT index 238350a8443..2beef047253 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT @@ -1 +1 @@ -Subproject commit 238350a844336c6dea7e3aa50ecab729bf27e288 +Subproject commit 2beef04725328923e05e576b884212d53ec97af7 diff --git a/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP b/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP index c5face5fa3c..b492c223cdb 160000 --- a/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP +++ b/FreeRTOS-Plus/Source/Application-Protocols/coreSNTP @@ -1 +1 @@ -Subproject commit c5face5fa3cc3c37b8216c35d03d323373e89a85 +Subproject commit b492c223cdbebfb9335166d0e6fc47e93a94de75 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface index f1097fb3b1c..b7494dcdd40 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface +++ b/FreeRTOS-Plus/Source/FreeRTOS-Cellular-Interface @@ -1 +1 @@ -Subproject commit f1097fb3b1c69120a0a0541c6a858830b3f4e762 +Subproject commit b7494dcdd40aab2fed0bb992760e6cdeba0543d5 diff --git a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP index f940d75a139..abcb94c8768 160000 --- a/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP +++ b/FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP @@ -1 +1 @@ -Subproject commit f940d75a1393ba976edfcce118d4d97dc234322d +Subproject commit abcb94c8768532a6cae3c39ffe37602640992a28 diff --git a/FreeRTOS-Plus/Source/Utilities/backoff_algorithm b/FreeRTOS-Plus/Source/Utilities/backoff_algorithm index 0b4f9920fa2..3cc0bf8c4d4 160000 --- a/FreeRTOS-Plus/Source/Utilities/backoff_algorithm +++ b/FreeRTOS-Plus/Source/Utilities/backoff_algorithm @@ -1 +1 @@ -Subproject commit 0b4f9920fa28faba02815521f10b31a3443eaf59 +Subproject commit 3cc0bf8c4d41d7cd7aa2f1ded5075c87bf6b2bbb diff --git a/FreeRTOS-Plus/Source/coreJSON b/FreeRTOS-Plus/Source/coreJSON index b92c8cd9cdb..e3b7663f639 160000 --- a/FreeRTOS-Plus/Source/coreJSON +++ b/FreeRTOS-Plus/Source/coreJSON @@ -1 +1 @@ -Subproject commit b92c8cd9cdba790e46eab05f7a620b0f15c5be69 +Subproject commit e3b7663f6392d8c10e8db57506ec37e4801b145a diff --git a/FreeRTOS-Plus/Source/corePKCS11 b/FreeRTOS-Plus/Source/corePKCS11 index 59875a9aa3f..a923b213d33 160000 --- a/FreeRTOS-Plus/Source/corePKCS11 +++ b/FreeRTOS-Plus/Source/corePKCS11 @@ -1 +1 @@ -Subproject commit 59875a9aa3f08a95eb8cdc0ba345b38dc49134ab +Subproject commit a923b213d33c6538e92ba3c7971b2d859f881afb diff --git a/FreeRTOS/Source b/FreeRTOS/Source index 4d4f8d0d50b..dbf70559b27 160000 --- a/FreeRTOS/Source +++ b/FreeRTOS/Source @@ -1 +1 @@ -Subproject commit 4d4f8d0d50bedc37e1d07c96aded7d2bc20f0d6c +Subproject commit dbf70559b27d39c1fdb68dfb9a32140b6a6777a0 diff --git a/manifest.yml b/manifest.yml index 931b1b06910..d75b6578bb3 100644 --- a/manifest.yml +++ b/manifest.yml @@ -5,42 +5,42 @@ license: "MIT" dependencies: - name: "FreeRTOS-Kernel" - version: "4d4f8d0d5" + version: "V11.1.0" repository: type: "git" url: "https://github.com/FreeRTOS/FreeRTOS-Kernel.git" path: "FreeRTOS/Source" - name: "FreeRTOS-Plus-TCP" - version: "V4.1.0" + version: "V4.2.2" repository: type: "git" url: "https://github.com/FreeRTOS/FreeRTOS-Plus-TCP.git" path: "FreeRTOS-Plus/Source/FreeRTOS-Plus-TCP" - name: "coreJSON" - version: "b92c8cd" + version: "v3.3.0" repository: type: "git" url: "https://github.com/FreeRTOS/coreJSON.git" path: "FreeRTOS-Plus/Source/coreJSON" - name: "sigv4" - version: "9d9f95a" + version: "v1.3.0" repository: type: "git" url: "https://github.com/aws/SigV4-for-AWS-IoT-embedded-sdk.git" path: "FreeRTOS-Plus/Source/AWS/sigv4" - name: "coreHTTP" - version: "dc94df0" + version: "v3.1.1" repository: type: "git" url: "https://github.com/FreeRTOS/coreHTTP.git" path: "FreeRTOS-Plus/Source/Application-Protocols/coreHTTP" - name: "coreMQTT" - version: "238350a" + version: "v2.3.1" repository: type: "git" url: "https://github.com/FreeRTOS/coreMQTT.git" @@ -54,28 +54,28 @@ dependencies: path: "FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent" - name: "corePKCS11" - version: "59875a9" + version: "v3.6.1" repository: type: "git" url: "https://github.com/FreeRTOS/corePKCS11.git" path: "FreeRTOS-Plus/Source/corePKCS11" - name: "device-defender" - version: "9dbf7ba" + version: "v1.4.0" repository: type: "git" url: "https://github.com/aws/Device-Defender-for-AWS-IoT-embedded-sdk.git" path: "FreeRTOS-Plus/Source/AWS/device-defender" - name: "device-shadow" - version: "2f16e7c" + version: "v1.4.1" repository: type: "git" url: "https://github.com/aws/Device-Shadow-for-AWS-IoT-embedded-sdk.git" path: "FreeRTOS-Plus/Source/AWS/device-shadow" - name: "jobs" - version: "f1c3bd6" + version: "v1.5.1" repository: type: "git" url: "https://github.com/aws/Jobs-for-AWS-IoT-embedded-sdk.git" @@ -110,7 +110,7 @@ dependencies: path: "FreeRTOS-Plus/ThirdParty/libslirp" - name: "backoffAlgorithm" - version: "0b4f992" + version: "v1.4.1" repository: type: "git" url: "https://github.com/FreeRTOS/backoffAlgorithm" @@ -124,7 +124,7 @@ dependencies: path: "FreeRTOS-Plus/Source/AWS/ota" - name: "coreSNTP" - version: "c5face5" + version: "v1.3.1" repository: type: "git" url: "https://github.com/FreeRTOS/coreSNTP" @@ -145,7 +145,7 @@ dependencies: path: "FreeRTOS/Demo/ThirdParty/Partner-Supported-Demos" - name: "FreeRTOS-Cellular-Interface" - version: "f1097fb" + version: "v1.4.0" repository: type: "git" url: "https://github.com/FreeRTOS/FreeRTOS-Cellular-Interface.git" @@ -173,7 +173,7 @@ dependencies: path: "FreeRTOS-Plus/Source/FreeRTOS-Cellular-Modules/sara-r4" - name: "fleet-provisioning" - version: "daf174d" + version: "v1.2.1" repository: type: "git" url: "https://github.com/aws/Fleet-Provisioning-for-AWS-IoT-embedded-sdk.git" From dc7205e172999fb745aaf91e880008734c1a5b8e Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Fri, 24 May 2024 08:27:01 +0200 Subject: [PATCH 02/15] Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c: remove unused g_ulBase (#1224) In FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c the extern definition of g_ulBase ist not used, so remove it. Also move _heap_bottom and _heap_top to where they are used in syscall.c. Signed-off-by: Florian La Roche --- FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c index d12a7dec8d4..4d0ef93aaab 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c @@ -45,11 +45,6 @@ typedef struct UART_t #define UART_CTRL_TX_EN ( 1 << 0 ) #define UART_CTRL_RX_EN ( 1 << 1 ) - -extern unsigned long _heap_bottom; -extern unsigned long _heap_top; -extern unsigned long g_ulBase; - /** * @brief initializes the UART emulated hardware */ @@ -85,6 +80,9 @@ FILE *const stdout = &__stdio; #else +extern unsigned long _heap_bottom; +extern unsigned long _heap_top; + static char * heap_end = ( char * ) &_heap_bottom; /** @@ -150,6 +148,7 @@ void * _sbrk( int incr ) return prev_heap_end; } + void _close( int fd ) { ( void ) fd; From d7226b05b7c694ba590414d7c7a8134aab2f6ec8 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Fri, 24 May 2024 09:26:03 +0200 Subject: [PATCH 03/15] Demo/CORTEX_MPS2_QEMU_IAR_GCC add path to IMAGE and remove mapfile (#1223) For Demo/CORTEX_MPS2_QEMU_IAR_GCC gcc Makefile: - simplify IMAGE var to already include full path - clean target also removes mapfile Signed-off-by: Florian La Roche Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com> --- .../CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile index c79414fe948..eec39ba2957 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile @@ -1,5 +1,5 @@ OUTPUT_DIR := ./output -IMAGE := RTOSDemo.out +IMAGE := $(OUTPUT_DIR)/RTOSDemo.out # The directory that contains the /source and /demo sub directories. FREERTOS_ROOT = ./../../../.. @@ -35,7 +35,7 @@ SOURCE_FILES += $(KERNEL_DIR)/portable/MemMang/heap_4.c SOURCE_FILES += $(KERNEL_DIR)/portable/GCC/ARM_CM3/port.c # -# Common demo files for the "full" build, as opposed to the "blinky" build - +# Common demo files for the "full" build, as opposed to the "blinky" build - # these files are build by all the FreeRTOS kernel demos. # DEMO_ROOT = $(FREERTOS_ROOT)/Demo @@ -95,27 +95,27 @@ DEP_FILES := $(SOURCE_FILES:%.c=$(OUTPUT_DIR)/%.d) DEP_FILES_NO_PATH = $(notdir $(DEP_FILES)) DEP_OUTPUT = $(DEP_FILES_NO_PATH:%.d=$(OUTPUT_DIR)/%.d) -all: $(OUTPUT_DIR)/$(IMAGE) +all: $(IMAGE) %.o : %.c $(OUTPUT_DIR)/%.o : %.c $(OUTPUT_DIR)/%.d Makefile $(CC) $(CFLAGS) -c $< -o $@ -$(OUTPUT_DIR)/$(IMAGE): ./mps2_m3.ld $(OBJS_OUTPUT) Makefile +$(IMAGE): ./mps2_m3.ld $(OBJS_OUTPUT) Makefile @echo "" @echo "" @echo "--- Final linking ---" @echo "" $(LD) $(OBJS_OUTPUT) $(CFLAGS) -Xlinker --gc-sections -Xlinker -T ./mps2_m3.ld \ -Xlinker -Map=$(OUTPUT_DIR)/RTOSDemo.map -specs=nano.specs \ - -specs=nosys.specs -specs=rdimon.specs -o $(OUTPUT_DIR)/$(IMAGE) - $(SIZE) $(OUTPUT_DIR)/$(IMAGE) + -specs=nosys.specs -specs=rdimon.specs -o $(IMAGE) + $(SIZE) $(IMAGE) $(DEP_OUTPUT): include $(wildcard $(DEP_OUTPUT)) clean: - rm -f $(OUTPUT_DIR)/$(IMAGE) $(OUTPUT_DIR)/*.o $(OUTPUT_DIR)/*.d + rm -f $(IMAGE) $(OUTPUT_DIR)/RTOSDemo.map $(OUTPUT_DIR)/*.o $(OUTPUT_DIR)/*.d #use "make print-[VARIABLE_NAME] to print the value of a variable generated by #this makefile. From 95a3e87595367bcd59fdcb2e3603692362808be6 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Tue, 4 Jun 2024 16:38:16 +0200 Subject: [PATCH 04/15] MPS2_AN385 improvements (#1225) * MPS2_AN385 improvements Sync various MPS2_AN385 CORTEX-M3 QEMU targets and improve their Makefiles and cleanup gcc support: - FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2: - Makefile - output image size after linking - move -nostartfiles from compiler to linker flags - modernize compiler warning flags - add --gc-sections to linker flags - TCPEchoClient_SingleTasks.c: fix compiler warnings - main.c: fix compiler warnings (remove unused code) - main_networking.c - remove ipLOCAL_MAC_ADDRESS (unknown) - fix compiler warnings about unused params - startup.c: main(void), remove unused includes, silence unused params - syscalls.c: remove unused defines, silence unused params, more compact _sbrk() - FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc: - Makefile - CFLAGS/LDFLAGS in more readable lines - move -nostartfiles to linker flags - comment out -specs=rdimon.specs as it is not needed - startup_gcc.c: fix typo in comment, remove unused uart code - FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC - Makefile - after compilation output size of image - remove -DQEMU_SOC_MPS2, not needed - update many CFLAGS/LDFLAGS settings to more modern gcc/source - -ffunction-sections -fdata-sections is moved to CFLAGS - startup.c: sync with other ports - syscall.c: _write(): param buf is not unused, silence unused params Signed-off-by: Florian La Roche * remove ipLOCAL_MAC_ADDRESS completely and fix formatting errors remove ipLOCAL_MAC_ADDRESS completely and fix formatting errors Signed-off-by: Florian La Roche --- .../FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile | 34 +++++++++++-------- .../TCPEchoClient_SingleTasks.c | 23 +++++++++---- .../FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c | 6 +--- .../main_networking.c | 10 ++++-- .../startup.c | 27 ++++++++++----- .../syscalls.c | 28 +++++++-------- .../build/gcc/Makefile | 23 ++++++++----- .../build/gcc/startup_gcc.c | 18 +--------- .../Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile | 26 +++++--------- .../init/startup.c | 14 +++++--- .../Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c | 2 +- .../CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c | 20 +++++++---- 12 files changed, 122 insertions(+), 109 deletions(-) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile index fdfe7c74103..e51a46f79da 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile @@ -1,4 +1,5 @@ CC = arm-none-eabi-gcc +SIZE = arm-none-eabi-size BIN := freertos_tcp_mps2_demo.axf BUILD_DIR := build @@ -51,30 +52,33 @@ SOURCE_FILES += ${FREERTOS_TCP}/source/portable/BufferManagement/BufferAllocatio SOURCE_FILES += ${FREERTOS_TCP}/source/portable/NetworkInterface/MPS2_AN385/NetworkInterface.c SOURCE_FILES += ${FREERTOS_TCP}/source/portable/NetworkInterface/MPS2_AN385/ether_lan9118/smsc9220_eth_drv.c -DEFINES := -DQEMU_SOC_MPS2 -DHEAP3 - -LDFLAGS = -T mps2_m3.ld -specs=nano.specs --specs=rdimon.specs -lc -lrdimon -LDFLAGS += -Xlinker -Map=${BUILD_DIR}/output.map - -CFLAGS += -nostartfiles -mthumb -mcpu=cortex-m3 -Wno-error=implicit-function-declaration -CFLAGS += -Wno-builtin-declaration-mismatch -Werror +DEFINES := -DHEAP3 +CPPFLAGS += $(DEFINES) +CFLAGS += -mthumb -mcpu=cortex-m3 ifeq ($(DEBUG), 1) - CFLAGS += -ggdb3 -Og + CFLAGS += -g3 -Og -ffunction-sections -fdata-sections else - CFLAGS += -O3 + CFLAGS += -Os -ffunction-sections -fdata-sections endif - CFLAGS += -fstrict-aliasing -Wstrict-aliasing -Wno-error=address-of-packed-member +CFLAGS += -MMD +CFLAGS += -Wall -Wextra -Wshadow +#CFLAGS += -Wpedantic -fanalyzer +#CFLAGS += -flto +CFLAGS += $(INCLUDE_DIRS) -OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) +LDFLAGS = -T mps2_m3.ld +LDFLAGS += -Xlinker -Map=${BUILD_DIR}/output.map +LDFLAGS += -Xlinker --gc-sections +LDFLAGS += -nostartfiles -specs=nano.specs -specs=nosys.specs -specs=rdimon.specs -CPPFLAGS += $(DEFINES) -CFLAGS += $(INCLUDE_DIRS) +OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) .PHONY: clean $(BUILD_DIR)/$(BIN) : $(OBJ_FILES) - $(CC) -ffunction-sections -fdata-sections $(CFLAGS) $(LDFLAGS) $+ -o $(@) + $(CC) $(CFLAGS) $(LDFLAGS) $+ -o $(@) + $(SIZE) $(@) %.d: %.c @set -e; rm -f $@; \ @@ -87,7 +91,7 @@ INCLUDES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.d) ${BUILD_DIR}/%.o : %.c Makefile -mkdir -p $(@D) - $(CC) $(CPPFLAGS) $(CFLAGS) -MMD -c $< -o $@ + $(CC) $(CFLAGS) $(CPPFLAGS) -c $< -o $@ clean: -rm -rf build diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c index 41b9ed09332..477ba4c1c07 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/TCPEchoClient_SingleTasks.c @@ -206,10 +206,10 @@ lStringLength = prvCreateTxData( pcTransmittedString, echoBUFFER_SIZES ); /* Add in some unique text at the front of the string. */ - sprintf( pcTransmittedString, "TxRx message number %u", ulTxCount ); + sprintf( pcTransmittedString, "TxRx message number %lu", ulTxCount ); ulTxCount++; - printf( "sending data to the echo server size %d original %d\n", + printf( "sending data to the echo server size %ld original %d\n", lStringLength, echoBUFFER_SIZES ); /* Send the string to the socket. */ @@ -217,7 +217,7 @@ ( void * ) pcTransmittedString, /* The data being sent. */ lStringLength, /* The length of the data being sent. */ 0 ); /* No flags. */ - printf( "FreeRTOS_send returned...transmitted %d\n", + printf( "FreeRTOS_send returned...transmitted %ld\n", lTransmitted ); if( lTransmitted < 0 ) @@ -398,15 +398,24 @@ #if ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) eDHCPCallbackAnswer_t xApplicationDHCPHook( eDHCPCallbackPhase_t eDHCPPhase, uint32_t ulIPAddress ) + { + ( void ) eDHCPPhase; + ( void ) ulIPAddress; + + return eDHCPContinue; + } #else /* ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) */ eDHCPCallbackAnswer_t xApplicationDHCPHook_Multi( eDHCPCallbackPhase_t eDHCPPhase, struct xNetworkEndPoint * pxEndPoint, IP_Address_t * pxIPAddress ) + { + ( void ) eDHCPPhase; + ( void ) pxEndPoint; + ( void ) pxIPAddress; + + return eDHCPContinue; + } #endif /* ( ipconfigIPv4_BACKWARD_COMPATIBLE == 1 ) */ - { - /* Provide a stub for this function. */ - return eDHCPContinue; - } #endif /* if ( ipconfigUSE_DHCP_HOOK != 0 )*/ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c index cb17a6bf47c..ec5f5650c85 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main.c @@ -40,9 +40,7 @@ void main_tcp_echo_client_tasks( void ); void vApplicationIdleHook( void ); void vApplicationTickHook( void ); -extern void initialise_monitor_handles( void ); - -int main() +int main( void ) { main_tcp_echo_client_tasks(); return 0; @@ -84,8 +82,6 @@ void vApplicationStackOverflowHook( TaskHandle_t pxTask, void vApplicationIdleHook( void ) { - volatile size_t xFreeHeapSpace; - /* This is just a trivial example of an idle hook. It is called on each * cycle of the idle task. It must *NOT* attempt to block. In this case the * idle task just queries the amount of FreeRTOS heap that remains. See the diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c index 5af2c81b20e..60e5ca36402 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c @@ -180,8 +180,6 @@ void main_tcp_echo_client_tasks( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ @@ -224,6 +222,10 @@ BaseType_t xTasksAlreadyCreated = pdFALSE; uint32_t ulDNSServerAddress; char cBuffer[ 16 ]; + #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) + ( void ) pxEndPoint; + #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + /* If the network has just come up...*/ if( eNetworkEvent == eNetworkUp ) { @@ -335,6 +337,10 @@ static void prvMiscInitialisation( void ) { BaseType_t xReturn; + #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) + ( void ) pxEndPoint; + #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + /* Determine if a name lookup is for this node. Two names are given * to this node: that returned by pcApplicationHostnameHook() and that set * by mainDEVICE_NICK_NAME. */ diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c index 3dcec37f443..72a269c07eb 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/startup.c @@ -28,15 +28,14 @@ #include #include #include -#include "CMSIS/CMSDK_CM3.h" -#include "CMSIS/core_cm3.h" extern void vPortSVCHandler( void ); extern void xPortPendSVHandler( void ); extern void xPortSysTickHandler( void ); -extern void uart_init(); -extern int main(); +extern void uart_init( void ); +extern int main( void ); +void _start( void ); void __attribute__( ( weak ) ) EthernetISR( void ); extern uint32_t _estack, _sidata, _sdata, _edata, _sbss, _ebss; @@ -63,7 +62,6 @@ void Reset_Handler( void ) } /* jump to board initialisation */ - void _start( void ); _start(); } @@ -96,6 +94,16 @@ void prvGetRegistersFromStack( uint32_t * pulFaultStackAddress ) for( ; ; ) { } + + /* Remove the warning about unused variables. */ + ( void ) r0; + ( void ) r1; + ( void ) r2; + ( void ) r3; + ( void ) r12; + ( void ) lr; + ( void ) pc; + ( void ) psr; } static void Default_Handler( void ) __attribute__( ( naked ) ); @@ -114,7 +122,8 @@ void Default_Handler( void ) "NVIC_INT_CTRL_CONST: .word 0xe000ed04\n" ); } -static void HardFault_Handler( void ) __attribute__( ( naked ) ); + +static void Default_Handler2( void ) __attribute__( ( naked ) ); void Default_Handler2( void ) { __asm volatile @@ -158,7 +167,7 @@ void Default_Handler6( void ) } } -const uint32_t * isr_vector[] __attribute__( ( section( ".isr_vector" ) ) ) = +const uint32_t * const isr_vector[] __attribute__( ( section( ".isr_vector" ) ) ) = { ( uint32_t * ) &_estack, ( uint32_t * ) &Reset_Handler, /* Reset -15 */ @@ -195,7 +204,7 @@ const uint32_t * isr_vector[] __attribute__( ( section( ".isr_vector" ) ) ) = void _start( void ) { uart_init(); - main( 0, 0 ); + main(); exit( 0 ); } @@ -212,4 +221,6 @@ __attribute__( ( naked ) ) void exit( int status ) "bkpt 0xab\n" "end: b end\n" ); + + ( void ) status; } diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c index bfa97f3b8e8..6e5425db004 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/syscalls.c @@ -38,24 +38,21 @@ typedef struct UART_t volatile uint32_t BAUDDIV; } UART_t; -#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) +#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) #define UART_DR( baseaddr ) ( *( unsigned int * ) ( baseaddr ) ) -#define UART_STATE_TXFULL ( 1 << 0 ) -#define UART_CTRL_TX_EN ( 1 << 0 ) -#define UART_CTRL_RX_EN ( 1 << 1 ) +#define UART_CTRL_TX_EN ( 1 << 0 ) extern unsigned long _heap_bottom; extern unsigned long _heap_top; -extern unsigned long g_ulBase; -static void * heap_end = 0; +static char * heap_end = ( char * ) &_heap_bottom; /** * @brief initializes the UART emulated hardware */ -void uart_init() +void uart_init( void ) { UART0_ADDR->BAUDDIV = 16; UART0_ADDR->CTRL = UART_CTRL_TX_EN; @@ -68,6 +65,7 @@ void uart_init() */ int _fstat( int file ) { + ( void ) file; return 0; } @@ -80,6 +78,9 @@ int _read( int file, char * buf, int len ) { + ( void ) file; + ( void ) buf; + ( void ) len; return -1; } @@ -97,6 +98,8 @@ int _write( int file, { int todo; + ( void ) file; + for( todo = 0; todo < len; todo++ ) { UART_DR( UART0_ADDR ) = *buf++; @@ -113,16 +116,9 @@ int _write( int file, */ void * _sbrk( int incr ) { - char * prev_heap_end; - - if( heap_end == 0 ) - { - heap_end = ( void * ) &_heap_bottom; - } - - prev_heap_end = heap_end; + void * prev_heap_end = heap_end; - if( ( heap_end + incr ) > ( void * ) &_heap_top ) + if( ( heap_end + incr ) > ( char * ) &_heap_top ) { return ( void * ) -1; } diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile index eec39ba2957..f268700e4f2 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/Makefile @@ -9,13 +9,20 @@ LD = arm-none-eabi-gcc SIZE = arm-none-eabi-size MAKE = make - -CFLAGS += $(INCLUDE_DIRS) -nostartfiles -ffreestanding -mthumb -mcpu=cortex-m3 \ - -Wall -Wextra -g3 -Os -ffunction-sections -fdata-sections \ - -MMD -MP -MF"$(@:%.o=%.d)" -MT $@ - -#CFLAGS += -Wpedantic -Wshadow -fanalyzer +CFLAGS += -ffreestanding -mthumb -mcpu=cortex-m3 +CFLAGS += -Wall -Wextra -Wshadow +CFLAGS += -g3 -Os -ffunction-sections -fdata-sections +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" -MT $@ +#CFLAGS += -std=c99 +#CFLAGS += -Wpedantic -fanalyzer #CFLAGS += -flto +CFLAGS += $(INCLUDE_DIRS) + +LDFLAGS = -T ./mps2_m3.ld +LDFLAGS += -Xlinker -Map=$(OUTPUT_DIR)/RTOSDemo.map +LDFLAGS += -Xlinker --gc-sections +LDFLAGS += -nostartfiles +LDFLAGS += -specs=nano.specs -specs=nosys.specs # -specs=rdimon.specs # # Kernel build. @@ -106,9 +113,7 @@ $(IMAGE): ./mps2_m3.ld $(OBJS_OUTPUT) Makefile @echo "" @echo "--- Final linking ---" @echo "" - $(LD) $(OBJS_OUTPUT) $(CFLAGS) -Xlinker --gc-sections -Xlinker -T ./mps2_m3.ld \ - -Xlinker -Map=$(OUTPUT_DIR)/RTOSDemo.map -specs=nano.specs \ - -specs=nosys.specs -specs=rdimon.specs -o $(IMAGE) + $(LD) $(CFLAGS) $(LDFLAGS) $(OBJS_OUTPUT) -o $(IMAGE) $(SIZE) $(IMAGE) $(DEP_OUTPUT): diff --git a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c index 0b06e65fe29..fe6d2b1e997 100644 --- a/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c +++ b/FreeRTOS/Demo/CORTEX_MPS2_QEMU_IAR_GCC/build/gcc/startup_gcc.c @@ -27,22 +27,6 @@ #include #include -/* UART peripheral register addresses and bits. */ -#define UART0_ADDR ( ( UART_t * ) ( 0x40004000 ) ) -#define UART_DR( baseaddr ) ( *( uint32_t * ) ( baseaddr ) ) -#define UART_STATE( baseaddr ) ( *( uint32_t * ) ( baseaddr + 4 ) ) -#define UART_STATE_TXFULL ( 1 << 0 ) - -typedef struct UART_t -{ - volatile uint32_t DATA; - volatile uint32_t STATE; - volatile uint32_t CTRL; - volatile uint32_t INTSTATUS; - volatile uint32_t BAUDDIV; -} UART_t; - - /* FreeRTOS interrupt handlers. */ extern void vPortSVCHandler( void ); extern void xPortPendSVHandler( void ); @@ -99,7 +83,7 @@ void Reset_Handler( void ) } /* Variables used to store the value of registers at the time a hardfault - * occurs. These are volatile to try and prevent the compiler/linker optimising + * occurs. These are volatile to try and prevent the compiler/linker optimizing * them away as the variables never actually get used. */ volatile uint32_t r0; volatile uint32_t r1; diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile index 87fc5f0ac4e..82c018698d2 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/Makefile @@ -1,4 +1,5 @@ CC = arm-none-eabi-gcc +SIZE = arm-none-eabi-size BIN := RTOSDemo.axf BUILD_DIR := build @@ -34,33 +35,23 @@ INCLUDE_DIRS += -I$(FREERTOS_DIR)/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/C INCLUDE_DIRS += -I$(KERNEL_DIR)/include INCLUDE_DIRS += -I$(KERNEL_DIR)/portable/GCC/ARM_CM3_MPU -DEFINES := -DQEMU_SOC_MPS2 DEFINES := -DHEAP4 - CPPFLAGS += $(DEFINES) -CFLAGS += -mcpu=cortex-m3 -CFLAGS += -Wno-error=implicit-function-declaration -CFLAGS += -Wno-builtin-declaration-mismatch -CFLAGS += -Werror -CFLAGS += -Wall -CFLAGS += -Wextra -CFLAGS += -fstrict-aliasing -CFLAGS += -Wstrict-aliasing -CFLAGS += -Wno-error=address-of-packed-member -CFLAGS += -Wno-unused-parameter +CFLAGS += -mthumb -mcpu=cortex-m3 +CFLAGS += -Wall -Wextra -Wshadow -Wno-unused-parameter +#CFLAGS += -Wpedantic -fanalyzer CFLAGS += $(INCLUDE_DIRS) LDFLAGS = -T ./scripts/mps2_m3.ld -LDFLAGS += -mthumb - LDFLAGS += -Xlinker -Map=${BUILD_DIR}/output.map +LDFLAGS += -Xlinker --gc-sections LDFLAGS += -nostartfiles -nostdlib -nolibc -nodefaultlibs ifeq ($(DEBUG), 1) - CFLAGS += -ggdb3 -Og -save-temps=obj + CFLAGS += -g3 -Og -ffunction-sections -fdata-sections -save-temps=obj else - CFLAGS += -O3 + CFLAGS += -Os -ffunction-sections -fdata-sections endif ifeq ($(PICOLIBC), 1) @@ -73,7 +64,8 @@ OBJ_FILES := $(SOURCE_FILES:%.c=$(BUILD_DIR)/%.o) .PHONY: clean $(BUILD_DIR)/$(BIN) : $(OBJ_FILES) - $(CC) -ffunction-sections -fdata-sections $(LDFLAGS) $+ -o $(@) + $(CC) $(CFLAGS) $(LDFLAGS) $+ -o $(@) + $(SIZE) $(@) %.d: %.c @set -e; rm -f $@; \ diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c index 400583c127e..4a9752d4607 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/init/startup.c @@ -35,7 +35,9 @@ extern void vPortSVCHandler( void ); extern void xPortPendSVHandler( void ); extern void xPortSysTickHandler( void ); extern void uart_init( void ); -extern int main(); +extern int main( void ); + +void _start( void ); extern uint32_t _estack, _sidata, _sdata, _edata, _sbss, _ebss; @@ -61,13 +63,12 @@ void Reset_Handler( void ) } /* jump to board initialisation */ - void _start( void ); _start(); } void prvGetRegistersFromStack( uint32_t * pulFaultStackAddress ) { -/* These are volatile to try and prevent the compiler/linker optimising them +/* These are volatile to try and prevent the compiler/linker optimizing them * away as the variables never actually get used. If the debugger won't show the * values of the variables, make them global my moving their declaration outside * of this function. */ @@ -122,6 +123,7 @@ void Default_Handler( void ) "NVIC_INT_CTRL_CONST: .word 0xe000ed04\n" ); } + static void HardFault_Handler( void ) __attribute__( ( naked ) ); void HardFault_Handler( void ) { @@ -232,12 +234,12 @@ const uint32_t * const isr_vector[] __attribute__( ( section( ".isr_vector" ) ) void _start( void ) { uart_init(); - main( 0, 0 ); + main(); exit( 0 ); } __attribute__( ( naked ) ) -void exit( __attribute__( ( unused ) ) int status ) +void exit( int status ) { /* Force qemu to exit using ARM Semihosting */ __asm volatile ( @@ -250,4 +252,6 @@ void exit( __attribute__( ( unused ) ) int status ) "bkpt 0xab\n" "end: b end\n" ); + + ( void ) status; } diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c index d24cfa890ed..6481ac42969 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/main.c @@ -37,7 +37,7 @@ void vApplicationIdleHook( void ); void vApplicationTickHook( void ); -int main() +int main( void ) { app_main(); return 0; diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c index 4d0ef93aaab..d8fc48cb9d6 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/syscall.c @@ -69,7 +69,7 @@ void uart_init(void) int _uart_putc(char c, FILE *file) { - (void) file; + ( void ) file; UART_DR( UART0_ADDR ) = c; return (unsigned char) c; } @@ -90,8 +90,9 @@ static char * heap_end = ( char * ) &_heap_bottom; * @todo implement if necessary * */ -int _fstat( __attribute__( ( unused ) ) int file ) +int _fstat( int file ) { + ( void ) file; return 0; } @@ -100,10 +101,13 @@ int _fstat( __attribute__( ( unused ) ) int file ) * @todo implement if necessary * */ -int _read( __attribute__( ( unused ) ) int file, - __attribute__( ( unused ) ) char * buf, - __attribute__( ( unused ) ) int len ) +int _read( int file, + char * buf, + int len ) { + ( void ) file; + ( void ) buf; + ( void ) len; return -1; } @@ -115,12 +119,14 @@ int _read( __attribute__( ( unused ) ) int file, * @param [in] len length of the buffer * @returns the number of bytes written */ -int _write( __attribute__( ( unused ) ) int file, - __attribute__( ( unused ) ) char * buf, +int _write( int file, + char * buf, int len ) { int todo; + ( void ) file; + for( todo = 0; todo < len; todo++ ) { UART_DR( UART0_ADDR ) = *buf++; From 3be3080ebe7a9ddbe4fae58de4a0992c429da771 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Mon, 10 Jun 2024 08:02:23 +0200 Subject: [PATCH 05/15] Posix_GCC: update compiler options (#1227) Posix_GCC: update compiler options 1. Add to CFLAGS - add -O0 optimization for debug builds. - add -O3 optimization for release builds. 2. Update signal handler `handle_sigint()` to use `_exit()` instead of `exit()`. Normal exit() is not allowed within a signal handler. Signed-off-by: Florian La Roche --- FreeRTOS/Demo/Posix_GCC/CMakeLists.txt | 5 +++++ FreeRTOS/Demo/Posix_GCC/main.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/FreeRTOS/Demo/Posix_GCC/CMakeLists.txt b/FreeRTOS/Demo/Posix_GCC/CMakeLists.txt index 199de7508b5..6131634b6c0 100644 --- a/FreeRTOS/Demo/Posix_GCC/CMakeLists.txt +++ b/FreeRTOS/Demo/Posix_GCC/CMakeLists.txt @@ -4,6 +4,8 @@ project( posix_demo ) add_compile_options( -D_WINDOWS_ ) +add_compile_options( -Wall -Wextra -Wpedantic ) + if( TRACE_ON_ENTER ) add_compile_options( -DTRACE_ON_ENTER=1 ) else() @@ -33,6 +35,9 @@ else() set( CMAKE_BUILD_TYPE "debug" ) endif() +set(CMAKE_CXX_FLAGS_RELEASE "-O3") +set(CMAKE_CXX_FLAGS_DEBUG "-O0 -g3") + if( SANITIZE_ADDRESS ) add_compile_options( -fsanitize=address -fsanitize=alignment ) endif() diff --git a/FreeRTOS/Demo/Posix_GCC/main.c b/FreeRTOS/Demo/Posix_GCC/main.c index bf69bf280c0..f5773de512e 100644 --- a/FreeRTOS/Demo/Posix_GCC/main.c +++ b/FreeRTOS/Demo/Posix_GCC/main.c @@ -455,7 +455,7 @@ void handle_sigint( int signal ) printf( "chdir into %s error is %d\n", BUILD, errno ); } - exit( 2 ); + _exit( 2 ); } /*-----------------------------------------------------------*/ From c68a9af02016899436841b33f74e680d2ac4a86b Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Thu, 20 Jun 2024 22:23:12 +0200 Subject: [PATCH 06/15] FreeRTOS_Plus_TCP_Echo_Qemu_mps2: remove unused defines/functions (#1229) For FreeRTOS_Plus_TCP_Echo_Qemu_mps2: - remove unused defines - disable unused functions - typo: ipconfigUSE_DNS -> ipconfigUSE_DHCP Signed-off-by: Florian La Roche Co-authored-by: Anubhav Rawal <113639451+rawalexe@users.noreply.github.com> Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> --- .../FreeRTOSConfig.h | 22 ++++++++----------- .../FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile | 1 - .../mps2_m3.ld | 2 +- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h index 371b5f8dc1a..c30c781ffdc 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/FreeRTOSConfig.h @@ -57,11 +57,8 @@ extern void vAssertCalled( void ); #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 0 #define configMAX_PRIORITIES ( 10 ) -#define configTIMER_QUEUE_LENGTH 20 -#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 3 ) #define configUSE_COUNTING_SEMAPHORES 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1 -#define configNUM_TX_DESCRIPTORS 15 /* Set the following definitions to 1 to include the API function, or zero * to exclude the API function. */ @@ -74,7 +71,7 @@ extern void vAssertCalled( void ); #define INCLUDE_vTaskDelete 0 #define INCLUDE_vTaskCleanUpResources 0 #define INCLUDE_vTaskSuspend 0 -#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelayUntil 0 #define INCLUDE_vTaskDelay 1 @@ -89,7 +86,6 @@ extern void vAssertCalled( void ); /* networking definitions */ #define configMAC_ISR_SIMULATOR_PRIORITY ( configMAX_PRIORITIES - 2 ) #define ipconfigUSE_NETWORK_EVENT_HOOK 1 -/*#define ipconfigSOCK_DEFAULT_RECEIVE_BLOCK_TIME pdMS_TO_TICKS(5000) */ #define configNETWORK_INTERFACE_TO_USE 1L /* The address of an echo server that will be used by the two demo echo client @@ -115,16 +111,16 @@ extern void vAssertCalled( void ); #define configMAC_ADDR4 0x34 #define configMAC_ADDR5 0xAD -/* Default IP address configuration. Used in ipconfigUSE_DNS is set to 0, or - * ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +/* Default IP address configuration. Used if ipconfigUSE_DHCP is set to 0, or + * ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be contacted. */ #define configIP_ADDR0 10 #define configIP_ADDR1 211 #define configIP_ADDR2 55 #define configIP_ADDR3 5 -/* Default gateway IP address configuration. Used in ipconfigUSE_DNS is set to - * 0, or ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +/* Default gateway IP address configuration. Used if ipconfigUSE_DHCP is set to + * 0, or ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be contacted. */ #define configGATEWAY_ADDR0 10 #define configGATEWAY_ADDR1 211 @@ -132,16 +128,16 @@ extern void vAssertCalled( void ); #define configGATEWAY_ADDR3 1 /* Default DNS server configuration. OpenDNS addresses are 208.67.222.222 and - * 208.67.220.220. Used in ipconfigUSE_DNS is set to 0, or ipconfigUSE_DNS is set - * to 1 but a DNS server cannot be contacted.*/ + * 208.67.220.220. Used if ipconfigUSE_DHCP is set to 0, or ipconfigUSE_DHCP is set + * to 1 but a DHCP server cannot be contacted.*/ #define configDNS_SERVER_ADDR0 127 #define configDNS_SERVER_ADDR1 0 #define configDNS_SERVER_ADDR2 0 #define configDNS_SERVER_ADDR3 53 -/* Default netmask configuration. Used in ipconfigUSE_DNS is set to 0, or - * ipconfigUSE_DNS is set to 1 but a DNS server cannot be contacted. */ +/* Default netmask configuration. Used if ipconfigUSE_DHCP is set to 0, or + * ipconfigUSE_DHCP is set to 1 but a DHCP server cannot be contacted. */ #define configNET_MASK0 255 #define configNET_MASK1 255 #define configNET_MASK2 255 diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile index e51a46f79da..eb248d9a51a 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/Makefile @@ -30,7 +30,6 @@ INCLUDE_DIRS += -I$(KERNEL_DIR)/include SOURCE_FILES += $(KERNEL_DIR)/tasks.c SOURCE_FILES += $(KERNEL_DIR)/list.c SOURCE_FILES += $(KERNEL_DIR)/queue.c -SOURCE_FILES += $(KERNEL_DIR)/timers.c SOURCE_FILES += $(KERNEL_DIR)/event_groups.c # FreeRTOS Kernel ARM Cortex-M3 Port diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld index 13b1a3d79f0..97089f3c4aa 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/mps2_m3.ld @@ -128,7 +128,7 @@ SECTIONS _heap_top = .; . = . + _Min_Stack_Size; . = ALIGN(8); - } >RAM + } >RAM /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ From 4a231726de8dcd349eded1b8c7e9da880b07d746 Mon Sep 17 00:00:00 2001 From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Date: Fri, 21 Jun 2024 16:51:45 +0530 Subject: [PATCH 07/15] Fix compilation issue in WinSim Demo (#1232) * Fix compilation issue * Fix formatting * Uncrustify: triggered by comment. * Remove commented line --------- Co-authored-by: GitHub Action --- .../FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c index 126e7477696..3d4e285f1d6 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Minimal_Windows_Simulator/main.c @@ -145,6 +145,7 @@ static UBaseType_t ulNextRand; int main( void ) { + BaseType_t xResult; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -185,14 +186,14 @@ int main( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - - FreeRTOS_IPInit_Multi(); + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xResult = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xResult == pdTRUE ); + /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\r\n" ) ); vTaskStartScheduler(); From cfaee4906bbd2d821909516c07bd55bb39e02d23 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Sun, 30 Jun 2024 07:03:21 +0200 Subject: [PATCH 08/15] Posix_GCC: use complete function declaration (#1234) complete function declaration for Posix_GCC Signed-off-by: Florian La Roche --- FreeRTOS/Demo/Posix_GCC/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FreeRTOS/Demo/Posix_GCC/main.c b/FreeRTOS/Demo/Posix_GCC/main.c index f5773de512e..7f0fcf9fbc9 100644 --- a/FreeRTOS/Demo/Posix_GCC/main.c +++ b/FreeRTOS/Demo/Posix_GCC/main.c @@ -268,7 +268,7 @@ void vApplicationTickHook( void ) /*-----------------------------------------------------------*/ -void traceOnEnter() +void traceOnEnter( void ) { #if ( TRACE_ON_ENTER == 1 ) int xReturn; From 4c4f8450c3840a94f8f7605570e8c4ab6ef96a59 Mon Sep 17 00:00:00 2001 From: Florian La Roche Date: Mon, 1 Jul 2024 09:16:15 +0200 Subject: [PATCH 09/15] CORTEX_MPU_M3_MPS2_QEMU_GCC: remove unused defines (#1233) From CORTEX_MPU_M3_MPS2_QEMU_GCC remove unused configNUM_TX_DESCRIPTORS define and remove HEAP3 from as heap_4.c is used. Signed-off-by: Florian La Roche Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> --- FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h index 01fefd710db..e83bb33c70b 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_M3_MPS2_QEMU_GCC/FreeRTOSConfig.h @@ -72,7 +72,6 @@ extern void vAssertCalled( void ); #define configUSE_COUNTING_SEMAPHORES 1 #define configSUPPORT_DYNAMIC_ALLOCATION 1 #define configSUPPORT_STATIC_ALLOCATION 1 -#define configNUM_TX_DESCRIPTORS 15 #define configSTREAM_BUFFER_TRIGGER_LEVEL_TEST_MARGIN 2 #define configCHECK_FOR_STACK_OVERFLOW 2 #define configALLOW_UNPRIVILEGED_CRITICAL_SECTIONS 0 @@ -134,9 +133,4 @@ unsigned long ulGetRunTimeCounterValue( void ); /* Prototype of function that re extern void vLoggingPrintf( const char * pcFormatString, ... ); -#ifdef HEAP3 - #define xPortGetMinimumEverFreeHeapSize ( x ) - #define xPortGetFreeHeapSize ( x ) -#endif - #endif /* FREERTOS_CONFIG_H */ From 18bf1ffb189cc7d73dd1cffb1b50765777c99b70 Mon Sep 17 00:00:00 2001 From: Niklas Date: Mon, 22 Jul 2024 08:45:03 +0200 Subject: [PATCH 10/15] fix AbortDelay.c Test (#1237) * fix AbortDelay.c Test * Uncrustify: triggered by comment. * Update comment * Fix formatting --------- Co-authored-by: Niklas Jenner Co-authored-by: GitHub Action Co-authored-by: Monika Singh --- FreeRTOS/Demo/Common/Minimal/AbortDelay.c | 25 ++++++++++++----------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/FreeRTOS/Demo/Common/Minimal/AbortDelay.c b/FreeRTOS/Demo/Common/Minimal/AbortDelay.c index 55f0ba638e8..581fcbe8aef 100644 --- a/FreeRTOS/Demo/Common/Minimal/AbortDelay.c +++ b/FreeRTOS/Demo/Common/Minimal/AbortDelay.c @@ -488,20 +488,21 @@ uint8_t uxRxData; #if ( configSUPPORT_STATIC_ALLOCATION == 1 ) - { - /* Defines the memory that will actually hold the streams within the - * stream buffer. */ - static uint8_t ucStorageBuffer[ sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) + 1 ]; - /* The variable used to hold the stream buffer structure. */ + /* The variable used to hold the stream buffer structure. + * This control information is valid as long as xStreamBuffer + * is valid. */ StaticStreamBuffer_t xStreamBufferStruct; - - - xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ), - xTriggerLevelBytes, - ucStorageBuffer, - &xStreamBufferStruct ); - } + { + /* Defines the memory that will actually hold the streams within the + * stream buffer. */ + static uint8_t ucStorageBuffer[ sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) + 1 ]; + + xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ), + xTriggerLevelBytes, + ucStorageBuffer, + &xStreamBufferStruct ); + } #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */ { xStreamBuffer = xStreamBufferCreate( sizeof( uint8_t ), xTriggerLevelBytes ); From e713577f0c3b5e0b383ea242ffadb35adc3b1618 Mon Sep 17 00:00:00 2001 From: Michael Tautschnig Date: Thu, 1 Aug 2024 07:57:53 +0200 Subject: [PATCH 11/15] Use CBMC version 5.95.1 (#1226) The upcoming CBMC version 6 release includes changes that may affect existing proofs. This PR will make sure that FreeRTOS PRs are not negatively impacted by this release. After releasing CBMC version 6 we will issue a follow-up PR that will return FreeRTOS to using CBMC's latest release, and will include any changes to proofs that may be necessary to support the new version. Co-authored-by: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Co-authored-by: Nikhil Kamath <110539926+amazonKamath@users.noreply.github.com> --- .github/workflows/ci.yml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 4747d4904b6..99122b7e3e9 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -168,6 +168,8 @@ jobs: - name: Set up CBMC runner uses: FreeRTOS/CI-CD-Github-Actions/set_up_cbmc_runner@main + with: + cbmc_version: "5.95.1" - name: Run CBMC uses: FreeRTOS/CI-CD-Github-Actions/run_cbmc@main From 79d6134f39e047bb0596547cd396007bb14c2fff Mon Sep 17 00:00:00 2001 From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Date: Fri, 9 Aug 2024 10:50:04 +0530 Subject: [PATCH 12/15] Update README to fix broken links (#1240) --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 8fc881f9d7e..9a78012dbba 100644 --- a/README.md +++ b/README.md @@ -1,10 +1,10 @@ The [FreeRTOS 202212.00](https://github.com/FreeRTOS/FreeRTOS/tree/202212.00) release updates FreeRTOS Kernel, FreeRTOS+TCP, coreMQTT, corePKCS11, coreHTTP, coreJSON, AWS IoT Over-the-air-Updates (OTA), AWS IoT Device Shadow, AWS IoT Jobs, AWS IoT Device Defender, Backoff Algorithm, AWS IoT Fleet Provisioning, coreSNTP, SigV4, and FreeRTOS Cellular Interface libraries to their [LTS 2.0](https://github.com/FreeRTOS/FreeRTOS-LTS/blob/202210-LTS/CHANGELOG.md) versions. It also updates coreMQTT Agent to v1.2.0 to be compatible with coreMQTT v2.X.X, and updates MbedTLS to v3.2.1. This release also adds Visual Studio static library projects for the FreeRTOS Kernel, FreeRTOS+TCP, Logging, MbedTLS, coreHTTP, and corePKCS11. With the addition of the static library projects, all Visual Studio projects have been updated to use them. Additionally, all demos dependent on coreMQTT have been updated to work with coreMQTT v2.X.X. ## Getting started -The [FreeRTOS.org](https://www.freertos.org) website contains a [FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/FreeRTOS-quick-start-guide.html), a [list of supported devices and compilers](https://www.freertos.org/RTOS_ports.html), the [API reference](https://www.freertos.org/a00106.html), and many other resources. +The [FreeRTOS.org](https://www.freertos.org) website contains a [FreeRTOS Kernel Quick Start Guide](https://www.freertos.org/Documentation/01-FreeRTOS-quick-start/01-Beginners-guide/02-Quick-start-guide), a [list of supported devices and compilers](https://www.freertos.org/RTOS_ports.html), the [API reference](https://www.freertos.org/Documentation/02-Kernel/04-API-references/01-Task-creation/00-TaskHandle), and many other resources. ### Getting help -You can use your Github login to get support from both the FreeRTOS community and directly from the primary FreeRTOS developers on our [active support forum](https://forums.freertos.org). The [FAQ](https://www.freertos.org/FAQ.html) provides another support resource. +You can use your Github login to get support from both the FreeRTOS community and directly from the primary FreeRTOS developers on our [active support forum](https://forums.freertos.org). The [FAQ](https://www.freertos.org/Why-FreeRTOS/FAQs) provides another support resource. ## Cloning this repository This repo uses [Git Submodules](https://git-scm.com/book/en/v2/Git-Tools-Submodules) to bring in dependent components. From 46311d1612d2b7d9caaf069c9728df7f6a72b7cb Mon Sep 17 00:00:00 2001 From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Date: Sun, 11 Aug 2024 19:07:30 +0530 Subject: [PATCH 13/15] ARMv7-R No_GIC Port Demo (#1236) Add ARM_CRx_No_GIC_Demo --- .github/.cSpellWords.txt | 1 + .github/scripts/core_checker.py | 1 + .../.ccsproject | 8 + .../.clang-format | 104 + .../.cproject | 180 + .../.gitignore | 4 + .../.project | 112 + ...IC_R5F_TI_RM57_HERCULES_GCC.code-workspace | 50 + .../BoardFiles/HalCoGen-RM57L843.dil | 11975 ++++++++++++++++ .../BoardFiles/HalCoGen-RM57L843.hcg | 1041 ++ .../BoardFiles/RM57L8xx.ccxml | 43 + .../BoardFiles/include/Device_RM57.h | 114 + .../BoardFiles/include/Device_header.h | 65 + .../BoardFiles/include/Device_types.h | 133 + .../BoardFiles/include/MemMap.h | 39 + .../BoardFiles/include/adc.h | 344 + .../BoardFiles/include/can.h | 926 ++ .../BoardFiles/include/crc.h | 344 + .../BoardFiles/include/dcc.h | 353 + .../BoardFiles/include/dmm.h | 164 + .../BoardFiles/include/ecap.h | 347 + .../BoardFiles/include/emac.h | 438 + .../BoardFiles/include/emac_phyConfig.h | 45 + .../BoardFiles/include/emif.h | 216 + .../BoardFiles/include/epc.h | 134 + .../BoardFiles/include/eqep.h | 863 ++ .../BoardFiles/include/errata.h | 70 + .../BoardFiles/include/errata_SSWF021_45.h | 48 + .../include/errata_SSWF021_45_defs.h | 204 + .../BoardFiles/include/esm.h | 1178 ++ .../BoardFiles/include/etpwm.h | 909 ++ .../BoardFiles/include/fee_interface.h | 254 + .../BoardFiles/include/gio.h | 182 + .../BoardFiles/include/hal_stdtypes.h | 185 + .../BoardFiles/include/het.h | 633 + .../BoardFiles/include/htu.h | 70 + .../BoardFiles/include/hw_emac.h | 1304 ++ .../BoardFiles/include/hw_emac_ctrl.h | 92 + .../BoardFiles/include/hw_mdio.h | 235 + .../BoardFiles/include/hw_reg_access.h | 80 + .../BoardFiles/include/i2c.h | 290 + .../BoardFiles/include/lin.h | 317 + .../BoardFiles/include/mdio.h | 94 + .../BoardFiles/include/mibspi.h | 885 ++ .../BoardFiles/include/nmpu.h | 165 + .../BoardFiles/include/phy_dp83640.h | 139 + .../BoardFiles/include/phy_tlk111.h | 156 + .../BoardFiles/include/pinmux.h | 1762 +++ .../BoardFiles/include/pom.h | 339 + .../BoardFiles/include/reg_adc.h | 252 + .../BoardFiles/include/reg_can.h | 230 + .../BoardFiles/include/reg_ccmr5.h | 84 + .../BoardFiles/include/reg_crc.h | 132 + .../BoardFiles/include/reg_dcc.h | 99 + .../BoardFiles/include/reg_dma.h | 242 + .../BoardFiles/include/reg_dmm.h | 127 + .../BoardFiles/include/reg_ecap.h | 155 + .../BoardFiles/include/reg_efc.h | 94 + .../BoardFiles/include/reg_emif.h | 97 + .../BoardFiles/include/reg_epc.h | 97 + .../BoardFiles/include/reg_eqep.h | 148 + .../BoardFiles/include/reg_esm.h | 110 + .../BoardFiles/include/reg_etpwm.h | 219 + .../BoardFiles/include/reg_flash.h | 135 + .../BoardFiles/include/reg_gio.h | 128 + .../BoardFiles/include/reg_het.h | 187 + .../BoardFiles/include/reg_htu.h | 130 + .../BoardFiles/include/reg_i2c.h | 136 + .../BoardFiles/include/reg_l2ramw.h | 93 + .../BoardFiles/include/reg_lin.h | 138 + .../BoardFiles/include/reg_mibspi.h | 311 + .../BoardFiles/include/reg_nmpu.h | 98 + .../BoardFiles/include/reg_pbist.h | 96 + .../BoardFiles/include/reg_pcr.h | 149 + .../BoardFiles/include/reg_pinmux.h | 101 + .../BoardFiles/include/reg_pmm.h | 104 + .../BoardFiles/include/reg_pom.h | 121 + .../BoardFiles/include/reg_rtp.h | 112 + .../BoardFiles/include/reg_sci.h | 164 + .../BoardFiles/include/reg_scm.h | 93 + .../BoardFiles/include/reg_sdcmmr.h | 95 + .../BoardFiles/include/reg_spi.h | 178 + .../BoardFiles/include/reg_stc.h | 96 + .../BoardFiles/include/reg_system.h | 192 + .../BoardFiles/include/reg_vim.h | 114 + .../BoardFiles/include/rtp.h | 165 + .../BoardFiles/include/sci.h | 263 + .../BoardFiles/include/spi.h | 232 + .../BoardFiles/include/std_nhet.h | 2362 +++ .../BoardFiles/include/sys_common.h | 132 + .../BoardFiles/include/sys_core.h | 351 + .../BoardFiles/include/sys_dma.h | 300 + .../BoardFiles/include/sys_mpu.h | 612 + .../BoardFiles/include/sys_pcr.h | 331 + .../BoardFiles/include/sys_pmm.h | 119 + .../BoardFiles/include/sys_pmu.h | 240 + .../BoardFiles/include/sys_vim.h | 386 + .../BoardFiles/include/system.h | 477 + .../BoardFiles/include/ti_fee.h | 625 + .../BoardFiles/include/ti_fee_cfg.h | 55 + .../BoardFiles/include/ti_fee_types.h | 260 + .../BoardFiles/source/adc.c | 1052 ++ .../BoardFiles/source/can.c | 1690 +++ .../BoardFiles/source/crc.c | 652 + .../BoardFiles/source/dabort.S | 164 + .../BoardFiles/source/dcc.c | 455 + .../BoardFiles/source/ecap.c | 1062 ++ .../BoardFiles/source/emac.c | 1965 +++ .../BoardFiles/source/emif.c | 320 + .../BoardFiles/source/epc.c | 369 + .../BoardFiles/source/eqep.c | 1273 ++ .../BoardFiles/source/errata.c | 273 + .../BoardFiles/source/errata_SSWF021_45.c | 374 + .../BoardFiles/source/esm.c | 1068 ++ .../BoardFiles/source/etpwm.c | 2393 +++ .../BoardFiles/source/gio.c | 505 + .../BoardFiles/source/het.c | 2921 ++++ .../BoardFiles/source/i2c.c | 1005 ++ .../BoardFiles/source/lin.c | 943 ++ .../BoardFiles/source/mdio.c | 251 + .../BoardFiles/source/mibspi.c | 3408 +++++ .../BoardFiles/source/nmpu.c | 403 + .../BoardFiles/source/notification.c | 330 + .../BoardFiles/source/phy_dp83640.c | 433 + .../BoardFiles/source/phy_tlk111.c | 401 + .../BoardFiles/source/pinmux.c | 559 + .../BoardFiles/source/pom.c | 354 + .../BoardFiles/source/sci.c | 994 ++ .../BoardFiles/source/sys_core.S | 574 + .../BoardFiles/source/sys_dma.c | 654 + .../BoardFiles/source/sys_intvecs.S | 75 + .../BoardFiles/source/sys_link.ld | 186 + .../BoardFiles/source/sys_pcr.c | 1081 ++ .../BoardFiles/source/sys_phantom.c | 77 + .../BoardFiles/source/sys_pmm.c | 229 + .../BoardFiles/source/sys_pmu.S | 215 + .../BoardFiles/source/sys_startup.c | 290 + .../BoardFiles/source/sys_vim.c | 855 ++ .../BoardFiles/source/system.c | 652 + .../CMakeLists.txt | 204 + .../README.md | 67 + .../include/FreeRTOSConfig.h | 170 + .../include/demo_tasks.h | 181 + .../source/irq_demo.c | 244 + .../source/main.c | 466 + .../source/notification_demo.c | 203 + .../source/queue_demo.c | 355 + .../source/reg_test.c | 176 + .../source/reg_test_GCC.S | 443 + .../targetConfigs/RM57L8xx.ccxml | 14 + .../targetConfigs/readme.txt | 9 + 151 files changed, 72639 insertions(+) create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.ccsproject create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.clang-format create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace create mode 100644 FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil create 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+SpacesInContainerLiterals: true +SpacesInCStyleCastParentheses: true +SpacesInParentheses: true +SpacesInSquareBrackets: true +TabWidth: 4 +UseCRLF: false +UseTab: Never +... + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject new file mode 100644 index 00000000000..29e8979ae89 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.cproject @@ -0,0 +1,180 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore new file mode 100644 index 00000000000..ba04ae8d56e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.gitignore @@ -0,0 +1,4 @@ +[Bb]uild +[Dd]ebug +.settings/ +.launches/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project new file mode 100644 index 00000000000..cadb79efb9e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.project @@ -0,0 +1,112 @@ + + + RM57_DEMO + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + FreeRTOS-Kernel + 2 + FREERTOS_KERNEL_DIR + + + + + 1703728734708 + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-CMakeLists.txt + + + + 1703728734721 + + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-build + + + + 1703284519364 + FreeRTOS-Kernel + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.c + + + + 1703284519366 + FreeRTOS-Kernel + 10 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-examples + + + + 1720520309667 + FreeRTOS-Kernel/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1720518946690 + FreeRTOS-Kernel/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-true-false-ARM_CRx_No_GIC + + + + + + BOARD_FILES_DIR + $%7BPROJECT_LOC%7D/BoardFiles + + + DEMO_TASKS_DIR + $%7BPARENT-1-PROJECT_LOC%7D/DemoTasks + + + FREERTOS_KERNEL_DIR + $%7BPARENT-2-PROJECT_LOC%7D/Source + + + FREERTOS_PORT_DIR + $%7BFREERTOS_KERNEL_DIR%7D/portable/GCC/ARM_CRx_No_GIC + + + REPOSITORY_ROOT + $%7BPARENT-2-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace new file mode 100644 index 00000000000..a132b0b1a0d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/.vscode/CORTEX_NO_GIC_R5F_TI_RM57_HERCULES_GCC.code-workspace @@ -0,0 +1,50 @@ +{ + "folders": [ + { + "path": ".." + }, + { + "path": "../../../Source", + "name": "FreeRTOS-Kernel" + }, + { + "path": "../../../Source/portable/GCC/ARM_CRx_No_GIC", + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_No_GIC", + "../../Source/include", + "../../Source", + ], + } + ], + "settings": { + "files.associations": { + "*.h": "c", + "variant": "c" + }, + + "files.exclude": { + "**/.launches/**": true, + "**/.settings/**": true, + "**/.ccsproject/**": true, + "**/examples**": true, + "**/.github**": true, + "**/.git[a-hj-z-]**": true, + "**/portable/**": true + + }, + + "C_Cpp.default.includePath": [ + "../source", + "../include", + "../BoardFiles/include", + "../BoardFiles/source", + "../../Source/portable/GCC/ARM_CRx_No_GIC", + "../../Source/include", + "../../Source", + ], + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil new file mode 100644 index 00000000000..49910de8bf4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.dil @@ -0,0 +1,11975 @@ +# RM57L843ZWT 02/13/23 13:55:32 +# +ARCH=RM57L843ZWT +# +DRIVER.TOOLS.VAR.GCC.VALUE=1 +DRIVER.TOOLS.VAR.ARM.VALUE=0 +DRIVER.TOOLS.VAR.IAR.VALUE=0 +DRIVER.TOOLS.VAR.GHS.VALUE=0 +DRIVER.TOOLS.VAR.TI.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE.VALUE=NORMAL_OIWTNOWA_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_0.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_1_WAIT_STATE_FREQ.VALUE=32.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_NAME.VALUE=het2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_NAME.VALUE=adc2Group2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_NAME.VALUE=mibspi4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_MAPPING.VALUE=2 +DRIVER.SYSTEM.VAR.VIM_CAPTURE_EVENT_SOURCE_1.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.EQEP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_3_WAIT_STATE_FREQ.VALUE=180.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_MAPPING.VALUE=96 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_MAPPING.VALUE=88 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.LIN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI3_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE_VALUE.VALUE=0x0002 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_NAME.VALUE=epcFullInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_NAME.VALUE=sci4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_NAME.VALUE=ecap5Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CRC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_HCLK_FREQ.VALUE=150.000 +DRIVER.SYSTEM.VAR.CLKT_PLL2_FREQ.VALUE=300.00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_MAPPING.VALUE=81 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_MAPPING.VALUE=73 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_MAPPING.VALUE=65 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_MAPPING.VALUE=57 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_MAPPING.VALUE=49 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_NAME.VALUE=dmaBTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_NAME.VALUE=het1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_NAME.VALUE=can1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECLK_CLKSRC.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CLKT_PLL2_OUTPUT_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXT2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_PLL1_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_END_ADDRESS.VALUE=0x6FFFFFFF +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_NAME.VALUE=etpwm5TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_MAPPING.VALUE=50 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_MAPPING.VALUE=42 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_MAPPING.VALUE=34 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_MAPPING.VALUE=26 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_MAPPING.VALUE=18 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANKS.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_DISP_ENTRY.VALUE=_isrStub +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CAN3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION_VALUE.VALUE=0x0500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_MAPPING.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION.VALUE=PRIV_RW_USER_RW_NOEXEC +DRIVER.SYSTEM.VAR.LBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE.VALUE=NORMAL_OIWBWA_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_END_ADDRESS.VALUE=0x00007fff +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_DATA_1_WAIT_STATE_FREQ.VALUE=90.0 +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_BASE.VALUE=0x08000500 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_MAPPING.VALUE=125 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_MAPPING.VALUE=117 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_MAPPING.VALUE=109 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_NAME.VALUE=etpwm1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_NAME.VALUE=dcc1DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_NAME.VALUE=sciLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_NAME.VALUE=i2cInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_PMU_GLOBAL_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SIZE.VALUE=512_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_STACK.VALUE=12 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EMAC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_MAPPING.VALUE=8 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_NAME.VALUE=FreeRTOS_Tick_Handler +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER0_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENTRY.VALUE=_c_int00 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_VCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_NAME.VALUE=can4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_MAPPING.VALUE=110 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_NAME.VALUE=ecap6Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_MAPPING.VALUE=102 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LENGTH.VALUE=0x00080000 +DRIVER.SYSTEM.VAR.CORE_MPU_TOTAL_REGION.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE.VALUE=256_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_NAME.VALUE=dmaFTCAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_NAME.VALUE=spi2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_MAPPING.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_SOURCE_ENABLE.VALUE=0x00000008 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_BASE_ADDRESS.VALUE=0xF0000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_MAPPING.VALUE=95 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_MAPPING.VALUE=87 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_MAPPING.VALUE=79 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_IRQ_VIC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SPI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_8_WAIT_STATE_FREQ.VALUE=144.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_NAME.VALUE=etpwm6Interrupt +DRIVER.SYSTEM.VAR.CLKT_RTI2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_7_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.STC_INTERVAL.VALUE=40 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_GCLK_FREQ.VALUE=300.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_MAPPING.VALUE=80 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_MAPPING.VALUE=72 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_MAPPING.VALUE=64 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_MAPPING.VALUE=56 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_MAPPING.VALUE=48 +DRIVER.SYSTEM.VAR.CLKT_PLL1_REF_CLOCK_DIV.VALUE=8 +DRIVER.SYSTEM.VAR.FLASHW_BASE_ADDRESS.VALUE=0xFFF87000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_FIQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCILIN_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SPI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ALL_DVR_ENA.VALUE=1 +DRIVER.SYSTEM.VAR.CCM_MENU_VALUE.VALUE=0x0001 +DRIVER.SYSTEM.VAR.PBIST_ENA1.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_NAME.VALUE=etpwm1TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_NAME.VALUE=dcc2DoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_MAPPING.VALUE=41 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_MAPPING.VALUE=33 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_MAPPING.VALUE=25 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_MAPPING.VALUE=17 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_MODE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.PMM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.EMIF_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_OUTPUT_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_PLL2_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_BASE_ADDRESS.VALUE=0xF8000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_PRE_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.FLASH_MODE_VALUE.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SIZE_VALUE.VALUE=0x1B +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_NUM.VALUE=3 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_NAME.VALUE=lin2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_MAPPING.VALUE=10 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SIZE.VALUE=128_MB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_BYPASS_ON_SLIP.VALUE=0x20000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_MAPPING.VALUE=124 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_MAPPING.VALUE=116 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_MAPPING.VALUE=108 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_NAME.VALUE=adc2Group0Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_NAME.VALUE=can2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_NAME.VALUE=dmaLFSAInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_NAME.VALUE=mibspi1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.FLASH_ARBITRATION.VALUE=FIX +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SCI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_9_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ_INPUT.VALUE=16.0 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_6_WAIT_STATE_FREQ.VALUE=112.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SIZE_VALUE.VALUE=0x12 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_MAPPING.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_RTI2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_BACKGROUND_REGION_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CONFIG.VALUE=TRUE +DRIVER.SYSTEM.VAR.CRC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_MAPPING.VALUE=101 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_NAME.VALUE=etpwm6TripZoneInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_WAIT_STATES.VALUE=9 +DRIVER.SYSTEM.VAR.FLASH_DATA_MAX_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.FLASH_MODE.VALUE=PIPELINE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MINIT_VALUE.VALUE=0x1E57F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_MAPPING.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.RAM_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_PMU_EVENT_EXPORT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_2_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.GIO_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_MAPPING.VALUE=94 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_MAPPING.VALUE=86 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_MAPPING.VALUE=78 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE.VALUE=STRONGLYORDERED_SHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.MIBSPI4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_STACK_ABORT_BASE.VALUE=0x08000600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_NAME.VALUE=etpwm2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_RTI1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_6_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.CLKT_GHV_WAKUP_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_TYPE_VALUE.VALUE=0x0000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_MAPPING.VALUE=71 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_MAPPING.VALUE=63 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_MAPPING.VALUE=55 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_MAPPING.VALUE=47 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_MAPPING.VALUE=39 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CLKT_HCLK_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER1_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.EFUSE_SELFTEST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_LINK_BASE_ADDRESS.VALUE=0x08000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_NAME.VALUE=sci4LowLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_DIV.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE.VALUE=8_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_4_WAIT_STATE_FREQ.VALUE=80.0 +DRIVER.SYSTEM.VAR.FLASH_ADDRESS_WAIT_STATES_FREQ.VALUE=120.0 +DRIVER.SYSTEM.VAR.RAM_STACK_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_NAME.VALUE=adc2Group1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_MAPPING.VALUE=40 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_NAME.VALUE=can2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_MAPPING.VALUE=32 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_NAME.VALUE=lin1LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_MAPPING.VALUE=24 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_NAME.VALUE=crcInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_MAPPING.VALUE=16 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_END_ADDRESS.VALUE=0xF07FFFFF +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM7_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_1.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_2.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_3.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_4.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_NAME.VALUE=eqep1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_NAME.VALUE=etpwm7Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_5.VALUE=0 +DRIVER.SYSTEM.VAR.LBIST_STT.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_6.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_ECC_AVAILABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_7.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_8.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE_VALUE.VALUE=0x000C +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_MAPPING.VALUE=123 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_MAPPING.VALUE=115 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_MAPPING.VALUE=107 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_NAME.VALUE=het1HighLevelInterrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_9.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_LENGTH.VALUE=0x00000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_CACHE_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.SCI2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.LIN_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SIZE_VALUE.VALUE=0x1A +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_MAPPING.VALUE=6 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.ECLK_FREQ.VALUE=9.375 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_MAPPING.VALUE=100 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_NAME.VALUE=etpwm2TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_NAME.VALUE=EMACTxIntISR +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_IRQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_2_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_RTI2_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_10_WAIT_STATE_FREQ.VALUE=176.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.RAM_STACK_LENGTH.VALUE=0x00000800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_PERMISSION.VALUE=PRIV_RO_USER_NA_EXEC +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS.VALUE=true +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIVIDER1.VALUE=4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_1_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_END_ADDRESS.VALUE=0x003fffff +DRIVER.SYSTEM.VAR.CORE_PRAGMA_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI4_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_POST_SOURCE.VALUE=VCLKA4_DIVR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ1.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_2_WAIT_STATE_FREQ.VALUE=48.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_MAPPING.VALUE=93 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_MAPPING.VALUE=85 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_MAPPING.VALUE=77 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_MAPPING.VALUE=69 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ2.VALUE=18.750 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.MIBSPI2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL.VALUE=150 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_NAME.VALUE=adc1Group2Interrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CLKT_OSC_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PINMUX_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_3_4.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_BIAS_VALUE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_MAPPING.VALUE=70 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_MAPPING.VALUE=62 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_MAPPING.VALUE=54 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_MAPPING.VALUE=46 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_MAPPING.VALUE=38 +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_SOURCE_ENABLE.VALUE=0x00000080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_LAST.VALUE=15 +DRIVER.SYSTEM.VAR.CORE_MPU_TASK_REGION_FIRST.VALUE=13 +DRIVER.SYSTEM.VAR.PBIST_ALGO_15.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_NAME.VALUE=eqep2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_NAME.VALUE=etpwm7TripZoneInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_16.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.RAM_LINK_LENGTH.VALUE=0x0007F800 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CAN4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_OSCFRQCONFIGCNT_VALUE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_MAPPING.VALUE=31 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_MAPPING.VALUE=23 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_MAPPING.VALUE=15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_11_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_5_6.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ENA.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_HCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_10_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ETPWM5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL.VALUE=150 +DRIVER.SYSTEM.VAR.CLKT_RTI2_FREQ.VALUE=0.0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_FREQ.VALUE=0.080 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE.VALUE=NORMAL_OINC_NONSHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_PREFETCH_ENTRY.VALUE=_prefetch +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_FREQ.VALUE=0.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION_VALUE.VALUE=0x1600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_NAME.VALUE=etpwm3Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_OSCILLATOR_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_BASE_ADDRESS.VALUE=0x60000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_7_8.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_RESET_ON_OSCILLATOR_FAIL.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_0.VALUE=0x00008020 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_1.VALUE=0x00200000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_0_WAIT_STATE_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_MAPPING.VALUE=122 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_MAPPING.VALUE=114 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_MAPPING.VALUE=106 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_PMU_COUNTER2_EVENT.VALUE=0x11 +DRIVER.SYSTEM.VAR.FLASH_DATA_WAIT_STATES.VALUE=3 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ADC2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK2_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_DATA_2_WAIT_STATE_FREQ.VALUE=135.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_MAPPING.VALUE=5 +DRIVER.SYSTEM.VAR.VIM_CHANNELS.VALUE=128 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_BASE_ADDRESS_7.VALUE=0xF0200000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ESM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_MAPPING.VALUE=99 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_NAME.VALUE=mibspi5HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_NAME.VALUE=can3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_NAME.VALUE=mibspi3HighInterruptLevel +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_NAME.VALUE=can1LowLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_FREQ.VALUE=10.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE_VALUE.VALUE=0x12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_0_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_IRQ_ENTRY.VALUE="ldr pc,[pc,#-0x1b0]" +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.LIN1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SPI2_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_GHV_POWER_DOWN_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.RAM_STACK_USER_BASE.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_NAME.VALUE=ecap1Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_92_MAPPING.VALUE=92 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_84_MAPPING.VALUE=84 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_76_MAPPING.VALUE=76 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_68_MAPPING.VALUE=68 +DRIVER.SYSTEM.VAR.CLKT_GCLK_DOMAIN_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_81_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_73_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_65_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_57_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_49_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.SYSTEM_INIT.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_NAME.VALUE=esmLowInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_NAME.VALUE=mibspi1HighLevelInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_1_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_TYPE.VALUE=FIQ +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_9_WAIT_STATE_FREQ.VALUE=160.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION_VALUE.VALUE=0x0600 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_PERMISSION_VALUE.VALUE=0x1200 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_61_MAPPING.VALUE=61 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_53_MAPPING.VALUE=53 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_45_MAPPING.VALUE=45 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_37_MAPPING.VALUE=37 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_29_MAPPING.VALUE=29 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DIR.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_LENGTH.VALUE=0x00400000 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_EXT1_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE.VALUE=DEVICE_NONSHAREABLE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_ECC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_95_NAME.VALUE=etpwm3TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_87_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_79_NAME.VALUE=EMACRxIntISR +DRIVER.SYSTEM.VAR.CLKT_VCLK1_DIVIDER.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_PERMISSION.VALUE=PRIV_RO_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_124_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_116_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_108_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CAN2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SYSTEM.VAR.PBIST_ALGO_1.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_DATA_0_WAIT_STATE_FREQ.VALUE=45.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_MAPPING.VALUE=30 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_MAPPING.VALUE=22 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_MAPPING.VALUE=14 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_7_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.PBIST_ALGO_2.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_RTI1_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_AVCLK1_DOMAIN_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET2_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_VCLK3_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ1.VALUE=75.000 +DRIVER.SYSTEM.VAR.PBIST_ALGO_11_12.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_MAX_WAIT_STATES.VALUE=11 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECAP5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ADC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_TYPE_VALUE.VALUE=0x000B +DRIVER.SYSTEM.VAR.VIM_CHANNEL_70_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_62_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_54_NAME.VALUE=mibspi4LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_46_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_38_NAME.VALUE=mibspi3LowLevelInterrupt +DRIVER.SYSTEM.VAR.FEE_FLASH_ECC_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_110_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_102_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_MAPPING.VALUE=121 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_MAPPING.VALUE=113 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_MAPPING.VALUE=105 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_RESERVED_ENTRY.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_121_NAME.VALUE=crc2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_113_NAME.VALUE=can4HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_105_NAME.VALUE=ecap2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_MAPPING.VALUE=4 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_END_ADDRESS.VALUE=0x87FFFFFF +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE.VALUE=4_MB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.I2C1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_7_WAIT_STATE_FREQ.VALUE=128.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_MAPPING.VALUE=98 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_NAME.VALUE=vPortYieldWithinAPI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_NAME.VALUE=lin1HighLevelInterrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_FUN.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_94_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_86_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_78_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.HET_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.PBIST_ALGO_13_14.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_BASE.VALUE=0x08000700 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_BASE.VALUE=0x08000300 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.DMM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_0.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_FREQ.VALUE=75.000 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_1.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.VIM_CHANNEL_96_NAME.VALUE=etpwm4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_91_MAPPING.VALUE=91 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_88_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_83_MAPPING.VALUE=83 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_75_MAPPING.VALUE=75 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_67_MAPPING.VALUE=67 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_59_MAPPING.VALUE=59 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_2.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.CLKT_VCLK2_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_3.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_END_ADDRESS.VALUE=0x0807ffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_40_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_32_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_24_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_16_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PDR.VALUE=0 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_4.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_5.VALUE=SLEEP +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE_VALUE.VALUE=0x0E +DRIVER.SYSTEM.VAR.VIM_CHANNEL_8_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.ECLK_PRESCALER.VALUE=8 +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_6.VALUE=SLEEP +DRIVER.SYSTEM.VAR.FLASH_BANK_CONFIG_7.VALUE=ACTIVE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_END_ADDRESS.VALUE=0xffffffff +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_VCLK4_FREQ.VALUE=75.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_60_MAPPING.VALUE=60 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_52_MAPPING.VALUE=52 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_44_MAPPING.VALUE=44 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_36_MAPPING.VALUE=36 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_28_MAPPING.VALUE=28 +DRIVER.SYSTEM.VAR.CLKT_PLL1_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_SOURCE_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL2_MUL_VAL.VALUE=9500 +DRIVER.SYSTEM.VAR.CLKT_RTI1_POST_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_NAME.VALUE=het2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_NAME.VALUE=can3LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_NAME.VALUE=dmaHBCAInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL2_BAND_WIDTH_ADJUSTMENT.VALUE=7 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_DATA_ENTRY.VALUE=_dabort +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_MAPPING.VALUE=21 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_MAPPING.VALUE=13 +DRIVER.SYSTEM.VAR.CLKT_PLL2_REF_CLOCK_DIV.VALUE=8 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_RATE.VALUE=255 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ETPWM1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_RESET_ON_SLIP.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_5_WAIT_STATE_FREQ.VALUE=96.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_TYPE_VALUE.VALUE=0x0010 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION_VALUE.VALUE=0x0300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_127_MAPPING.VALUE=127 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_122_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_119_MAPPING.VALUE=119 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_114_NAME.VALUE=i2c2Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_106_NAME.VALUE=ecap3nterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_PERMISSION.VALUE=PRIV_RO_USER_RO_EXEC +DRIVER.SYSTEM.VAR.CLKT_PLL1_FM_ENABLE.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SIZE.VALUE=32_KB +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.ECAP3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_30_NAME.VALUE=mibspi2LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_22_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_14_NAME.VALUE=adc1Group0Interrupt +DRIVER.SYSTEM.VAR.CLKT_LPOLO_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SCI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PSL.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_MAPPING.VALUE=120 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_MAPPING.VALUE=112 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_MAPPING.VALUE=104 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_END_ADDRESS.VALUE=0x0000001F +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_BASE_ADDRESS.VALUE=0x80000000 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_SVC_ENTRY.VALUE=vPortSWI +DRIVER.SYSTEM.VAR.VIM_CHANNEL_21_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_13_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CONFIG_NEW.VALUE=1 +DRIVER.SYSTEM.VAR.CRC1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_EXTERNAL2_FREQ.VALUE=00.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_TYPE_VALUE.VALUE=0x0002 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_NAME.VALUE=etpwm4TripZoneInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_3_MAPPING.VALUE=3 +DRIVER.SYSTEM.VAR.CLKT_LPOHI_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_101_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_99_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_6_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.CLKT_GHV_NORMAL_SOURCE.VALUE=PLL1 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_DIV_FREQ.VALUE=75.0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_97_MAPPING.VALUE=97 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_89_MAPPING.VALUE=89 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_NAME.VALUE=gioHighLevelInterrupt +DRIVER.SYSTEM.VAR.CLKT_PLL1_ENABLE.VALUE=TRUE +DRIVER.SYSTEM.VAR.FLASH_BASE_ADDRESS.VALUE=0x00000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_11_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_5_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_M3.VALUE=0 +DRIVER.SYSTEM.VAR.SPI5_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_TYPE_VALUE.VALUE=0x0006 +DRIVER.SYSTEM.VAR.CLKT_AVCLK2_DOMAIN_DISABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_15_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_TYPE.VALUE=NORMAL_OIWTNOWA_NONSHARED +DRIVER.SYSTEM.VAR.VIM_CHANNEL_120_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_112_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_104_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_100_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.RTP_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.MIBSPI3_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_0.VALUE=0x001F7FE0 +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_1.VALUE=0x00200000 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_11_WAIT_STATE_FREQ.VALUE=192.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_SIZE_VALUE.VALUE=0x16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_90_MAPPING.VALUE=90 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_82_MAPPING.VALUE=82 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_80_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_74_MAPPING.VALUE=74 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_72_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_66_MAPPING.VALUE=66 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_64_NAME.VALUE=sci3HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_58_MAPPING.VALUE=58 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_56_NAME.VALUE=mibspi5LowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_48_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_14_SIZE.VALUE=32_BYTES +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_8_SUB_1_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.EQEP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.RTI_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.STC_MAX_TIMEOUT.VALUE=0xFFFFFFFF +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.FLASH_EEPROM_DATA_3_WAIT_STATE_FREQ.VALUE=64.0 +DRIVER.SYSTEM.VAR.RAM_STACK_FIQ_BASE.VALUE=0x08000400 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_PERMISSION_VALUE.VALUE=0x1300 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_0_NAME.VALUE=esmHighInterrupt +DRIVER.SYSTEM.VAR.FLASH_BANK_LINK_LENGTH_7.VALUE=0x000020000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_SUB_2_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_50_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_42_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_34_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_26_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_18_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.FEE_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_10.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_LPO_LOW_TRIM_VALUE.VALUE=16 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_123_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_115_NAME.VALUE=lin2HighLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_107_NAME.VALUE=ecap4Interrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_51_MAPPING.VALUE=51 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_43_MAPPING.VALUE=43 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_35_MAPPING.VALUE=35 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_27_MAPPING.VALUE=27 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_19_MAPPING.VALUE=19 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_11.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_5_PERMISSION.VALUE=PRIV_RW_USER_RW_EXEC +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_12.VALUE=0 +DRIVER.SYSTEM.VAR.CCM_MENU.VALUE=NONE +DRIVER.SYSTEM.VAR.CLKT_RESERVED_SOURCE_ENABLE.VALUE=0x00000004 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_9_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SIZE.VALUE=512_KB +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_BASE_ADDRESS.VALUE=0x08000000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_2_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_4_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_13.VALUE=0 +DRIVER.SYSTEM.VAR.POM_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CLKT_PLL1_MUL_VAL.VALUE=9500 +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_14.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_AVCLK3_SOURCE.VALUE=VCLK +DRIVER.SYSTEM.VAR.CLKT_PLL1_FREQ.VALUE=300.00 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_1_SIZE_VALUE.VALUE=0x15 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_31_NAME.VALUE=phantomInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_23_NAME.VALUE=gioLowLevelInterrupt +DRIVER.SYSTEM.VAR.VIM_CHANNEL_15_NAME.VALUE=adc1Group1Interrupt +DRIVER.SYSTEM.VAR.ERRATA_WORKAROUND_15.VALUE=0 +DRIVER.SYSTEM.VAR.RAM_STACK_UNDEF_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.RAM_STACK_SVC_LENGTH.VALUE=0x00000100 +DRIVER.SYSTEM.VAR.CLKT_LPO_TRIM_OTP_LOC.VALUE=0xF00801B4 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_SUB_3_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_6_SUB_6_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_HANDLER_TABLE_UNDEF_ENTRY.VALUE=_undef +DRIVER.SYSTEM.VAR.VIM_CHANNEL_93_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_85_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_77_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_69_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ETPWM6_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.DCC_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_20_MAPPING.VALUE=20 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_12_MAPPING.VALUE=12 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_PERMISSION.VALUE=PRIV_RW_USER_RO_NOEXEC +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_16_BASE_ADDRESS.VALUE=0xFFF80000 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_SUB_4_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_7_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_ENDIAN_LITTLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_125_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.VIM_CHANNEL_117_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_109_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.OS_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_12_SIZE_VALUE.VALUE=0x04 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_126_MAPPING.VALUE=126 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_118_MAPPING.VALUE=118 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_98_NAME.VALUE=etpwm5Interrupt +DRIVER.SYSTEM.VAR.ECLK_PORT_BIT0_PULL.VALUE=2 +DRIVER.SYSTEM.VAR.ECLK_SUSPEND.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_PLL1_SPEADING_AMOUNT.VALUE=61 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_13_TYPE.VALUE=NORMAL_OIWTNOWA_SHARED +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_10_SUB_5_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_4_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.CORE_VFP_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.ECAP1_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.I2C_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.AJSM_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.ECLK_OSCILLATOR_FREQ.VALUE=16.000 +DRIVER.SYSTEM.VAR.CLKT_LPO_HIGH_TRIM.VALUE=100.00 +DRIVER.SYSTEM.VAR.CLKT_AVCLK4_SPL_SOURCE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_MAPPING.VALUE=9 +DRIVER.SYSTEM.VAR.VIM_ECC_INTERRUPT_MAPPED_TO_VIM.VALUE=FALSE +DRIVER.SYSTEM.VAR.CLKT_VCLK4_DOMAIN_ENABLE.VALUE=FALSE +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_3_SUB_0_DISABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_71_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_63_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_55_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_47_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_41_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_39_INT_PRAGMA_ENABLE.VALUE=1 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_33_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_25_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_17_INT_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_9_INT_TYPE.VALUE=IRQ +DRIVER.SYSTEM.VAR.SCI1_ENABLE.VALUE=0 +DRIVER.SYSTEM.VAR.CLKT_CRYSTAL_FREQ.VALUE=16.0 +DRIVER.SYSTEM.VAR.CORE_MPU_REGION_7_TYPE_VALUE.VALUE=0x0008 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_111_MAPPING.VALUE=111 +DRIVER.SYSTEM.VAR.VIM_CHANNEL_103_MAPPING.VALUE=103 +DRIVER.SYSTEM.VAR.VIM_PHANTOM_NAME.VALUE=phantomInterrupt +DRIVER.OS.VAR.OS_USERECERSIVEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_USETIMERS.VALUE=0 +DRIVER.OS.VAR.OS_USECNTSEMAPHORE.VALUE=0 +DRIVER.OS.VAR.OS_GENERATERUNTIMESTATS.VALUE=0 +DRIVER.OS.VAR.OS_USEMPU.VALUE=0 +DRIVER.OS.VAR.OS_TOTALHEAPSIZE.VALUE=8192 +DRIVER.OS.VAR.OS_USEVERBOSESTACK.VALUE=2 +DRIVER.OS.VAR.OS_TIMERPRIORITY.VALUE=0 +DRIVER.OS.VAR.OS_SVCENABLE.VALUE=0 +DRIVER.OS.VAR.OS_MAXTASKNAMELEN.VALUE=16 +DRIVER.OS.VAR.OS_MAXPRIORITIES.VALUE=5 +DRIVER.OS.VAR.OS_TIMERTASKSTACKDEPTH.VALUE=0 +DRIVER.OS.VAR.OS_COROUTINEPRIORITIES.VALUE=2 +DRIVER.OS.VAR.OS_USECOROUTINES.VALUE=0 +DRIVER.OS.VAR.OS_USEMUTEXES.VALUE=0 +DRIVER.OS.VAR.OS_CPUCLOCKHZ.VALUE=75000000 +DRIVER.OS.VAR.OS_USEMALLOCFAILEDHOOK.VALUE=0 +DRIVER.OS.VAR.OS_MINSTACKSIZE.VALUE=128 +DRIVER.OS.VAR.OS_SYSTEM_MODE.VALUE=0x1F +DRIVER.OS.VAR.OS_USEPREEMPTION.VALUE=1 +DRIVER.OS.VAR.OS_IDLESHOULDYIELD.VALUE=1 +DRIVER.OS.VAR.OS_USEIDLEHOOK.VALUE=0 +DRIVER.OS.VAR.OS_TICKRATEHZ.VALUE=1000 +DRIVER.OS.VAR.OS_TIMERPQUEUELENGTH.VALUE=0 +DRIVER.OS.VAR.OS_USETRACE.VALUE=0 +DRIVER.OS.VAR.OS_USESTACK.VALUE=0 +DRIVER.OS.VAR.OS_USETICKHOOK.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL93_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL85_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL77_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL69_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL21_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL13_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL94_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL86_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL78_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL3_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL41_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL33_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL25_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL17_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL88_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL9_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL81_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL73_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL65_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL57_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL49_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL2_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL50_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL42_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL34_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL26_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL18_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL8_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL11_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL70_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL62_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL54_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL46_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL38_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL1_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL94_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL86_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL78_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL7_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL71_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL63_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL55_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL47_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL39_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL0_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL40_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL32_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL24_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL16_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL10_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL6_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL89_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL4_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_LEVEL.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL91_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL83_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL75_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL67_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL59_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_INT_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL92_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL84_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL76_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL68_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL5_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL61_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL53_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL45_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL37_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL29_ENABLE.VALUE=0 +DRIVER.ESM.VAR.ESM_GROUP0_CHANNEL90_INT_LEVEL.VALUE=0 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+DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT1_BIT7_ENA.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT2_PULDIS.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT3_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT7_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT4_LVL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT2_ENA.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT5_PDR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT4_POL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT2_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_DOUT.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT6_PULDIS.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT4_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_PDR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORTB_ENABLE.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT1_BIT5_LVL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT3_ENA.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT6_PDR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT5_POL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT3_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT3_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT6_DOUT.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT7_PULL.VALUE=1 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_LVL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT5_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_PDR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_POL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT6_LVL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT7_PULDIS.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT4_ENA.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT7_PDR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT6_POL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT0_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT4_DIR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT0_PULDIS.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_DOUT.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_LVL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT6_PSL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT2_PDR.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_POL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT7_LVL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT5_ENA.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT1_BIT7_POL.VALUE=0 +DRIVER.GIO.VAR.GIO_PORT0_BIT1_PSL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI4_BASE.VALUE=0xFFF7E700 +DRIVER.SCI.VAR.SCI4_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI3_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI4_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI4_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI2_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI1_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.SCI.VAR.SCI4_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI3_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI4_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI4_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI1_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI4_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI3_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI4_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_BASE_PORT.VALUE=0xFFF7E740 +DRIVER.SCI.VAR.SCI4_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI2_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI4_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI3_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI3_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI3_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI1_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_BASE_PORT.VALUE=0xFFF7E640 +DRIVER.SCI.VAR.SCI3_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI3_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_WAKEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI2_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI2_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI4_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI3_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI1_BASE.VALUE=0xFFF7E400 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_BREAKINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_LENGTH.VALUE=8 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI2_BAUDRATE.VALUE=9600 +DRIVER.SCI.VAR.SCI1_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_STOPBITS.VALUE=2 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI2_RXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI2_BASE.VALUE=0xFFF7E600 +DRIVER.SCI.VAR.SCI2_FEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_FUN.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI3_ACTUALBAUDRATE.VALUE=9606 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_TXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_BREAKINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_TIMMINGMODE.VALUE=1 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI4_OEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI2_PEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.SCI.VAR.SCI3_BASE.VALUE=0xFFF7E500 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SCI.VAR.SCI4_WAKEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_FEINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI3_PORT_BIT0_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI1_OEINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SCI.VAR.SCI1_TXINTENA.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SCI.VAR.SCI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SCI.VAR.SCI2_RXINTLVL.VALUE=0 +DRIVER.SCI.VAR.SCI3_PORT_BIT1_DIR.VALUE=0 +DRIVER.SCI.VAR.SCI3_BASE_PORT.VALUE=0xFFF7E540 +DRIVER.SCI.VAR.SCI4_PARITYENA.VALUE=0 +DRIVER.SCI.VAR.SCI4_CLKMODE.VALUE=1 +DRIVER.SCI.VAR.SCI2_EVENPARITY.VALUE=0 +DRIVER.SCI.VAR.SCI2_PRESCALE.VALUE=487 +DRIVER.SCI.VAR.SCI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI4_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI2_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_BASE_RAM.VALUE=0xFF080000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.MIBSPI.VAR.MIBSPI4_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI4_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI4_BASE_RAM.VALUE=0xFF060000 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI4_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_CSNR.VALUE=CS_1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_BASE.VALUE=0xFFF7F400 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_TXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ENABLE.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_BITERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_CSNR.VALUE=CS_2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSNR.VALUE=CS_3 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_BASE.VALUE=0xFFF7F600 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_CSNR.VALUE=CS_4 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI2_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_DLENERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_PARITYENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG7_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_WAITENA3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG1_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TIMEOUTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG1_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_CLKMOD.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT4_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TIMEOUTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PHASE3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PARERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI4_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG4_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG6_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_T2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_RXINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG7_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_DEYSNCLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG5_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_LENGTH.VALUE=8 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_WDELAY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI1_TG5_BUF_CSNR.VALUE=CS_5 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE.VALUE=0xFFF7F800 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_MASTER.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_BUF_CSNR.VALUE=CS_6 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG0_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG4_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI3_C2EDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG7_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI2_TG2_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG2_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_LOCK.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_OVRNINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG7_BUF_CSNR.VALUE=CS_7 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_TG3_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_C2TDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_OVRNINTLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_TG0_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_BITERRLVL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG6_BUF_MODE.VALUE=4 +DRIVER.MIBSPI.VAR.MIBSPI5_DEYSNCENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG6_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI4_POLARITY3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG1_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_TG6_TRGSRC.VALUE=TRG_DISABLED +DRIVER.MIBSPI.VAR.MIBSPI1_SHIFTDIR3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_TG0_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_FUN.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT17_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT25_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG2_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI2_TG4_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_T2CDELAY.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT5_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG2_TRGEVT.VALUE=TRG_ALWAYS +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSHOLD_LASTBUF.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI1_CSDEF.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_CS_ENCODE.VALUE=0xFF +DRIVER.MIBSPI.VAR.MIBSPI5_TG7_USE_CS_ENCODE.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TXINTENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG3_BUF_WDEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_TG2_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG6_PRST.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE0.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI2_TG3_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE1.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG1_LENGTH.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI3_TG3_BUF_CSHOLD.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE2.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN0.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.MIBSPI.VAR.MIBSPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PRESCALE3.VALUE=74 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN1.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI3_DLENERRENA.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL2.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_TG5_ONESHOT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA0.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG5_BUF_DFSEL.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_TG0_BUF_CSNR.VALUE=CS_0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN2.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.MIBSPI.VAR.MIBSPI5_PARPOL3.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI4_PARITYENA1.VALUE=0 +DRIVER.MIBSPI.VAR.MIBSPI3_CHARLEN3.VALUE=16 +DRIVER.MIBSPI.VAR.MIBSPI1_TG1_TRGSRC.VALUE=TRG_DISABLED +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI3_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI1_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI1_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI3_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_BASE_PORT.VALUE=0xFFF7F618 +DRIVER.SPI.VAR.SPI5_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BASE_RAM.VALUE=0xFF0E0000 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI4_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI1_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI4_BASE_RAM.VALUE=0xFF060000 +DRIVER.SPI.VAR.SPI1_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI1_BASE.VALUE=0xFFF7F400 +DRIVER.SPI.VAR.SPI3_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI4_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI5_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_PORT.VALUE=0xFFF7FC18 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_BASE.VALUE=0xFFF7F600 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI3_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI5_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI3_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI2_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE.VALUE=0xFFF7F800 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI3_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI4_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BASE_PORT.VALUE=0xFFF7F818 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI2_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_BASE_RAM.VALUE=0xFF0C0000 +DRIVER.SPI.VAR.SPI3_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI1_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI4_BASE.VALUE=0xFFF7FA00 +DRIVER.SPI.VAR.SPI3_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI2_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI2_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI2_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI4_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_BASE_PORT.VALUE=0xFFF7F418 +DRIVER.SPI.VAR.SPI5_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_BASE.VALUE=0xFFF7FC00 +DRIVER.SPI.VAR.SPI2_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI2_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI5_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI5_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT26_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT18_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI2_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_WDELAY2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_WDELAY3.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_POLARITY0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY1.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT4_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT25_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT17_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_POLARITY2.VALUE=0 +DRIVER.SPI.VAR.SPI1_OVRNINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_DEYSNCENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_POLARITY3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_T2CDELAYACTUAL.VALUE=13.333 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT0_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_BASE_RAM.VALUE=0xFF080000 +DRIVER.SPI.VAR.SPI2_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT11_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI2_ENABLEHIGHZ.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_TIMEOUTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_BITERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_RXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_BITERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR0.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL0.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR1.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI4_C2TDELAYACTUAL.VALUE=26.667 +DRIVER.SPI.VAR.SPI3_SHIFTDIR2.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE1.VALUE=0 +DRIVER.SPI.VAR.SPI3_SHIFTDIR3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PARPOL3.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE2.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT9_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT27_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT19_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_PHASE3.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT4_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT1_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI1_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE0.VALUE=74 +DRIVER.SPI.VAR.SPI1_PORT_BIT10_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_C2EDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI5_PRESCALE1.VALUE=74 +DRIVER.SPI.VAR.SPI5_PRESCALE2.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT5_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_PRESCALE3.VALUE=74 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI3_PORT_BIT8_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_PORT_BIT3_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_BASE_PORT.VALUE=0xFFF7FA18 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT0_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI5_OVRNINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI2_ACTUALBAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT1_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_MASTER.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT4_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT5_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT1_DOUT.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT2_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_T2CDELAY.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT9_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_PORT_BIT11_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI5_BASE_RAM.VALUE=0xFF0A0000 +DRIVER.SPI.VAR.SPI5_CHARLEN0.VALUE=16 +DRIVER.SPI.VAR.SPI3_PORT_BIT10_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI3_PORT_BIT2_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI5_CHARLEN1.VALUE=16 +DRIVER.SPI.VAR.SPI2_PARERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN2.VALUE=16 +DRIVER.SPI.VAR.SPI1_PORT_BIT4_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI5_CHARLEN3.VALUE=16 +DRIVER.SPI.VAR.SPI5_PORT_BIT25_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT17_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI5_PORT_BIT11_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI4_PARERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI2_PORT_BIT11_DIR.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_DLENERRENA.VALUE=0 +DRIVER.SPI.VAR.SPI4_RXINTENA.VALUE=0 +DRIVER.SPI.VAR.SPI3_RAM_PARITY_ENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA0.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT0_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA0.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA1.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA1.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_DLENERRLVL.VALUE=0 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_DEYSNCLVL.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI1_WAITENA2.VALUE=0 +DRIVER.SPI.VAR.SPI5_PARITYENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_WAITENA3.VALUE=0 +DRIVER.SPI.VAR.SPI1_PORT_BIT3_PSL.VALUE=1 +DRIVER.SPI.VAR.SPI3_PORT_BIT1_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT8_PULL.VALUE=2 +DRIVER.SPI.VAR.SPI2_PORT_BIT9_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE0.VALUE=1000.000 +DRIVER.SPI.VAR.SPI1_T2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE1.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_BAUDRATE2.VALUE=1000.000 +DRIVER.SPI.VAR.SPI4_TXINTLVL.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT3_DIR.VALUE=1 +DRIVER.SPI.VAR.SPI2_PORT_BIT10_FUN.VALUE=1 +DRIVER.SPI.VAR.SPI5_PORT_BIT5_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI4_BAUDRATE3.VALUE=1000.000 +DRIVER.SPI.VAR.SPI2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.SPI.VAR.SPI1_TIMEOUTENA.VALUE=0 +DRIVER.SPI.VAR.SPI5_CLKMOD.VALUE=1 +DRIVER.SPI.VAR.SPI4_PORT_BIT8_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PORT_BIT9_DOUT.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE0.VALUE=0 +DRIVER.SPI.VAR.SPI2_C2EDELAYACTUAL.VALUE=0.000 +DRIVER.SPI.VAR.SPI1_PORT_BIT5_PDR.VALUE=0 +DRIVER.SPI.VAR.SPI3_PHASE1.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_RAMBASE.VALUE=0xFF1C0000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BASE.VALUE=0xFFF7DC00 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_BASE.VALUE=0xFFF7DE00 +DRIVER.CAN.VAR.CAN_1_RAMBASE.VALUE=0xFF1E0000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BASE.VALUE=0xFFF7E000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_TQ.VALUE=133.333 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_1_NOMINAL_BIT_TIME.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_BASE.VALUE=0xFFF7E200 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_SAMPLE_POINT_REFERENCE.VALUE=75 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_1_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_4_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_1_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_4_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_3_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_BRPE.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_2_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_ID.VALUE=30 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_ID.VALUE=22 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_ID.VALUE=14 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_4_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_ID.VALUE=31 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_ID.VALUE=23 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_20_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_ID.VALUE=15 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_12_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PORT_RX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_BRP.VALUE=9 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_ID.VALUE=40 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_ID.VALUE=32 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_ID.VALUE=24 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_ID.VALUE=16 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_ID.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MASK.VALUE=0x1FFFFFFF +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_40_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_32_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_24_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_16_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_ID.VALUE=41 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_ID.VALUE=33 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_ID.VALUE=25 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_ID.VALUE=17 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_ID.VALUE=9 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_BAUDRATE.VALUE=500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_IDENTIFIER_MODE.VALUE=0x40000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_RAMBASE.VALUE=0xFF180000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_AUTO_BUS_ON_TIME.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_PORT_TX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_ID.VALUE=50 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_ID.VALUE=42 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_ID.VALUE=34 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_ID.VALUE=26 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_ID.VALUE=18 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_PIN_MODE.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_30_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_22_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_14_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_7_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_ENABLE.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_ID.VALUE=51 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_ID.VALUE=43 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_ID.VALUE=35 +DRIVER.CAN.VAR.CAN_3_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_ID.VALUE=27 +DRIVER.CAN.VAR.CAN_3_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_ID.VALUE=19 +DRIVER.CAN.VAR.CAN_3_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_50_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_42_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_34_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_26_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_18_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ID.VALUE=60 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ID.VALUE=52 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ID.VALUE=44 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ID.VALUE=36 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ID.VALUE=28 +DRIVER.CAN.VAR.CAN_1_MESSAGE_63_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_55_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_47_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_39_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_1_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SHIFT.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_RX_PULDIS.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ID.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_BRP_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_2_BRPE_FREQ.VALUE=7.500 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PROP_SEG.VALUE=6 +DRIVER.CAN.VAR.CAN_1_MESSAGE_41_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_33_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_25_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_17_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ID.VALUE=61 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ID.VALUE=53 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ID.VALUE=45 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ID.VALUE=37 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ID.VALUE=29 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_11_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_3_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ID.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_40_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_32_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_24_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_16_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_8_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_10_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_SAMPLE_POINT.VALUE=73.333 +DRIVER.CAN.VAR.CAN_2_MESSAGE_51_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_43_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_35_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_27_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_19_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ID.VALUE=62 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ID.VALUE=54 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ID.VALUE=46 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ID.VALUE=38 +DRIVER.CAN.VAR.CAN_1_MESSAGE_64_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_56_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_48_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_PORT_TX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_1_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_21_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_13_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_7_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_5_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_60_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_52_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_44_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_36_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_28_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ID.VALUE=3 +DRIVER.CAN.VAR.CAN_1_PORT_RX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_4_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_PHASE_SEG.VALUE=4 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_1_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ID.VALUE=63 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ID.VALUE=55 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ID.VALUE=47 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ID.VALUE=39 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_SJW.VALUE=4 +DRIVER.CAN.VAR.CAN_3_RAMBASE.VALUE=0xFF1A0000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIN.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_3_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_59_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_61_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_53_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_45_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_37_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_29_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PDR.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_ID.VALUE=4 +DRIVER.CAN.VAR.CAN_1_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_DIR.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_6_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_DOUT.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_64_ID.VALUE=64 +DRIVER.CAN.VAR.CAN_3_MESSAGE_56_ID.VALUE=56 +DRIVER.CAN.VAR.CAN_3_MESSAGE_48_ID.VALUE=48 +DRIVER.CAN.VAR.CAN_3_MESSAGE_31_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_23_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_15_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_57_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_49_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_3_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_NOMINAL_AUTO_BUS_ON_TIME.VALUE=0.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_SYNC.VALUE=1 +DRIVER.CAN.VAR.CAN_2_PORT_TX_PULL.VALUE=2 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_2_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_1_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_64_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_63_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_56_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_55_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_48_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_47_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_39_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_61_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_53_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_45_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_37_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_29_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_ID.VALUE=10 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_ID.VALUE=5 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_64_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_56_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_48_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_20_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_12_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_4_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_50_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_42_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_34_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_26_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_18_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_ID.VALUE=57 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_ID.VALUE=49 +DRIVER.CAN.VAR.CAN_3_MESSAGE_41_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_33_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_25_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_17_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_9_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_41_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_33_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_25_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_17_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_NOMINAL_BIT_RATE.VALUE=500.000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_51_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_43_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_35_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_27_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_19_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_9_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_41_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_33_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_25_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_17_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_11_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_4_MESSAGE_21_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_13_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_5_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_11_ID.VALUE=11 +DRIVER.CAN.VAR.CAN_2_MESSAGE_6_ID.VALUE=6 +DRIVER.CAN.VAR.CAN_3_PROPAGATION_DELAY.VALUE=700 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_50_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_42_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_34_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_26_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_18_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_AUTO_RETRANSMISSION.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_20_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_12_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_9_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_58_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_58_ID.VALUE=58 +DRIVER.CAN.VAR.CAN_1_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_3_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_31_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_23_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_4_MESSAGE_15_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_7_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_10_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_PORT_TX_PSL.VALUE=1 +DRIVER.CAN.VAR.CAN_3_MESSAGE_60_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_52_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_44_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_36_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_28_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_62_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_54_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_46_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_38_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_20_ID.VALUE=20 +DRIVER.CAN.VAR.CAN_2_MESSAGE_12_ID.VALUE=12 +DRIVER.CAN.VAR.CAN_2_MESSAGE_7_ID.VALUE=7 +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_4_MESSAGE_57_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_49_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_59_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_51_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_43_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_35_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_27_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_19_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_5_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_61_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_53_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_45_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_40_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_37_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_32_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_29_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_24_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_16_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_10_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_1_MESSAGE_8_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_2_MASK.VALUE=0x000007FF +DRIVER.CAN.VAR.CAN_3_MESSAGE_59_ID.VALUE=59 +DRIVER.CAN.VAR.CAN_3_MESSAGE_50_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_42_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_34_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_26_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_18_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_AUTO_BUS_ON_TR.VALUE=0 +DRIVER.CAN.VAR.CAN_2_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_5_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_4_DLC.VALUE=8 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_63_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_62_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_55_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_54_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_47_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_46_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_EOB.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_39_DIR.VALUE=0x20000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_38_INT_ENA_REF.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_PORT_RX_FUN.VALUE=1 +DRIVER.CAN.VAR.CAN_4_MESSAGE_51_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_43_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_35_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_27_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_19_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_10_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_BOOL_ENA.VALUE=0 +DRIVER.CAN.VAR.CAN_1_MESSAGE_58_INT_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_21_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_1_MESSAGE_13_ENA.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_30_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_22_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_4_MESSAGE_14_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_6_RTR.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_3_MESSAGE_2_INT_LEVEL.VALUE=0x00000000 +DRIVER.CAN.VAR.CAN_2_MESSAGE_21_ID.VALUE=21 +DRIVER.CAN.VAR.CAN_2_MESSAGE_13_ID.VALUE=13 +DRIVER.CAN.VAR.CAN_2_MESSAGE_8_ID.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC2_BND.VALUE=2 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC2_ACTUAL_CYCLE_TIME.VALUE=106.67 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP0_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_PRESCALER.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_RAMBASE.VALUE=0xFF3A0000 +DRIVER.ADC.VAR.ADC2_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP0_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PARITY_ENABLE.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC1_ACTUAL_CYCLE_TIME.VALUE=106.67 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_RAMBASE.VALUE=0xFF3E0000 +DRIVER.ADC.VAR.ADC1_BASE.VALUE=0xFFF7C000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_DIR.VALUE=0 +DRIVER.ADC.VAR.ADC2_RAM_PARITY_ENA.VALUE=0x00000005 +DRIVER.ADC.VAR.ADC2_GROUP2_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP2_LENGTH.VALUE=32 +DRIVER.ADC.VAR.ADC1_GROUP0_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP2_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_BND.VALUE=8 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.ADC.VAR.ADC2_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_PRESCALE.VALUE=7 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_BASE.VALUE=0xFFF7C200 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PDR.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_GROUP0_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONVERSION_TIME.VALUE=1.300 +DRIVER.ADC.VAR.ADC1_GROUP0_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC1_GROUP0_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP1_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PORT_BIT0_PSL.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP2_EXTENDED_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_LENGTH.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP1_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN3_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_HW_TRIGGER_SOURCE_ALT.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN25_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN29_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN30_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_CYCLE_TIME.VALUE=100.00 +DRIVER.ADC.VAR.ADC2_GROUP0_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN7_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC1_GROUP1_PIN0_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ID_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_DISCHARGE_TIME.VALUE=0.00 +DRIVER.ADC.VAR.ADC1_GROUP2_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_ALT_TRIG_COMP.VALUE=1 +DRIVER.ADC.VAR.ADC1_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_ALT_TRIG.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_RAM_PARITY_ENA.VALUE=0 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN4_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_DISCHARGE_PRESCALER.VALUE=0 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN8_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN26_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN18_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_RESOLUTION.VALUE=12_BIT +DRIVER.ADC.VAR.ADC2_GROUP2_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN1_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN11_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN31_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN23_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN15_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_HW_TRIGGER_SOURCE.VALUE=EVENT +DRIVER.ADC.VAR.ADC2_GROUP0_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN27_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN19_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_PRESCALE.VALUE=7 +DRIVER.ADC.VAR.ADC2_GROUP0_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP2_PINS.VALUE=0 +DRIVER.ADC.VAR.ADC2_PORT_BIT0_PULL.VALUE=2 +DRIVER.ADC.VAR.ADC1_LENGTH.VALUE=64 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN20_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN12_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_CHANNEL_TOTAL_TIME.VALUE=0.000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_CONTINUOUS_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN5_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_ACTUAL_SAMPLE_TIME.VALUE=320.01 +DRIVER.ADC.VAR.ADC1_GROUP0_SCAN_TIME.VALUE=0.000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN21_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_PIN13_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP0_TRIGGER_EDGE_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN9_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_SAMPLE_TIME.VALUE=300.00 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN17_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_FIFO_SIZE.VALUE=16 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN2_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP1_PIN10_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP2_PIN6_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN24_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_PIN16_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN22_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC2_GROUP2_PIN14_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_PIN28_ENABLE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP1_TRIGGER_MODE.VALUE=0x00000000 +DRIVER.ADC.VAR.ADC1_GROUP0_ACTUAL_DISCHARGE_TIME.VALUE=0.00 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN1_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN1_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BASE_PORT.VALUE=0xFFF7E440 +DRIVER.LIN.VAR.LIN2_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN2_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN2_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_MAXPRESCALE.VALUE=3370 +DRIVER.LIN.VAR.LIN2_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN1_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN1_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN2_RXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_WAKEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_FEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN2_IDINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN2_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN2_TOAWUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BASE.VALUE=0xFFF7E400 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN2_TOINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN2_BEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_ACTUALBAUDRATE.VALUE=20.032 +DRIVER.LIN.VAR.LIN1_FEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_OEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN1_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN2_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_FUN.VALUE=4 +DRIVER.LIN.VAR.LIN2_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN1_PORT_BIT0_PSL.VALUE=1 +DRIVER.LIN.VAR.LIN2_RXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_WAKEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_IDINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PRESCALE.VALUE=233 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN2_BASE.VALUE=0xFFF7E600 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN2_PBEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_TOINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PSL.VALUE=2 +DRIVER.LIN.VAR.LIN2_BASE_PORT.VALUE=0xFFF7E640 +DRIVER.LIN.VAR.LIN1_BAUDRATE.VALUE=20.000 +DRIVER.LIN.VAR.LIN2_TOAWUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PSL.VALUE=4 +DRIVER.LIN.VAR.LIN2_MAXBAUDRATE.VALUE=22.255 +DRIVER.LIN.VAR.LIN1_RXINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_FEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PULL.VALUE=2 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_TX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN2_NREINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_ISFEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_ISFEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_ACTUALBAUDRATE.VALUE=20.032 +DRIVER.LIN.VAR.LIN1_IDINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_TOA3WUSINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_TOINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PARITYENA.VALUE=0 +DRIVER.LIN.VAR.LIN1_BEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_RXINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_HGENCTRL.VALUE=1 +DRIVER.LIN.VAR.LIN1_PRESCALE.VALUE=233 +DRIVER.LIN.VAR.LIN1_ISFEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN2_LENGTH.VALUE=8 +DRIVER.LIN.VAR.LIN2_MAXPRESCALE.VALUE=3370 +DRIVER.LIN.VAR.LIN2_CEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BREAKINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_TOA3WUSINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_MSTMOD.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_BEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PBEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_SDEL.VALUE=1 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN1_MAXBAUDRATE.VALUE=22.255 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.LIN.VAR.LIN1_SBREAK.VALUE=13 +DRIVER.LIN.VAR.LIN2_OEINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_FUN.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT2_DIR.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT0_PDR.VALUE=0 +DRIVER.LIN.VAR.LIN2_PORT_BIT1_FUN.VALUE=2 +DRIVER.LIN.VAR.LIN2_CEINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN1_NREINTENA.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_BREAKINTLVL.VALUE=0x00000000 +DRIVER.LIN.VAR.LIN2_RX_MASK.VALUE=0xFF +DRIVER.LIN.VAR.LIN1_PORT_BIT2_PULDIS.VALUE=0 +DRIVER.HET.VAR.HET2_EDGE5_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM5_PERIOD_PRESCALER.VALUE=149888 +DRIVER.HET.VAR.HET2_PWM0_PERIOD_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT0_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_INT_X0.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE4_BOTH.VALUE=0 +DRIVER.HET.VAR.HET1_BIT1_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT6_HRSHARE.VALUE=0x00000008 +DRIVER.HET.VAR.HET2_INT_X1.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM2_DUTY.VALUE=50 +DRIVER.HET.VAR.HET1_BIT29_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT0_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000 +DRIVER.HET.VAR.HET2_PWM3_PERIOD.VALUE=1000.000 +DRIVER.HET.VAR.HET2_PWM1_PIN_SELECT.VALUE=10 +DRIVER.HET.VAR.HET2_BIT20_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT12_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT3_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_INT_X2.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X3.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM2_DUTYTIME.VALUE=500.053 +DRIVER.HET.VAR.HET2_INT_X4.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM6_ACTION.VALUE=3 +DRIVER.HET.VAR.HET1_PWM0_DUTY_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT4_PULL.VALUE=1 +DRIVER.HET.VAR.HET2_PWM3_ENA.VALUE=0 +DRIVER.HET.VAR.HET2_BIT4_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X5.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_IGNORE_SUSPEND_ENABLE.VALUE=0x00020000 +DRIVER.HET.VAR.HET1_BIT30_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT26_HRSHARE.VALUE=0x00002000 +DRIVER.HET.VAR.HET1_BIT22_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT18_HRSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT14_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_PWM4_ACTUALPERIOD.VALUE=1000.106 +DRIVER.HET.VAR.HET2_BIT3_PSL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X6.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_EDGE0_PIN_SELECT.VALUE=9 +DRIVER.HET.VAR.HET1_BIT28_PDR.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_BIT7_DOUT.VALUE=0 +DRIVER.HET.VAR.HET2_INT_X7.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT7_DIR.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X8.VALUE=0x00000000 +DRIVER.HET.VAR.HET1_PWM3_PERIOD_LVL.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT26_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT18_PULDIS.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_BIT10_ANDSHARE.VALUE=0x00000000 +DRIVER.HET.VAR.HET2_INT_X9.VALUE=0x00000000 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+DRIVER.DMM.VAR.DMM_PORT_BIT14_PSL.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT18_DIR.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT2_PULL.VALUE=2 +DRIVER.DMM.VAR.DMM_PORT_BIT6_PULDIS.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT16_PDR.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT5_DOUT.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT13_PULL.VALUE=2 +DRIVER.DMM.VAR.DMM_PORT_BIT16_DOUT.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT17_FUN.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT15_PSL.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT17_PULDIS.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT17_PDR.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT10_PULDIS.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT18_FUN.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT16_PSL.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT3_PULL.VALUE=2 +DRIVER.DMM.VAR.DMM_PORT_BIT0_DIR.VALUE=1 +DRIVER.DMM.VAR.DMM_PORT_BIT18_PDR.VALUE=0 +DRIVER.DMM.VAR.DMM_PORT_BIT6_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_STOPBITS.VALUE=2 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C1_BASE_PORT.VALUE=0xFFF7D44C +DRIVER.I2C.VAR.I2C2_PARITYENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_DATACOUNT.VALUE=8 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C1_IGNACK.VALUE=0 +DRIVER.I2C.VAR.I2C1_ADDRMODE.VALUE=7BIT_AMODE +DRIVER.I2C.VAR.I2C2_ALINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_TXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C1_BC_VALUE.VALUE=0x0003 +DRIVER.I2C.VAR.I2C1_TXRX_VALUE.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICXRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_MODCLK.VALUE=8 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_DIR.VALUE=0 +DRIVER.I2C.VAR.I2C1_ALINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_PRESCALE.VALUE=8 +DRIVER.I2C.VAR.I2C2_ARDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_DIR.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_FUN.VALUE=0 +DRIVER.I2C.VAR.I2C1_MSMODE.VALUE=1 +DRIVER.I2C.VAR.I2C1_AASLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_RM_ENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_FUN.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C2_SCDLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_STPCND.VALUE=1 +DRIVER.I2C.VAR.I2C1_ALINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C1_ARDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ARDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICRRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_BASE_PORT.VALUE=0xFFF7D54C +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C2_DATACOUNT.VALUE=8 +DRIVER.I2C.VAR.I2C1_LENGTH.VALUE=8 +DRIVER.I2C.VAR.I2C1_TXRX.VALUE=TRANSMITTER +DRIVER.I2C.VAR.I2C2_NACKINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_IGNACK.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_STACND.VALUE=1 +DRIVER.I2C.VAR.I2C2_TXRX.VALUE=TRANSMITTER +DRIVER.I2C.VAR.I2C1_PORT_BIT0_DIR.VALUE=0 +DRIVER.I2C.VAR.I2C1_ARDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICRRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C1_PARITYENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_BASE.VALUE=0xFFF7D400 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_DIR.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_FUN.VALUE=0 +DRIVER.I2C.VAR.I2C1_NACKINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_NACKINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_BAUDRATE.VALUE=100 +DRIVER.I2C.VAR.I2C1_AAS.VALUE=0 +DRIVER.I2C.VAR.I2C1_BCM.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_MSMODE.VALUE=1 +DRIVER.I2C.VAR.I2C2_STOPBITS.VALUE=2 +DRIVER.I2C.VAR.I2C1_BC.VALUE=8_BIT +DRIVER.I2C.VAR.I2C1_PORT_BIT1_FUN.VALUE=0 +DRIVER.I2C.VAR.I2C2_EVENPARITY.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICRRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C1_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C2_BASE.VALUE=0xFFF7D500 +DRIVER.I2C.VAR.I2C2_AASLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_AAS.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICCH.VALUE=37 +DRIVER.I2C.VAR.I2C2_BCM.VALUE=0 +DRIVER.I2C.VAR.I2C2_BC.VALUE=2_BIT +DRIVER.I2C.VAR.I2C1_MODCLK.VALUE=8 +DRIVER.I2C.VAR.I2C1_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_ICCL.VALUE=37 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PDR.VALUE=0 +DRIVER.I2C.VAR.I2C2_ADDRMODE.VALUE=7BIT_AMODE +DRIVER.I2C.VAR.I2C2_FDF.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C1_RXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PSL.VALUE=1 +DRIVER.I2C.VAR.I2C2_BC_VALUE.VALUE=0x0003 +DRIVER.I2C.VAR.I2C1_PORT_BIT0_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C1_ICXRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICCH.VALUE=37 +DRIVER.I2C.VAR.I2C1_NACKINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICCL.VALUE=37 +DRIVER.I2C.VAR.I2C2_PORT_BIT1_DOUT.VALUE=0 +DRIVER.I2C.VAR.I2C1_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C1_TXDMA.VALUE=0 +DRIVER.I2C.VAR.I2C2_LENGTH.VALUE=8 +DRIVER.I2C.VAR.I2C1_EVENPARITY.VALUE=0 +DRIVER.I2C.VAR.I2C1_RM_ENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ICRRDYINTLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_ALINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_PRESCALE.VALUE=8 +DRIVER.I2C.VAR.I2C2_PORT_BIT0_PULDIS.VALUE=0 +DRIVER.I2C.VAR.I2C1_SCDLVL.VALUE=0 +DRIVER.I2C.VAR.I2C2_SCD.VALUE=0 +DRIVER.I2C.VAR.I2C1_PORT_BIT1_PULL.VALUE=2 +DRIVER.I2C.VAR.I2C2_TXRX_VALUE.VALUE=0 +DRIVER.I2C.VAR.I2C1_STPCND.VALUE=1 +DRIVER.I2C.VAR.I2C2_ICXRDYINTENA.VALUE=0 +DRIVER.I2C.VAR.I2C2_ADDRMODE_VALUE.VALUE=0x0001 +DRIVER.I2C.VAR.I2C1_BAUDRATE.VALUE=100 +DRIVER.I2C.VAR.I2C2_STACND.VALUE=1 +DRIVER.I2C.VAR.I2C2_RXDMA.VALUE=0 +DRIVER.DCC.VAR.DCC1_ENABLE_KEY.VALUE=10 +DRIVER.DCC.VAR.PINMUX_BASE.VALUE=0xFFFFEA00 +DRIVER.DCC.VAR.DCC1_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.PINMUX_BASE_PORT.VALUE=0xFFFFEA40 +DRIVER.DCC.VAR.DCC2_ENABLE_ERROR_INTERRUPT.VALUE=0xA +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_VALID0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLKT_N2HET2_0_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_FREQ.VALUE=0 +DRIVER.DCC.VAR.DCC2_DETECTION_TIME.VALUE=2500.00 +DRIVER.DCC.VAR.DCC2_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1_VALUE.VALUE=0x0002 +DRIVER.DCC.VAR.DCC1_CLKT_N2HET1_31_FREQ.VALUE=1 +DRIVER.DCC.VAR.DCC2_COUNT0_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC2_CLOCK_SOURCE1.VALUE=VCLK +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_FREQ.VALUE=16.0 +DRIVER.DCC.VAR.DCC1_VALID0_SEED.VALUE=792 +DRIVER.DCC.VAR.DCC1_BASE.VALUE=0xFFFFEC00 +DRIVER.DCC.VAR.DCC2_COUNT1_SEED.VALUE=0 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1_FREQ.VALUE=300.0 +DRIVER.DCC.VAR.DCC1_CLOCK_DRIFT.VALUE=1.0 +DRIVER.DCC.VAR.DCC1_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC1_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_ENABLE_SINGLESHOT_MODE.VALUE=0x5 +DRIVER.DCC.VAR.DCC2_BASE.VALUE=0xFFFFF400 +DRIVER.DCC.VAR.DCC1_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_DONE_INTERRUPT_ENABLE.VALUE=0xA +DRIVER.DCC.VAR.DCC2_ENABLE_KEY.VALUE=0xA +DRIVER.DCC.VAR.DCC1_COUNT0_SEED.VALUE=39204 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0_VALUE.VALUE=0x0001 +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE0.VALUE=OSCIN +DRIVER.DCC.VAR.DCC1_CLOCK_SOURCE1.VALUE=PLL1 +DRIVER.DCC.VAR.CLKT_TCK_FREQ.VALUE=12.0 +DRIVER.DCC.VAR.DCC1_COUNT1_SEED.VALUE=742500 +DRIVER.PINMUX.VAR.EQEP2A_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_SOC4A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.ETPWM_TIME_BASE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX61_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX50_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX42_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX34_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX26_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX18_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_96_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_88_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_81_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_73_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_65_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX30_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX30_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP5_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.EMIF_OUTPUT_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX10.VALUE="PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT" +DRIVER.PINMUX.VAR.MUX11_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX11.VALUE="PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_ETMDATA_08 | PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_E7_ETMDATA_10" +DRIVER.PINMUX.VAR.PINMUX20.VALUE="PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6" +DRIVER.PINMUX.VAR.PINMUX12.VALUE="PINMUX_BALL_E6_ETMDATA_11 | PINMUX_BALL_E13_ETMDATA_12 | PINMUX_BALL_E12_ETMDATA_13 | PINMUX_BALL_E11_ETMDATA_14" +DRIVER.PINMUX.VAR.PINMUX21.VALUE="PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MIBSPI1NCS_0 | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_MIBSPI1NCS_2" +DRIVER.PINMUX.VAR.PINMUX13.VALUE="PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_K15_ETMDATA_16 | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_M15_ETMDATA_18" +DRIVER.PINMUX.VAR.ECAP3_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX30.VALUE="PINMUX_BALL_E18_N2HET1_08 | PINMUX_BALL_V7_N2HET1_09 | PINMUX_BALL_D19_N2HET1_10 | PINMUX_BALL_E3_N2HET1_11" +DRIVER.PINMUX.VAR.PINMUX22.VALUE="PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0" +DRIVER.PINMUX.VAR.PINMUX14.VALUE="PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_E5_ETMDATA_20 | PINMUX_BALL_F5_ETMDATA_21 | PINMUX_BALL_G5_ETMDATA_22" +DRIVER.PINMUX.VAR.MUX92_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX31.VALUE="PINMUX_BALL_B4_N2HET1_12 | PINMUX_BALL_N2_N2HET1_13 | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16" +DRIVER.PINMUX.VAR.PINMUX23.VALUE="PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_B2_MIBSPI3NCS_2 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA" +DRIVER.PINMUX.VAR.PINMUX15.VALUE="PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_L5_ETMDATA_24 | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_N5_ETMDATA_26" +DRIVER.PINMUX.VAR.PINMUX32.VALUE="PINMUX_BALL_A13_N2HET1_17 | PINMUX_BALL_J1_N2HET1_18 | PINMUX_BALL_B13_N2HET1_19 | PINMUX_BALL_P2_N2HET1_20" +DRIVER.PINMUX.VAR.PINMUX24.VALUE="PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_E19_MIBSPI5NCS_0" +DRIVER.PINMUX.VAR.PINMUX16.VALUE="PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_R5_ETMDATA_28 | PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_R7_ETMDATA_30" +DRIVER.PINMUX.VAR.SIGNAL56_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL48_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX131_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX33.VALUE="PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_N2HET1_24" +DRIVER.PINMUX.VAR.PINMUX25.VALUE="PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MIBSPI5NENA" +DRIVER.PINMUX.VAR.PINMUX17.VALUE="PINMUX_BALL_R8_ETMDATA_31 | PINMUX_BALL_R9_ETMTRACECLKIN | PINMUX_BALL_R10_ETMTRACECLKOUT | PINMUX_BALL_R11_ETMTRACECTL" +DRIVER.PINMUX.VAR.SIGNAL56_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL48_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX131_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB6_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.EQEP2B_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX34.VALUE="PINMUX_BALL_A14_N2HET1_26 | PINMUX_BALL_K19_N2HET1_28 | PINMUX_BALL_B11_N2HET1_30 | PINMUX_BALL_D8_N2HET2_01" +DRIVER.PINMUX.VAR.PINMUX26.VALUE="PINMUX_BALL_J19_MIBSPI5SIMO_0 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2 | PINMUX_BALL_G17_MIBSPI5SIMO_3" +DRIVER.PINMUX.VAR.PINMUX18.VALUE="PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2" +DRIVER.PINMUX.VAR.MUX131_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX35.VALUE="PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_N2HET2_12 | PINMUX_BALL_D2_N2HET2_13 | PINMUX_BALL_D1_N2HET2_14" +DRIVER.PINMUX.VAR.PINMUX27.VALUE="PINMUX_BALL_J18_MIBSPI5SOMI_0 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3" +DRIVER.PINMUX.VAR.PINMUX19.VALUE="PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6" +DRIVER.PINMUX.VAR.MUX131_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX36.VALUE="PINMUX_BALL_P4_N2HET2_19 | PINMUX_BALL_T5_N2HET2_20 | PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK" +DRIVER.PINMUX.VAR.PINMUX28.VALUE="PINMUX_BALL_K18_N2HET1_00 | PINMUX_BALL_V2_N2HET1_01 | PINMUX_BALL_W5_N2HET1_02 | PINMUX_BALL_U1_N2HET1_03" +DRIVER.PINMUX.VAR.MUX131_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX37.VALUE="PINMUX_BALL_E2_N2HET2_03 | PINMUX_BALL_N3_N2HET2_07" +DRIVER.PINMUX.VAR.PINMUX29.VALUE="PINMUX_BALL_B12_N2HET1_04 | PINMUX_BALL_V6_N2HET1_05 | PINMUX_BALL_W3_N2HET1_06 | PINMUX_BALL_T1_N2HET1_07" +DRIVER.PINMUX.VAR.MUX131_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX123_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX115_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX107_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX80.VALUE=SIGNAL_AD2EVT_T10 +DRIVER.PINMUX.VAR.SIGNAL41_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL33_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL25_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL17_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX100_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.TEMP2_ENABLE.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX81.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL41_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL33_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL25_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL17_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX98_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX90.VALUE="SIGNAL_MII_RX_DV_U6 | SIGNAL_MII_RX_ER_U5 | SIGNAL_MII_RXCLK_T4 | SIGNAL_MII_RXD_0_U4" +DRIVER.PINMUX.VAR.PINMUX82.VALUE=0 +DRIVER.PINMUX.VAR.MUX127_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX119_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX100_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_133_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_125_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_117_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_109_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX91.VALUE="SIGNAL_MII_RXD_1_T3 | SIGNAL_MII_RXD_2_U3 | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_U7" +DRIVER.PINMUX.VAR.PINMUX83.VALUE=SIGNAL_GIOA_0_A5 +DRIVER.PINMUX.VAR.MUX100_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX92.VALUE="SIGNAL_N2HET1_17_A13 | SIGNAL_N2HET1_19_B13 | SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4" +DRIVER.PINMUX.VAR.PINMUX84.VALUE="SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 | SIGNAL_GIOA_4_A6" +DRIVER.PINMUX.VAR.MUX100_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX93.VALUE="SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17" +DRIVER.PINMUX.VAR.PINMUX85.VALUE="SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 | SIGNAL_GIOB_0_M2" +DRIVER.PINMUX.VAR.MUX100_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB0_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA2_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX94.VALUE="SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 | SIGNAL_N2HET2_02_D7 | SIGNAL_N2HET2_03_E2" +DRIVER.PINMUX.VAR.PINMUX86.VALUE="SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_F2 | SIGNAL_GIOB_3_W10 | SIGNAL_GIOB_4_G1" +DRIVER.PINMUX.VAR.MUX91_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX61_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX53_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX45_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX37_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX29_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_110_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_102_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX95.VALUE="SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 | SIGNAL_N2HET2_06_D11 | SIGNAL_N2HET2_07_N3" +DRIVER.PINMUX.VAR.PINMUX87.VALUE="SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 | SIGNAL_MDIO_F4" +DRIVER.PINMUX.VAR.MUX91_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX96.VALUE="SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16" +DRIVER.PINMUX.VAR.PINMUX88.VALUE="SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9" +DRIVER.PINMUX.VAR.SIGNAL10_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX91_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX97.VALUE="SIGNAL_N2HET2_12_D3 | SIGNAL_N2HET2_13_D2 | SIGNAL_N2HET2_14_D1 | SIGNAL_N2HET2_15_K4" +DRIVER.PINMUX.VAR.PINMUX89.VALUE="SIGNAL_MII_COL_W4 | SIGNAL_MII_CRS_V4" +DRIVER.PINMUX.VAR.SIGNAL10_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX91_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX83_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX75_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX67_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX59_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX98.VALUE="SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 | SIGNAL_N2HET2_20_T5 | SIGNAL_N2HET2_22_T7" +DRIVER.PINMUX.VAR.MUX6_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX99.VALUE="SIGNAL_nTZ1_1_N19 | SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3" +DRIVER.PINMUX.VAR.MUX6_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1A_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX6_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.EQEP1I_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM_SOC3A_SELECT.VALUE=ON +DRIVER.PINMUX.VAR.MUX60_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX60_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX52_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX44_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX36_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX28_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.TEMP3_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX120_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX112_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX104_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_94_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_86_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_78_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_3_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM3_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA_DISABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX30_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX22_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX14_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_71_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_63_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_55_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_47_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_39_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL4_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX21_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL4_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX21_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX13_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX95_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX87_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX79_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL61_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL53_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL45_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL37_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL29_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_40_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_32_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_24_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_16_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ECAP3_FILTER.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM7_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.MUX129_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TBCLK_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX129_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL30_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL22_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL14_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX129_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.I2C1.VALUE=0 +DRIVER.PINMUX.VAR.I2C2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL55_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL47_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL39_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX130_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX122_OPTION0.VALUE=0 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+DRIVER.PINMUX.VAR.MUX38_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX70_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX62_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX54_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX46_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX38_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX121_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX113_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX105_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_98_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_7_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX1_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_91_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_83_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_75_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_67_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_59_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL6_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX31_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL6_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX31_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX23_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX15_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX96_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX88_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL49_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_60_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_52_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_44_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_36_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_28_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.GIOB7_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ECAP6_FILTER_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SIGNAL50_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL42_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL34_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL26_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL18_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_21_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_13_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.SPI2.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL49_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX132_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL57_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL49_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.TEMP1_ENABLE_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.SPI4.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.RMII.VALUE=0 +DRIVER.PINMUX.VAR.MUX132_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX0.VALUE="PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_D4_EMIF_ADDR_00 | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06" +DRIVER.PINMUX.VAR.MUX132_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX1.VALUE="PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10" +DRIVER.PINMUX.VAR.MUX132_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.GIOB1_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.GIOA3_DMA_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.ETPWM2_EQEPERR_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.PINMUX2.VALUE="PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14" +DRIVER.PINMUX.VAR.MUX99_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX81_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX73_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX65_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX57_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX49_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL5_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX3.VALUE="PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18" +DRIVER.PINMUX.VAR.MUX99_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM4_EQEPERR12.VALUE=EQEPERR12 +DRIVER.PINMUX.VAR.PINMUX4.VALUE="PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C17_EMIF_ADDR_21" +DRIVER.PINMUX.VAR.SIGNAL50_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL42_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL34_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL26_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.SIGNAL18_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX101_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX5.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL50_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL42_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL34_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL26_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL18_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX99_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX6.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_127_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_119_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_A.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX7.VALUE=0 +DRIVER.PINMUX.VAR.MUX101_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.ALT_ADC_B.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX8.VALUE=PINMUX_BALL_D16_EMIF_BA_1 +DRIVER.PINMUX.VAR.MUX101_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.PINMUX9.VALUE="PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_L17_EMIF_nCS_2" +DRIVER.PINMUX.VAR.MUX101_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX4_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_120_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_112_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.PIN_MUX_104_SELECT.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION3.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_OPTION0.VALUE=1 +DRIVER.PINMUX.VAR.MUX92_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION4.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION0.VALUE=0 +DRIVER.PINMUX.VAR.SIGNAL11_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.MUX92_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX84_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX76_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX68_OPTION5.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION1.VALUE=0 +DRIVER.PINMUX.VAR.ETPWM_TZ1_SELECT.VALUE=OFF +DRIVER.PINMUX.VAR.MUX132_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX124_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX116_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX108_CONFLICT.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION2.VALUE=0 +DRIVER.PINMUX.VAR.MUX7_OPTION3.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_TRDIR_1.VALUE=HET_TO_MAIN_MEM +DRIVER.CRC.VAR.CRC2_CH2_WDTO.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DEBMOD_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ENABUS_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.HTU_CPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.HTU_CONTPAR_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_EC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPBFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_BASE.VALUE=0xFE000000 +DRIVER.CRC.VAR.CRC1_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_FC_1.VALUE=0 +DRIVER.CRC.VAR.HTU_BASE.VALUE=0xFFF7A400 +DRIVER.CRC.VAR.HTU_ICPBL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_BASE.VALUE=0xFB000000 +DRIVER.CRC.VAR.CRC1_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_CPAFULADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_WDTO.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_7_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_BCTO.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_PAR_1.VALUE=0 +DRIVER.CRC.VAR.HTU_CONT_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ENAREQ_1.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_BCTO.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_STADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPA_7_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPAL_3_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_DCP0_MMADD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC2_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ENAINTMAP_1.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_CPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP1_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.HTU_DCP0_HETADD.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPBL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_3_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_CVH.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_RES_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_CVL.VALUE=0 +DRIVER.CRC.VAR.HTU_DCP0_CPATMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC1_CH1_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC1_CH1_PSSIH.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH1_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_PSSIL.VALUE=0 +DRIVER.CRC.VAR.HTU_MP1_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPB_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_CVH.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_4_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC2_CH2_CVL.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH1_PCP.VALUE=0 +DRIVER.CRC.VAR.HTU_CPA_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_CCI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_CFI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_SCP.VALUE=0 +DRIVER.CRC.VAR.HTU_VBHOLD_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_BCTO.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC2_CH2_PCP.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ERRENA_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_1_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC2_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC2_CH2_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC2_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_DTE.VALUE=0 +DRIVER.CRC.VAR.HTU_CPB_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH1_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH2_SCP.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_MODE_VALUE.VALUE=0x0001 +DRIVER.CRC.VAR.CRC2_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC2_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_DTE.VALUE=1 +DRIVER.CRC.VAR.HTU_DCP0_TRDAT_1.VALUE=32BIT +DRIVER.CRC.VAR.HTU_ICPBL_6_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_4_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_ICPB_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC1_CH2_CVH.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_PSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPAL_0_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH2_CVL.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC2_CH1_PSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_CPA_1_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_CPBTMOD_1.VALUE=POST_INCREMENT +DRIVER.CRC.VAR.CRC1_CH2_PSSIH.VALUE=0 +DRIVER.CRC.VAR.HTU_MP0_ACC_1.VALUE=READ_ONLY +DRIVER.CRC.VAR.CRC1_CH2_PSSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPB_5_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH2_URI.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH2_PCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ICPAL_5_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.CRC1_CH1_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH1_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_DCP0_ADMOD_1.VALUE=INCREMENT_16BIT +DRIVER.CRC.VAR.HTU_CPA_6_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.HTU_CPB_2_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_WDTO.VALUE=0 +DRIVER.CRC.VAR.CRC2_CH2_PSIH.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_SCP.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_ENA_1.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH1_TOE.VALUE=0x00000000 +DRIVER.CRC.VAR.CRC1_CH1_MODE.VALUE=FULL_CPU +DRIVER.CRC.VAR.CRC2_CH2_PSIL.VALUE=0 +DRIVER.CRC.VAR.CRC1_CH2_PSA.VALUE=1 +DRIVER.CRC.VAR.CRC1_CH2_ORI.VALUE=0x00000000 +DRIVER.CRC.VAR.HTU_MP0_ENDADD_1.VALUE=0 +DRIVER.CRC.VAR.HTU_ICPBL_2_SEL_1.VALUE=HIGH +DRIVER.CRC.VAR.HTU_ICPA_0_SEL_1.VALUE=ENABLE +DRIVER.CRC.VAR.CRC2_CH1_MODE_VALUE.VALUE=0x0001 +DRIVER.EMAC.VAR.EMAC_PHY_CUSTOM.VALUE=0 +DRIVER.EMAC.VAR.EMAC_ADD1.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD2.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD3.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD4.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD5.VALUE=FF +DRIVER.EMAC.VAR.EMAC_ADD6.VALUE=FF +DRIVER.EMAC.VAR.EMAC_CTRL_BASE.VALUE=0xFCF78800 +DRIVER.EMAC.VAR.EMAC_PHY_DP83640.VALUE=1 +DRIVER.EMAC.VAR.EMAC_LOOPBACK_ENA.VALUE=0 +DRIVER.EMAC.VAR.MDIO_BASE.VALUE=0xFCF78900 +DRIVER.EMAC.VAR.EMAC_BASE.VALUE=0xFCF78000 +DRIVER.EMAC.VAR.EMAC_BASE_PORT.VALUE=0xFFFFFFFF +DRIVER.EMAC.VAR.EMAC_TRANSMIT_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHY_TLK111.VALUE=0 +DRIVER.EMAC.VAR.EMAC_CHANNELNUMBER.VALUE=0 +DRIVER.EMAC.VAR.EMAC_RX_PBUF_ALLOC.VALUE=10 +DRIVER.EMAC.VAR.EMAC_UNICAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_FULL_DUPLEX_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_PHYADDRESS.VALUE=1 +DRIVER.EMAC.VAR.EMAC_MII_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_CTRL_RAM_BASE.VALUE=0xFC520000 +DRIVER.EMAC.VAR.EMAC_BROADCAST_ENA.VALUE=1 +DRIVER.EMAC.VAR.EMAC_RECEIVE_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TA.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ENA_SDRAM.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES.VALUE=0 +DRIVER.EMIF.VAR.EMIF_AVAILABLE.VALUE=1 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_MAX.VALUE=213 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_MAX.VALUE=213 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_ASYNC3_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ENA.VALUE=1 +DRIVER.EMIF.VAR.EMIF_ASYNC1_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_BANKS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_BASE.VALUE=0xFCFFE800 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_MAX.VALUE=427 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_CLKFRQ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_ASYNC2_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC3_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_INIT_TIME.VALUE=200 +DRIVER.EMIF.VAR.EMIF_SDRAM_TREFRESH_DEFAULT.VALUE=1605 +DRIVER.EMIF.VAR.EMIF_ASYNC3_TSU.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_CLK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_ASIZE.VALUE=8_bit +DRIVER.EMIF.VAR.EMIF_SDRAM_TRAS.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_NOR_FLASH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_CAS_LATENCY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY0.VALUE=pin_low +DRIVER.EMIF.VAR.EMIF_SDRAM_TRCD_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_WAIT_POLARITY1.VALUE=pin_high +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRC.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRRD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_DELAY_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC_MAX_EXT_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC1_W_SETUP.VALUE=15 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_CYCLES_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_MS.VALUE=0.001 +DRIVER.EMIF.VAR.EMIF_NS.VALUE=0.000000001 +DRIVER.EMIF.VAR.EMIF_SDRAM_TWR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_EXTENDED_WAIT.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC3_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TAVAV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_MAX.VALUE=107 +DRIVER.EMIF.VAR.EMIF_SDRAM_TXSR.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TEHQZ.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_MAX.VALUE=427 +DRIVER.EMIF.VAR.EMIF_ASYNC2_R_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TELQV.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_STROBE_MODE.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRP_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_REFRESH_PERIOD_MAX.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_SIZE.VALUE=4_words +DRIVER.EMIF.VAR.EMIF_ASYNC2_WAIT.VALUE=pin0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TEHEL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_SDRAM_TRFC_VAL.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_R_HOLD.VALUE=7 +DRIVER.EMIF.VAR.EMIF_SDRAM_PAGE_SIZE.VALUE=elements_256 +DRIVER.EMIF.VAR.EMIF_ASYNC2_TELEH.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC1_PAGE_DELAY.VALUE=0 +DRIVER.EMIF.VAR.EMIF_IBANK.VALUE=0 +DRIVER.EMIF.VAR.EMIF_ASYNC2_W_STROBE.VALUE=63 +DRIVER.EMIF.VAR.EMIF_ASYNC1_TA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_10_ENA.VALUE=0 +DRIVER.POM.VAR.POM_TIMEOUT_ENABLE.VALUE=0 +DRIVER.POM.VAR.POM_REGION_11_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_20_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_12_ENA.VALUE=0 +DRIVER.POM.VAR.POM_NO_OF_REGION.VALUE=1 +DRIVER.POM.VAR.POM_REGION_21_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_13_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_30_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_22_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_14_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_31_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_23_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_15_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_1_ENA.VALUE=1 +DRIVER.POM.VAR.POM_REGION_32_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_24_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_16_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_2_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_25_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_17_ENA.VALUE=0 +DRIVER.POM.VAR.POM_OVRLY_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVLY_TRG_REGION.VALUE=INTERNAL_RAM +DRIVER.POM.VAR.POM_OVRLY_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_3_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_26_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_18_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_4_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_27_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_19_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_5_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_28_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_6_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE10.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE11.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE20.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE12.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_29_ENA.VALUE=0 +DRIVER.POM.VAR.POM_REGION_SIZE21.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE13.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE30.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE22.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE14.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE31.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE23.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE15.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE32.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE24.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE16.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE25.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE17.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE26.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE18.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE27.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE19.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE28.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE29.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_7_ENA.VALUE=0 +DRIVER.POM.VAR.POM_BASE.VALUE=0xFFA04000 +DRIVER.POM.VAR.POM_PROG_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_8_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD19.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE1.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD28.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE2.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_PROG_START_ADD29.VALUE=0x00000000 +DRIVER.POM.VAR.POM_REGION_SIZE3.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE4.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE5.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE6.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE7.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE8.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_SIZE9.VALUE=SIZE_64BYTES +DRIVER.POM.VAR.POM_REGION_9_ENA.VALUE=0 +DRIVER.POM.VAR.POM_PROG_START_ADD1.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD2.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD3.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD4.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD5.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD6.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD7.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD8.VALUE=0x00000000 +DRIVER.POM.VAR.POM_PROG_START_ADD9.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD10.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD11.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD20.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD12.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD21.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD13.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD30.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD22.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD14.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD31.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD23.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD15.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD32.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD24.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD16.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD25.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD17.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD26.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD18.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD27.VALUE=0x00000000 +DRIVER.POM.VAR.POM_OVRLY_START_ADD19.VALUE=0x00000000 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN5_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN3_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_RAM_PWR_DOMAIN1_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN4_ENABLE.VALUE=0 +DRIVER.PMM.VAR.PMM_PWR_DOMAIN2_ENABLE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM7_BASE.VALUE=0xFCF79200 +DRIVER.ETPWM.VAR.ETPWM5_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM1_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM6_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM3_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM2_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM3_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM6_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM1_BASE.VALUE=0xFCF78C00 +DRIVER.ETPWM.VAR.ETPWM6_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM1_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM4_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM3_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_BASE.VALUE=0xFCF78D00 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM7_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM3_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM4_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM2_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM4_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_BASE.VALUE=0xFCF78E00 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM2_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM7_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM7_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_FALLING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM3_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM1_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM3_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM5_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_OST.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_DUTYTIME.VALUE=50.000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_DEADBAND_INVERT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM3_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_BASE.VALUE=0xFCF78F00 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM4_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM2_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM2_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM1_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_TB_ACTUALFREQUENCY.VALUE=80.000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCA.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_ENABLE_SOCB.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM6_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTYTIME_REG.VALUE=3 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SOCB_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_BASE.VALUE=0xFCF79000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM1_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM4_PWMB_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM7_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_CLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_PWMB_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_DEADBAND_OUTPUT.VALUE=PWMA_PWMB_NIL +DRIVER.ETPWM.VAR.ETPWM1_INTERRUPT_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM5_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM4_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM1_OSHT_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM4_OSHT_WIDTH_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_MODE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_DCBEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM2_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM5_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCA.VALUE=DCAEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM1_SELECT_SOCB.VALUE=DCBEVT1 +DRIVER.ETPWM.VAR.ETPWM7_CBC3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_PERIOD_REG.VALUE=1000 +DRIVER.ETPWM.VAR.ETPWM3_CHOPPER_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM2_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_CBC4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM6_CHOPPER_ACTUALPERIOD.VALUE=100.000 +DRIVER.ETPWM.VAR.ETPWM7_CBC5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_CBC6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM5_PWMA_COMPARE.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM1_CHOPPER_PERIOD_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMB_PERIOD_REG.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_FALLING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_RISING_EDGE_DELAY.VALUE=9.091 +DRIVER.ETPWM.VAR.ETPWM6_BASE.VALUE=0xFCF79100 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_DUTYTIME.VALUE=500.000 +DRIVER.ETPWM.VAR.ETPWM6_PWMB_ENA.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM5_OSHT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMB_RISING_EDGE_DELAY_REG.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_DEADBAND_INPUT.VALUE=PWMA_RED_FED +DRIVER.ETPWM.VAR.ETPWM5_PWMB_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT3.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_OSHT4.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM2_SELECT_EVENT.VALUE=NO_EVENT +DRIVER.ETPWM.VAR.ETPWM5_OSHT5.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM5_PWMB_DUTY.VALUE=50 +DRIVER.ETPWM.VAR.ETPWM5_OSHT6.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM7_OSHT_ACTUAL_WIDTH.VALUE=100 +DRIVER.ETPWM.VAR.ETPWM6_CLKDIV.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_PWMA_DEADBAND_OUT.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM7_HSPCLKDIV_REG.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM2_CHOPPER_DUTY_NEW.VALUE=50.0 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_PERIOD.VALUE=1000.000 +DRIVER.ETPWM.VAR.ETPWM2_TB_FREQUENCY.VALUE=110.000 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT1.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM3_PWMA_POLARITY.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM6_SOCA_PERIOD.VALUE=1 +DRIVER.ETPWM.VAR.ETPWM6_DCAEVT2.VALUE=0x0000 +DRIVER.ETPWM.VAR.ETPWM4_FDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_RDELAY_SOURCE.VALUE=0 +DRIVER.ETPWM.VAR.ETPWM1_PWMA_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP5_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP5_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP2_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP6_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP6_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP5_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP1_BASE.VALUE=0xFCF79300 +DRIVER.ECAP.VAR.ECAP4_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP5_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP4_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP2_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP6_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_BASE.VALUE=0xFCF79400 +DRIVER.ECAP.VAR.ECAP2_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP2_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP6_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP5_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP3_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP3_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP3_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP1_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_BASE.VALUE=0xFCF79500 +DRIVER.ECAP.VAR.ECAP5_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP4_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP4_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_BASE.VALUE=0xFCF79600 +DRIVER.ECAP.VAR.ECAP6_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP4_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP3_CEVT4.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP6_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP5_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP4_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PWM_ACTUALPERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP6_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_PWM_COMPARE.VALUE=50 +DRIVER.ECAP.VAR.ECAP2_CAP2_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP3_PWM_DUTYTIME.VALUE=500.000 +DRIVER.ECAP.VAR.ECAP3_CAP4_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP1_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_PWM_PERIOD.VALUE=1000.000 +DRIVER.ECAP.VAR.ECAP5_BASE.VALUE=0xFCF79700 +DRIVER.ECAP.VAR.ECAP3_ENA_PWM.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_WRAP_COUNTER.VALUE=CAPTURE_EVENT1 +DRIVER.ECAP.VAR.ECAP3_CAPTURE_MODE.VALUE=ONE_SHOT +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP1.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP2.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP3.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP1_RESET_COUNTER_CAP4.VALUE=RESET_DISABLE +DRIVER.ECAP.VAR.ECAP5_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_PWM_DUTY.VALUE=50 +DRIVER.ECAP.VAR.ECAP1_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_PRESCALE_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_PRESCALE.VALUE=0 +DRIVER.ECAP.VAR.ECAP2_CNTOVF.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP5_CAP1_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP1_PWM_PERIOD_REG.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_CMP.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP2_ENA_LOAD.VALUE=0 +DRIVER.ECAP.VAR.ECAP3_PRD.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP3_RESET_COUNTER.VALUE=0 +DRIVER.ECAP.VAR.ECAP6_BASE.VALUE=0xFCF79800 +DRIVER.ECAP.VAR.ECAP6_CAP3_POLARITY.VALUE=RISING_EDGE +DRIVER.ECAP.VAR.ECAP4_CEVT1.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT2.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT3.VALUE=0x0000 +DRIVER.ECAP.VAR.ECAP4_CEVT4.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP2_QUPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_BASE.VALUE=0xFCF79900 +DRIVER.EQEP.VAR.EQEP1_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_BASE.VALUE=0xFCF79A00 +DRIVER.EQEP.VAR.EQEP1_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP2_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP1_PCSPW.VALUE=0x000 +DRIVER.EQEP.VAR.EQEP1_POSCMP.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP2_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP1_PCE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPS_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_ENABLE_CAPTURE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP2_PCPOL.VALUE=ACTIVE_HIGH +DRIVER.EQEP.VAR.EQEP2_INV_QEPA_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_CAP_CLK_PRESCALER.VALUE=PS_8 +DRIVER.EQEP.VAR.EQEP2_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_PC_MODE.VALUE=DIRECTION_COUNT +DRIVER.EQEP.VAR.EQEP2_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PCR_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INV_QEPB_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCSPW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_PC_INIT_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.EQEP.VAR.EQEP2_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_IEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_MAXPC_VALUE.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QCLM.VALUE=ON_POSITION_COUNTER_READ +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_STROBE_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP1_STROBE_EVT_SELECT.VALUE=DIRECTON_DEPENDENT +DRIVER.EQEP.VAR.EQEP1_UNIT_POS_PRESCALER.VALUE=PS_512 +DRIVER.EQEP.VAR.EQEP1_WDPRD.VALUE=0x0000 +DRIVER.EQEP.VAR.EQEP1_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_QPE_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PC_RST_MODE.VALUE=MAX_POSITION +DRIVER.EQEP.VAR.EQEP1_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SET_INIT_AT_STARTUP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_UTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWI_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_SEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SEL.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP2_PCU_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCSHDW.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SOEN.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_POSCMP.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QUPRD.VALUE=0x00000000 +DRIVER.EQEP.VAR.EQEP1_IGATE.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_QDC_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_SWAP.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_WDPRD.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_WTO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_POSITIVE_ROTATION.VALUE=CLOCKWISE +DRIVER.EQEP.VAR.EQEP2_INV_QEPI_POL.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCM_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP1_IEL_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_EXT_CLK_RATE.VALUE=RESOLUTION_1x +DRIVER.EQEP.VAR.EQEP2_SPSEL.VALUE=INDEX_PIN +DRIVER.EQEP.VAR.EQEP1_PCO_INT_ENA.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_INDEX_EVT_SELECT.VALUE=RISING_EDGE +DRIVER.EQEP.VAR.EQEP1_INDEX_EVT_INIT_ENABLE.VALUE=0 +DRIVER.EQEP.VAR.EQEP2_PCLOAD.VALUE=QPOSCNT_EQ_QPSCMP +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_NUMBER.VALUE=11 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_END.VALUE=9 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_START_SECTOR.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_3_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_START.VALUE=20 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_START.VALUE=12 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_START.VALUE=8 +DRIVER.FEE.VAR.FEE_VS29_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VS30_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS22_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS14_ENABLE.VALUE=0 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+DRIVER.FEE.VAR.FEE_MAXIMUM_BLOCKING_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_NO_OF_UNCONFIGURED_BLOCKS_TO_COPY.VALUE=0 +DRIVER.FEE.VAR.FEE_FLASH_BANK_NUM.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX5_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_START.VALUE=27 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_END.VALUE=27 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_5_END.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_START.VALUE=1 +DRIVER.FEE.VAR.FEE_SECTOR_OVERHEAD.VALUE=16 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_NUMBER.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_NUMBER.VALUE=25 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_NUMBER.VALUE=17 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_TI_FEE_SW_MINOR_VERSION.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_10_NUMBER.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_NUMBER.VALUE=6 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_END.VALUE=28 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_6_END.VALUE=5 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_11_START.VALUE=10 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_START.VALUE=6 +DRIVER.FEE.VAR.FEE_VS28_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VERSIONINFO_API.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_11_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_DATASETS.VALUE=1 +DRIVER.FEE.VAR.MAX_BLOCK_TIME.VALUE=600 +DRIVER.FEE.VAR.FEE_VS21_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS13_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_WRITE_CYCLES.VALUE=10 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_OFFSET.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_7_END.VALUE=6 +DRIVER.FEE.VAR.FEE_NUMBER_OF_BLOCKS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_BANK.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX14_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX3_ENABLE.VALUE=0 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+DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_NUMBER.VALUE=4 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_DEVERROR_DETECT.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_29_START.VALUE=28 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_END.VALUE=8 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_START.VALUE=2 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_1_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_VS26_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS18_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS11_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS4_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX8_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_MAX_NUMBER_OF_LINKS.VALUE=256 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_EEP.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX12_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX1_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_FLASH_ERROR_CORRECTION_ENABLE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_DATASELECT_BITS.VALUE=0 +DRIVER.FEE.VAR.FEE_OPERATING_FREQ.VALUE=150.000 +DRIVER.FEE.VAR.FEE_TOTAL_SECTORS.VALUE=32 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_16_NUMBER.VALUE=16 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_20_START.VALUE=19 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_12_START.VALUE=11 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_8_START.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_2_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_30_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_22_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_14_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_NUMBER.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_28_NUMBER.VALUE=28 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_21_NUMBER.VALUE=21 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_13_NUMBER.VALUE=13 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_9_NUMBER.VALUE=9 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_9_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_2_NUMBER.VALUE=2 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_33_START.VALUE=32 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_25_START.VALUE=24 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_17_START.VALUE=16 +DRIVER.FEE.VAR.FEE_JOBEND_NOTIFICATION.VALUE=JobEndNotification +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_13_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_12_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_8_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_VS32_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS24_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_VS16_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_ENABLE_ECC.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_OVERHEAD.VALUE=24 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_7_DATASETS.VALUE=1 +DRIVER.FEE.VAR.FEE_VS9_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_4_OFFSET.VALUE=0 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_3_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VS2_ENABLE.VALUE=1 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX6_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_DEVICE_INDEX.VALUE=0x00000000 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_31_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_23_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_15_BANK.VALUE=7 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_10_SIZE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX10_ENABLE.VALUE=0 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_14_NUMBER.VALUE=14 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_4_START.VALUE=3 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_15_IMED_DATA.VALUE=TRUE +DRIVER.FEE.VAR.FEE_CHECK_BANK7_ACCESS.VALUE=STD_OFF +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_WRITE_CYCLES.VALUE=0x8 +DRIVER.FEE.VAR.FEE_POLLING_MODE.VALUE=STD_ON +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_5_NUMBER.VALUE=5 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_26_NUMBER.VALUE=26 +DRIVER.FEE.VAR.FEE_VIRTUAL_SECTOR_18_NUMBER.VALUE=18 +DRIVER.FEE.VAR.FEE_BLOCK_INDEX_6_SIZE.VALUE=0 +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_1.VALUE=0xFFFFFFFF +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_2.VALUE=0xFFFDFFFE +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_WORD_3.VALUE=0xFFEFFFFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_0.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_0.VALUE=0xFF +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_1.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_VISIBLE_KEY_ECC_BYTE_1.VALUE=0xD2 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_2.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN_WORD_3.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_0.VALUE=0xFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_ECC_BYTE_1.VALUE=0xD2 +DRIVER.AJSM.VAR.AJSM_SCAN_PATTERN.VALUE=PATTERN_NOT_REQUIRED +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_0.VALUE=0xEFFDFFFF +DRIVER.AJSM.VAR.AJSM_NEW_KEY_WORD_1.VALUE=0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg new file mode 100644 index 00000000000..b26c9d9f031 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/HalCoGen-RM57L843.hcg @@ -0,0 +1,1041 @@ + + + + RM57Lx + RM57L843ZWT_FREERTOS + FreeRTOS.dil + gcc + + + 04.07.01 + + + + + + + + + + + + + + + + + + + + + + + + + hal_stdtypes.h + include\hal_stdtypes.h + + + sys_common.h + include\sys_common.h + + + reg_system.h + include\reg_system.h + + + reg_flash.h + include\reg_flash.h + + + reg_l2ramw.h + include\reg_l2ramw.h + + + reg_vim.h + include\reg_vim.h + + + reg_pbist.h + include\reg_pbist.h + + + reg_stc.h + include\reg_stc.h + + + reg_efc.h + include\reg_efc.h + + + reg_pcr.h + include\reg_pcr.h + + + reg_pmm.h + include\reg_pmm.h + + + reg_dma.h + include\reg_dma.h + + + reg_ccmr5.h + include\reg_ccmr5.h + + + sys_core.h + include\sys_core.h + + + system.h + include\system.h + + + sys_vim.h + include\sys_vim.h + + + sys_mpu.h + include\sys_mpu.h + + + sys_pmu.h + include\sys_pmu.h + + + sys_pcr.h + include\sys_pcr.h + + + sys_pmm.h + include\sys_pmm.h + + + sys_dma.h + include\sys_dma.h + + + sys_core.s + source\sys_core.s + + + sys_intvecs.s + source\sys_intvecs.s + + + sys_mpu.s + source\sys_mpu.s + + + sys_pmu.s + source\sys_pmu.s + + + sys_pcr.c + source\sys_pcr.c + + + sys_pmm.c + source\sys_pmm.c + + + sys_dma.c + source\sys_dma.c + + + system.c + source\system.c + + + sys_phantom.c + source\sys_phantom.c + + + sys_startup.c + source\sys_startup.c + + + sys_vim.c + source\sys_vim.c + + + sys_main.c + source\sys_main.c + + + notification.c + source\notification.c + + + sys_link.ld + source\sys_link.ld + + + reg_epc.h + include\reg_epc.h + + + reg_nmpu.h + include\reg_nmpu.h + + + reg_scm.h + include\reg_scm.h + + + reg_sdcmmr.h + include\reg_sdcmmr.h + + + epc.h + include\epc.h + + + epc.c + source\epc.c + + + nmpu.h + include\nmpu.h + + + nmpu.c + source\nmpu.c + + + errata.h + include\errata.h + + + errata.c + source\errata.c + + + Test.h + + + errata_SSWF021_45.h + include\errata_SSWF021_45.h + + + errata_SSWF021_45_defs.h + include\errata_SSWF021_45_defs.h + + + errata_SSWF021_45.c + source\errata_SSWF021_45.c + + + os_projdefs.h + + + FreeRTOSConfig.h + + + os_portmacro.h + + + os_mpu_wrappers.h + + + os_portable.h + + + FreeRTOS.h + + + os_list.h + + + os_queue.h + + + os_semphr.h + + + os_croutine.h + + + os_StackMacros.h + + + os_task.h + + + os_timer.h + + + os_port.c + + + os_portasm.s + + + os_tasks.c + + + os_queue.c + + + os_list.c + + + os_croutine.c + + + os_timer.c + + + os_mpu_wrappers.c + + + os_heap.c + + + os_event_groups.c + + + os_event_groups.h + + + reg_pinmux.h + + + pinmux.h + + + pinmux.c + + + reg_gio.h + + + gio.h + + + gio.c + + + reg_esm.h + + + esm.h + + + esm.c + + + reg_sci.h + + + sci.h + + + sci.c + + + reg_lin.h + + + lin.h + + + lin.c + + + reg_mibspi.h + + + mibspi.h + + + mibspi.c + + + reg_spi.h + + + spi.h + + + + reg_can.h + + + can.h + + + can.c + + + reg_adc.h + + + adc.h + + + adc.c + + + + + + + + + std_nhet.h + + + reg_het.h + + + het.h + + + het.c + + + reg_htu.h + + + htu.h + + + + + + + + + reg_i2c.h + + + i2c.h + + + i2c.c + + + emac.h + + + hw_emac.h + + + hw_emac_ctrl.h + + + hw_mdio.h + + + hw_reg_access.h + + + mdio.h + + + emac.c + + + mdio.c + + + phy_dp83640.c + + + phy_dp83640.h + + + phy_tlk111.c + + + phy_tlk111.h + + + emac_phyConfig.h + + + reg_dcc.h + + + dcc.h + + + dcc.c + + + reg_rtp.h + + + rtp.h + + + + reg_dmm.h + + + dmm.h + + + + reg_emif.h + + + emif.h + + + emif.c + + + reg_pom.h + + + pom.h + + + pom.c + + + reg_crc.h + + + crc.h + + + crc.c + + + reg_etpwm.h + + + etpwm.h + + + etpwm.c + + + reg_ecap.h + + + ecap.h + + + ecap.c + + + reg_eqep.h + + + eqep.h + + + eqep.c + + + Device_RM57.h + + + Device_header.h + + + Device_types.h + + + ti_fee_cfg.h + + + MemMap.h + + + ti_fee_types.h + + + ti_fee.h + + + fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + include\os_projdefs.h + + + include\FreeRTOSConfig.h + + + include\os_portmacro.h + + + include\os_mpu_wrappers.h + + + include\os_portable.h + + + include\FreeRTOS.h + + + include\os_list.h + + + include\os_queue.h + + + include\os_semphr.h + + + include\os_croutine.h + + + include\os_StackMacros.h + + + include\os_task.h + + + include\os_timer.h + + + source\os_port.c + + + source\os_portasm.s + + + source\os_tasks.c + + + source\os_queue.c + + + source\os_list.c + + + source\os_croutine.c + + + source\os_timer.c + + + source\os_mpu_wrappers.c + + + source\os_heap.c + + + source\os_event_groups.c + + + include\os_event_groups.h + + + + + + + include\reg_pinmux.h + + + include\pinmux.h + + + source\pinmux.c + + + + + + + include\reg_gio.h + + + include\gio.h + + + source\gio.c + + + + + + + include\reg_esm.h + + + include\esm.h + + + source\esm.c + + + + + + + include\reg_sci.h + + + include\sci.h + + + source\sci.c + + + + + + + include\reg_lin.h + + + include\lin.h + + + source\lin.c + + + + + + + include\reg_mibspi.h + + + include\mibspi.h + + + source\mibspi.c + + + + + + + include\reg_spi.h + + + include\spi.h + + + + + + + + + + include\reg_can.h + + + include\can.h + + + source\can.c + + + + + + + include\reg_adc.h + + + include\adc.h + + + source\adc.c + + + + + + + include\std_nhet.h + + + include\reg_het.h + + + include\het.h + + + source\het.c + + + include\reg_htu.h + + + include\htu.h + + + + + + + include\reg_i2c.h + + + include\i2c.h + + + source\i2c.c + + + + + + + include\emac.h + + + include\hw_emac.h + + + include\hw_emac_ctrl.h + + + include\hw_mdio.h + + + include\hw_reg_access.h + + + include\mdio.h + + + source\emac.c + + + source\mdio.c + + + source\phy_dp83640.c + + + include\phy_dp83640.h + + + source\phy_tlk111.c + + + include\phy_tlk111.h + + + include\emac_phyConfig.h + + + + + + + include\reg_dcc.h + + + include\dcc.h + + + source\dcc.c + + + + + + + include\reg_rtp.h + + + include\rtp.h + + + + + + + + + + include\reg_dmm.h + + + include\dmm.h + + + + + + + + + + include\reg_emif.h + + + include\emif.h + + + source\emif.c + + + + + + + include\reg_pom.h + + + include\pom.h + + + source\pom.c + + + + + + + include\reg_crc.h + + + include\crc.h + + + source\crc.c + + + + + + + include\reg_etpwm.h + + + include\etpwm.h + + + source\etpwm.c + + + + + + + include\reg_ecap.h + + + include\ecap.h + + + source\ecap.c + + + + + + + include\reg_eqep.h + + + include\eqep.h + + + source\eqep.c + + + + + + + include\Device_RM57.h + + + include\Device_header.h + + + include\Device_types.h + + + include\ti_fee_cfg.h + + + include\MemMap.h + + + include\ti_fee_types.h + + + include\ti_fee.h + + + include\fee_interface.h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml new file mode 100644 index 00000000000..b8ddc17d97a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/RM57L8xx.ccxml @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h new file mode 100644 index 00000000000..b8d0e928377 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_RM57.h @@ -0,0 +1,114 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_RM57.c + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the number of sectors. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_RM57_H + #define DEVICE_RM57_H + + /** @def DEVICE_CONFIGURATION_VERSION + * @brief Device Configuration Version + * + * @note Indicates the current version of the device files + */ + #define DEVICE_CONFIGURATION_VERSION \ + 0U /* Indicates the current version of the device files */ + + /** @def DEVICE_NUMBER_OF_FLASH_BANKS + * @brief Number of Flash Banks + * + * @note Defines the number of Flash Banks on the device + */ + #define DEVICE_NUMBER_OF_FLASH_BANKS \ + 1U /* Defines the number of Flash Banks on the device */ + + /** @def DEVICE_BANK_MAX_NUMBER_OF_SECTORS + * @brief Maximum number of Sectors + * + * @note Defines the maxium number of sectors in all banks + */ + #define DEVICE_BANK_MAX_NUMBER_OF_SECTORS \ + 32U /* Defines the maxium number of sectors in all banks */ + + /** @def DEVICE_BANK1_NUMBER_OF_SECTORS + * @brief Number of Sectors + * + * @note Defines the number of sectors in bank1 + */ + #define DEVICE_BANK1_NUMBER_OF_SECTORS \ + 32U /* Defines the number of sectors in bank1 */ + + /** @def DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS + * @brief Number of Sectors + * + * @note Defines the number of Read Cycle Thresholds + */ + #define DEVICE_NUMBER_OF_READ_CYCLE_THRESHOLDS \ + 4U /* Defines the number of Read Cycle Thresholds */ + + /* Include Files */ + #ifndef _PLATFORM_TYPES_H_ + #define _PLATFORM_TYPES_H_ + #endif + #ifndef _L2FMC + #define _L2FMC + #endif + #include "F021.h" + #include "hal_stdtypes.h" + #include "Device_types.h" + +#endif /* DEVICE_RM57_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h new file mode 100644 index 00000000000..99b1e37ae0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_header.h @@ -0,0 +1,65 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_header.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file includes the header file. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef TI_FEE_DEVICEHEADER_H +#define TI_FEE_DEVICEHEADER_H + +/* Uncomment the appropriate include file depending on the device you are using */ +#include "Device_RM57.h" + +/* End of file */ +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h new file mode 100644 index 00000000000..96add2784e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/Device_types.h @@ -0,0 +1,133 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: Device_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file defines the structures. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 01.15.00 06Jun2014 Vishwanath Reddy Initial Version. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/********************************************************************************************************************* + * INCLUDES + *********************************************************************************************************************/ + +#ifndef DEVICE_TYPES_H + #define DEVICE_TYPES_H + + #include "hal_stdtypes.h" + +/* Enum to describe the type of error handling on the device */ +typedef enum +{ + Device_ErrorHandlingNone, /* Device has no error handling */ + Device_ErrorHandlingParity, /* Device has parity error handling */ + Device_ErrorHandlingEcc /* Device has ECC error handling */ +} Device_FlashErrorCorrectionProcessType; + +/* Enum to describe the ARM core on the device*/ +typedef enum +{ + Device_CoreNone, /* To indicate that the device has a single core */ + Device_Arm7, /* To indicate that the device has a ARM7 core */ + Device_CortexR4, /* To indicate that the device has a CortexR4 core */ + Device_CortexM3 /* To indicate that the device has a CortexM3 core */ +} Device_ArmCoreType; + +/* Structure defines an individual sector within a bank */ +typedef struct +{ + Fapi_FlashSectorType Device_Sector; /* Sector number */ + uint32 Device_SectorStartAddress; /* Starting address of the sector */ + uint32 Device_SectorLength; /* Length of the sector */ + uint32 Device_MaxWriteCycles; /* Number of cycles the sector is rated for */ + uint32 Device_EccAddress; + uint32 Device_EccLength; +} Device_SectorType; + +/* Structure defines an individual bank */ +typedef struct +{ + Fapi_FmcRegistersType * Device_ControlRegister; + Fapi_FlashBankType Device_Core; /* Core number for this bank */ + Device_SectorType Device_SectorInfo[ DEVICE_BANK_MAX_NUMBER_OF_SECTORS ]; /* Array of + the + Sectors + within a + bank */ +} Device_BankType; + +/* Structure defines the Flash structure of the device */ +typedef struct +{ + uint8 Device_DeviceName[ 12 ]; /* Device name */ + uint32 Device_EngineeringId; /* Device Engineering ID */ + Device_FlashErrorCorrectionProcessType + Device_FlashErrorHandlingProcessInfo; /* Indicates + which + type + of bit + Error + handling + is on + the + device + */ + Device_ArmCoreType Device_MasterCore; /* Indicates the Master core type on the device + */ + boolean Device_SupportsInterrupts; /* Indicates if the device supports Flash + interrupts for processing Flash */ + uint32 Device_NominalWriteTime; /* Nominal time for one write command operation in uS + */ + uint32 Device_MaximumWriteTime; /* Maximum time for one write command operation in uS + */ + Device_BankType Device_BankInfo[ DEVICE_NUMBER_OF_FLASH_BANKS ]; /* Array of Banks on + the device */ +} Device_FlashType; + +#endif /* DEVICE_TYPES_H */ + +/* End of File */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h new file mode 100644 index 00000000000..8781cbf7be2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/MemMap.h @@ -0,0 +1,39 @@ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MEM_MAP_H__ +#define __MEM_MAP_H__ + +#endif /* __MEM_MAP_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h new file mode 100644 index 00000000000..b9d8118372d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/adc.h @@ -0,0 +1,344 @@ +/** @file adc.h + * @brief ADC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +#include "reg_adc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ADC General Definitions */ + +/** @def adcGROUP0 + * @brief Alias name for ADC event group + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP0 0U + +/** @def adcGROUP1 + * @brief Alias name for ADC group 1 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP1 1U + +/** @def adcGROUP2 + * @brief Alias name for ADC group 2 + * + * @note This value should be used for API argument @a group + */ +#define adcGROUP2 2U + +/** @def ADC_12_BIT_MODE + * @brief Alias name for ADC 12-bit mode of operation + */ +#define ADC_12_BIT_MODE 0x80000000U + +/** @enum adcResolution + * @brief Alias names for data resolution + * This enumeration is used to provide alias names for the data resolution: + * - 12 bit resolution + * - 10 bit resolution + * - 8 bit resolution + */ + +enum adcResolution +{ + ADC_12_BIT = 0x00000000U, /**< Alias for 12 bit data resolution */ + ADC_10_BIT = 0x00000100U, /**< Alias for 10 bit data resolution */ + ADC_8_BIT = 0x00000200U /**< Alias for 8 bit data resolution */ +}; + +/** @enum adcFiFoStatus + * @brief Alias names for FiFo status + * This enumeration is used to provide alias names for the current FiFo states: + * - FiFo is not full + * - FiFo is full + * - FiFo overflow occurred + */ + +enum adcFiFoStatus +{ + ADC_FIFO_IS_NOT_FULL = 0U, /**< Alias for FiFo is not full */ + ADC_FIFO_IS_FULL = 1U, /**< Alias for FiFo is full */ + ADC_FIFO_OVERFLOW = 3U /**< Alias for FiFo overflow occurred */ +}; + +/** @enum adcConversionStatus + * @brief Alias names for conversion status + * This enumeration is used to provide alias names for the current conversion states: + * - Conversion is not finished + * - Conversion is finished + */ + +enum adcConversionStatus +{ + ADC_CONVERSION_IS_NOT_FINISHED = 0U, /**< Alias for current conversion is not finished + */ + ADC_CONVERSION_IS_FINISHED = 8U /**< Alias for current conversion is finished */ +}; + +/** @enum adc1HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc1HwTriggerSource +{ + ADC1_EVENT = 0U, /**< Alias for event pin */ + ADC1_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC1_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC1_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC1_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC1_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC1_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC1_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + + ADC1_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC1_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC1_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC1_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC1_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC1_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC1_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC1_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC1_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC1_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC1_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/** @enum adc2HwTriggerSource + * @brief Alias names for hardware trigger source + * This enumeration is used to provide alias names for the hardware trigger sources: + */ + +enum adc2HwTriggerSource +{ + ADC2_EVENT = 0U, /**< Alias for event pin */ + ADC2_HET1_8 = 1U, /**< Alias for HET1 pin 8 */ + ADC2_HET1_10 = 2U, /**< Alias for HET1 pin 10 */ + ADC2_RTI_COMP0 = 3U, /**< Alias for RTI compare 0 match */ + ADC2_HET1_12 = 4U, /**< Alias for HET1 pin 12 */ + ADC2_HET1_14 = 5U, /**< Alias for HET1 pin 14 */ + ADC2_GIOB0 = 6U, /**< Alias for GIO port b pin 0 */ + ADC2_GIOB1 = 7U, /**< Alias for GIO port b pin 1 */ + ADC2_HET2_5 = 1U, /**< Alias for HET2 pin 5 */ + ADC2_HET1_27 = 2U, /**< Alias for HET1 pin 27 */ + ADC2_HET1_17 = 4U, /**< Alias for HET1 pin 17 */ + ADC2_HET1_19 = 5U, /**< Alias for HET1 pin 19 */ + ADC2_HET1_11 = 6U, /**< Alias for HET1 pin 11 */ + ADC2_HET2_13 = 7U, /**< Alias for HET2 pin 13 */ + + ADC2_EPWM_B = 1U, /**< Alias for B Signal EPWM */ + ADC2_EPWM_A1 = 3U, /**< Alias for A1 Signal EPWM */ + ADC2_HET2_1 = 5U, /**< Alias for HET2 pin 1 */ + ADC2_EPWM_A2 = 6U, /**< Alias for A2 Signal EPWM */ + ADC2_EPWM_AB = 7U /**< Alias for AB Signal EPWM */ +}; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct adcData + * @brief ADC Conversion data structure + * + * This type is used to pass adc conversion data. + */ +/** @typedef adcData_t + * @brief ADC Data Type Definition + */ +typedef struct adcData +{ + uint32 id; /**< Channel/Pin Id */ + uint16 value; /**< Conversion data value */ +} adcData_t; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +typedef struct adc_config_reg +{ + uint32 CONFIG_OPMODECR; + uint32 CONFIG_CLOCKCR; + uint32 CONFIG_GxMODECR[ 3U ]; + uint32 CONFIG_G0SRC; + uint32 CONFIG_G1SRC; + uint32 CONFIG_G2SRC; + uint32 CONFIG_BNDCR; + uint32 CONFIG_BNDEND; + uint32 CONFIG_G0SAMP; + uint32 CONFIG_G1SAMP; + uint32 CONFIG_G2SAMP; + uint32 CONFIG_G0SAMPDISEN; + uint32 CONFIG_G1SAMPDISEN; + uint32 CONFIG_G2SAMPDISEN; + uint32 CONFIG_PARCR; +} adc_config_reg_t; + +#define ADC1_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC1_CLOCKCR_CONFIGVALUE ( 7U ) + +#define ADC1_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC1_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC1_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC1_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) +#define ADC1_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT ) + +#define ADC1_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC1_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC1_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC1_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC1_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC1_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC1_PARCR_CONFIGVALUE ( 0x00000005U ) + +#define ADC2_OPMODECR_CONFIGVALUE 0x81140001U +#define ADC2_CLOCKCR_CONFIGVALUE ( 7U ) + +#define ADC2_G0MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) +#define ADC2_G1MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) +#define ADC2_G2MODECR_CONFIGVALUE \ + ( ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define ADC2_G0SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G1SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) +#define ADC2_G2SRC_CONFIGVALUE ( ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT ) + +#define ADC2_BNDCR_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ) ) +#define ADC2_BNDEND_CONFIGVALUE ( 2U ) + +#define ADC2_G0SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G1SAMP_CONFIGVALUE ( 1U ) +#define ADC2_G2SAMP_CONFIGVALUE ( 1U ) + +#define ADC2_G0SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G1SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) +#define ADC2_G2SAMPDISEN_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0U << 8U ) | 0x00000000U ) + +#define ADC2_PARCR_CONFIGVALUE ( 0x00000005U ) + +/** + * @defgroup ADC ADC + * @brief Analog To Digital Converter Module. + * + * The microcontroller includes two 12-bit ADC modules with selectable 10-bit or 12-bit + *resolution + * + * Related Files + * - reg_adc.h + * - adc.h + * - adc.c + * @addtogroup ADC + * @{ + */ + +/* ADC Interface Functions */ + +void adcInit( void ); +void adcStartConversion( adcBASE_t * adc, uint32 group ); +void adcStopConversion( adcBASE_t * adc, uint32 group ); +void adcResetFiFo( adcBASE_t * adc, uint32 group ); +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ); +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ); +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ); +void adcEnableNotification( adcBASE_t * adc, uint32 group ); +void adcDisableNotification( adcBASE_t * adc, uint32 group ); +void adcCalibration( adcBASE_t * adc ); +uint32 adcMidPointCalibration( adcBASE_t * adc ); +void adcSetEVTPin( adcBASE_t * adc, uint32 value ); +uint32 adcGetEVTPin( adcBASE_t * adc ); + +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void adcNotification(adcBASE_t *adc, uint32 group) + * @brief Group notification + * @param[in] adc Pointer to ADC node: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group number of ADC node: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * @note This function has to be provide by the user. + */ +void adcNotification( adcBASE_t * adc, uint32 group ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h new file mode 100644 index 00000000000..d1c122e6712 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/can.h @@ -0,0 +1,926 @@ +/** @file can.h + * @brief CAN Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CAN_H__ +#define __CAN_H__ + +#include "reg_can.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CAN General Definitions */ + +/** @def canLEVEL_ACTIVE + * @brief Alias name for CAN error operation level active (Error counter 0-95) + */ +#define canLEVEL_ACTIVE 0x00U + +/** @def canLEVEL_WARNING + * @brief Alias name for CAN error operation level warning (Error counter 96-127) + */ +#define canLEVEL_WARNING 0x40U + +/** @def canLEVEL_PASSIVE + * @brief Alias name for CAN error operation level passive (Error counter 128-255) + */ +#define canLEVEL_PASSIVE 0x20U + +/** @def canLEVEL_BUS_OFF + * @brief Alias name for CAN error operation level bus off (Error counter 256) + */ +#define canLEVEL_BUS_OFF 0x80U + +/** @def canLEVEL_PARITY_ERR + * @brief Alias name for CAN Parity error (Error counter 256-511) + */ +#define canLEVEL_PARITY_ERR 0x100U + +/** @def canLEVEL_TxOK + * @brief Alias name for CAN Sucessful Transmission + */ +#define canLEVEL_TxOK 0x08U + +/** @def canLEVEL_RxOK + * @brief Alias name for CAN Sucessful Reception + */ +#define canLEVEL_RxOK 0x10U + +/** @def canLEVEL_WakeUpPnd + * @brief Alias name for CAN Initiated a WakeUp to system + */ +#define canLEVEL_WakeUpPnd 0x200U + +/** @def canLEVEL_PDA + * @brief Alias name for CAN entered low power mode successfully. + */ +#define canLEVEL_PDA 0x400U + +/** @def canERROR_NO + * @brief Alias name for no CAN error occurred + */ +#define canERROR_OK 0U + +/** @def canERROR_STUFF + * @brief Alias name for CAN stuff error an RX message + */ +#define canERROR_STUFF 1U + +/** @def canERROR_FORMAT + * @brief Alias name for CAN form/format error an RX message + */ +#define canERROR_FORMAT 2U + +/** @def canERROR_ACKNOWLEDGE + * @brief Alias name for CAN TX message wasn't acknowledged + */ +#define canERROR_ACKNOWLEDGE 3U + +/** @def canERROR_BIT1 + * @brief Alias name for CAN TX message sending recessive level but monitoring dominant + */ +#define canERROR_BIT1 4U + +/** @def canERROR_BIT0 + * @brief Alias name for CAN TX message sending dominant level but monitoring recessive + */ +#define canERROR_BIT0 5U + +/** @def canERROR_CRC + * @brief Alias name for CAN RX message received wrong CRC + */ +#define canERROR_CRC 6U + +/** @def canERROR_NO + * @brief Alias name for CAN no message has send or received since last call of + * CANGetLastError + */ +#define canERROR_NO 7U + +/** @def canMESSAGE_BOX1 + * @brief Alias name for CAN message box 1 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX1 1U + +/** @def canMESSAGE_BOX2 + * @brief Alias name for CAN message box 2 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX2 2U + +/** @def canMESSAGE_BOX3 + * @brief Alias name for CAN message box 3 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX3 3U + +/** @def canMESSAGE_BOX4 + * @brief Alias name for CAN message box 4 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX4 4U + +/** @def canMESSAGE_BOX5 + * @brief Alias name for CAN message box 5 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX5 5U + +/** @def canMESSAGE_BOX6 + * @brief Alias name for CAN message box 6 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX6 6U + +/** @def canMESSAGE_BOX7 + * @brief Alias name for CAN message box 7 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX7 7U + +/** @def canMESSAGE_BOX8 + * @brief Alias name for CAN message box 8 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX8 8U + +/** @def canMESSAGE_BOX9 + * @brief Alias name for CAN message box 9 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX9 9U + +/** @def canMESSAGE_BOX10 + * @brief Alias name for CAN message box 10 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX10 10U + +/** @def canMESSAGE_BOX11 + * @brief Alias name for CAN message box 11 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX11 11U + +/** @def canMESSAGE_BOX12 + * @brief Alias name for CAN message box 12 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX12 12U + +/** @def canMESSAGE_BOX13 + * @brief Alias name for CAN message box 13 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX13 13U + +/** @def canMESSAGE_BOX14 + * @brief Alias name for CAN message box 14 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX14 14U + +/** @def canMESSAGE_BOX15 + * @brief Alias name for CAN message box 15 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX15 15U + +/** @def canMESSAGE_BOX16 + * @brief Alias name for CAN message box 16 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX16 16U + +/** @def canMESSAGE_BOX17 + * @brief Alias name for CAN message box 17 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX17 17U + +/** @def canMESSAGE_BOX18 + * @brief Alias name for CAN message box 18 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX18 18U + +/** @def canMESSAGE_BOX19 + * @brief Alias name for CAN message box 19 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX19 19U + +/** @def canMESSAGE_BOX20 + * @brief Alias name for CAN message box 20 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX20 20U + +/** @def canMESSAGE_BOX21 + * @brief Alias name for CAN message box 21 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX21 21U + +/** @def canMESSAGE_BOX22 + * @brief Alias name for CAN message box 22 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX22 22U + +/** @def canMESSAGE_BOX23 + * @brief Alias name for CAN message box 23 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX23 23U + +/** @def canMESSAGE_BOX24 + * @brief Alias name for CAN message box 24 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX24 24U + +/** @def canMESSAGE_BOX25 + * @brief Alias name for CAN message box 25 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX25 25U + +/** @def canMESSAGE_BOX26 + * @brief Alias name for CAN message box 26 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX26 26U + +/** @def canMESSAGE_BOX27 + * @brief Alias name for CAN message box 27 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX27 27U + +/** @def canMESSAGE_BOX28 + * @brief Alias name for CAN message box 28 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX28 28U + +/** @def canMESSAGE_BOX29 + * @brief Alias name for CAN message box 29 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX29 29U + +/** @def canMESSAGE_BOX30 + * @brief Alias name for CAN message box 30 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX30 30U + +/** @def canMESSAGE_BOX31 + * @brief Alias name for CAN message box 31 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX31 31U + +/** @def canMESSAGE_BOX32 + * @brief Alias name for CAN message box 32 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX32 32U + +/** @def canMESSAGE_BOX33 + * @brief Alias name for CAN message box 33 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX33 33U + +/** @def canMESSAGE_BOX34 + * @brief Alias name for CAN message box 34 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX34 34U + +/** @def canMESSAGE_BOX35 + * @brief Alias name for CAN message box 35 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX35 35U + +/** @def canMESSAGE_BOX36 + * @brief Alias name for CAN message box 36 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX36 36U + +/** @def canMESSAGE_BOX37 + * @brief Alias name for CAN message box 37 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX37 37U + +/** @def canMESSAGE_BOX38 + * @brief Alias name for CAN message box 38 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX38 38U + +/** @def canMESSAGE_BOX39 + * @brief Alias name for CAN message box 39 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX39 39U + +/** @def canMESSAGE_BOX40 + * @brief Alias name for CAN message box 40 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX40 40U + +/** @def canMESSAGE_BOX41 + * @brief Alias name for CAN message box 41 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX41 41U + +/** @def canMESSAGE_BOX42 + * @brief Alias name for CAN message box 42 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX42 42U + +/** @def canMESSAGE_BOX43 + * @brief Alias name for CAN message box 43 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX43 43U + +/** @def canMESSAGE_BOX44 + * @brief Alias name for CAN message box 44 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX44 44U + +/** @def canMESSAGE_BOX45 + * @brief Alias name for CAN message box 45 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX45 45U + +/** @def canMESSAGE_BOX46 + * @brief Alias name for CAN message box 46 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX46 46U + +/** @def canMESSAGE_BOX47 + * @brief Alias name for CAN message box 47 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX47 47U + +/** @def canMESSAGE_BOX48 + * @brief Alias name for CAN message box 48 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX48 48U + +/** @def canMESSAGE_BOX49 + * @brief Alias name for CAN message box 49 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX49 49U + +/** @def canMESSAGE_BOX50 + * @brief Alias name for CAN message box 50 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX50 50U + +/** @def canMESSAGE_BOX51 + * @brief Alias name for CAN message box 51 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX51 51U + +/** @def canMESSAGE_BOX52 + * @brief Alias name for CAN message box 52 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX52 52U + +/** @def canMESSAGE_BOX53 + * @brief Alias name for CAN message box 53 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX53 53U + +/** @def canMESSAGE_BOX54 + * @brief Alias name for CAN message box 54 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX54 54U + +/** @def canMESSAGE_BOX55 + * @brief Alias name for CAN message box 55 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX55 55U + +/** @def canMESSAGE_BOX56 + * @brief Alias name for CAN message box 56 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX56 56U + +/** @def canMESSAGE_BOX57 + * @brief Alias name for CAN message box 57 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX57 57U + +/** @def canMESSAGE_BOX58 + * @brief Alias name for CAN message box 58 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX58 58U + +/** @def canMESSAGE_BOX59 + * @brief Alias name for CAN message box 59 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX59 59U + +/** @def canMESSAGE_BOX60 + * @brief Alias name for CAN message box 60 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX60 60U + +/** @def canMESSAGE_BOX61 + * @brief Alias name for CAN message box 61 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX61 61U + +/** @def canMESSAGE_BOX62 + * @brief Alias name for CAN message box 62 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX62 62U + +/** @def canMESSAGE_BOX63 + * @brief Alias name for CAN message box 63 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX63 63U + +/** @def canMESSAGE_BOX64 + * @brief Alias name for CAN message box 64 + * + * @note This value should be used for API argument @a messageBox + */ +#define canMESSAGE_BOX64 64U + +/** @enum canloopBackType + * @brief canLoopback type definition + */ +/** @typedef canloopBackType_t + * @brief canLoopback type Type Definition + * + * This type is used to select the can module Loopback type Digital or Analog loopback. + */ +typedef enum canloopBackType +{ + Internal_Lbk = 0x00000010U, + External_Lbk = 0x00000100U, + Internal_Silent_Lbk = 0x00000018U +} canloopBackType_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct can_config_reg +{ + uint32 CONFIG_CTL; + uint32 CONFIG_ES; + uint32 CONFIG_BTR; + uint32 CONFIG_TEST; + uint32 CONFIG_ABOTR; + uint32 CONFIG_INTMUX0; + uint32 CONFIG_INTMUX1; + uint32 CONFIG_INTMUX2; + uint32 CONFIG_INTMUX3; + uint32 CONFIG_TIOC; + uint32 CONFIG_RIOC; +} can_config_reg_t; + +/* Configuration registers initial value for CAN1*/ +#define CAN1_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN1_ES_CONFIGVALUE 0x00000007U +#define CAN1_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN1_TEST_CONFIGVALUE 0x00000080U +#define CAN1_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN1_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN1_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN1_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN1_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN1_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN2*/ +#define CAN2_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN2_ES_CONFIGVALUE 0x00000007U +#define CAN2_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN2_TEST_CONFIGVALUE 0x00000080U +#define CAN2_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN2_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN2_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN2_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN2_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN2_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN3*/ +#define CAN3_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN3_ES_CONFIGVALUE 0x00000007U +#define CAN3_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN3_TEST_CONFIGVALUE 0x00000080U +#define CAN3_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN3_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN3_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN3_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN3_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN3_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/* Configuration registers initial value for CAN4*/ +#define CAN4_CTL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020002U ) +#define CAN4_ES_CONFIGVALUE 0x00000007U +#define CAN4_BTR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) \ + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U ) +#define CAN4_TEST_CONFIGVALUE 0x00000080U +#define CAN4_ABOTR_CONFIGVALUE ( ( uint32 ) ( 0U ) ) +#define CAN4_INTMUX0_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN4_INTMUX1_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define CAN4_INTMUX2_CONFIGVALUE 0x00000000U +#define CAN4_INTMUX3_CONFIGVALUE 0x00000000U +#define CAN4_TIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) +#define CAN4_RIOC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) ) + +/** + * @defgroup CAN CAN + * @brief Controller Area Network Module. + * + * The Controller Area Network is a high-integrity, serial, multi-master communication + * protocol for distributed real-time applications. This CAN module is implemented + * according to ISO 11898-1 and is suitable for industrial, automotive and general + * embedded communications + * + * Related Files + * - reg_can.h + * - can.h + * - can.c + * @addtogroup CAN + * @{ + */ + +/* CAN Interface Functions */ + +void canInit( void ); +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ); +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ); +uint32 canGetID( canBASE_t * node, uint32 messageBox ); +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ); +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ); +uint32 canFillMessageObjectData( canBASE_t * node, + uint32 messageBox, + const uint8 * data ); +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ); +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ); +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ); +uint32 canGetLastError( canBASE_t * node ); +uint32 canGetErrorLevel( canBASE_t * node ); +void canEnableErrorNotification( canBASE_t * node ); +void canDisableErrorNotification( canBASE_t * node ); +void canEnableStatusChangeNotification( canBASE_t * node ); +void canDisableStatusChangeNotification( canBASE_t * node ); +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ); +void canDisableloopback( canBASE_t * node ); +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ); +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ); +uint32 canIoTxGetBit( canBASE_t * node ); +uint32 canIoRxGetBit( canBASE_t * node ); +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ); +/** @fn void canErrorNotification(canBASE_t *node, uint32 notification) + * @brief Error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Error notification code: + * - canLEVEL_PASSIVE (0x20) : When RX- or TX error counter are between 32 + * and 63 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * - canLEVEL_PARITY_ERR (0x100): When RX- or TX error counter are above 256 + * + * @note This function has to be provide by the user. + */ +void canErrorNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canStatusChangeNotification(canBASE_t *node, uint32 notification) + * @brief Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] notification Status change notification code: + * - canLEVEL_TxOK (0x08) : When sucessful transmission + * - canLEVEL_RxOK (0x10) : When sucessful reception + * - canLEVEL_WakeUpPnd (0x200): When sucessful WakeUp to system initiated + * - canLEVEL_PDA (0x400): When sucessful low power mode entrance + * + * @note This function has to be provide by the user. + */ +void canStatusChangeNotification( canBASE_t * node, uint32 notification ); + +/** @fn void canMessageNotification(canBASE_t *node, uint32 messageBox) + * @brief Message notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * + * @note This function has to be provide by the user. + */ +void canMessageNotification( canBASE_t * node, uint32 messageBox ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h new file mode 100644 index 00000000000..28291143d45 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/crc.h @@ -0,0 +1,344 @@ +/** @file crc.h + * @brief CRC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __CRC_H__ +#define __CRC_H__ + +#include "reg_crc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* CRC General Definitions */ + +/** @def CRCLEVEL_ACTIVE + * @brief Alias name for CRC error operation level active + */ +#define CRCLEVEL_ACTIVE 0x00U + +/** @def CRC_AUTO + * @brief Alias name for CRC auto mode + */ +#define CRC_AUTO 0x00000001U + +/** @def CRC_SEMI_CPU + * @brief Alias name for semi cpu mode setting + */ +#define CRC_SEMI_CPU 0x00000002U + +/** @def CRC_FULL_CPU + * @brief Alias name for CRC cpu full mode + */ +#define CRC_FULL_CPU 0x00000003U + +/** @def CRC_CH4_TO + * @brief Alias name for channel4 time out interrupt flag + */ +#define CRC_CH4_TO 0x10000000U + +/** @def CRC_CH4_UR + * @brief Alias name for channel4 underrun interrupt flag + */ +#define CRC_CH4_UR 0x08000000U + +/** @def CRC_CH4_OR + * @brief Alias name for channel4 overrun interrupt flag + */ +#define CRC_CH4_OR 0x04000000U + +/** @def CRC_CH4_FAIL + * @brief Alias name for channel4 crc fail interrupt flag + */ +#define CRC_CH4_FAIL 0x02000000U + +/** @def CRC_CH4_CC + * @brief Alias name for channel4 compression complete interrupt flag + */ +#define CRC_CH4_CC 0x01000000U + +/** @def CRC_CH3_TO + * @brief Alias name for channel3 time out interrupt flag + */ +#define CRC_CH3_TO 0x00100000U + +/** @def CRC_CH3_UR + * @brief Alias name for channel3 underrun interrupt flag + */ +#define CRC_CH3_UR 0x00080000U + +/** @def CRC_CH3_OR + * @brief Alias name for channel3 overrun interrupt flag + */ +#define CRC_CH3_OR 0x00040000U + +/** @def CRC_CH3_FAIL + * @brief Alias name for channel3 crc fail interrupt flag + */ +#define CRC_CH3_FAIL 0x00020000U + +/** @def CRC_CH3_CC + * @brief Alias name for channel3 compression complete interrupt flag + */ +#define CRC_CH3_CC 0x00010000U + +/** @def CRC_CH2_TO + * @brief Alias name for channel2 time out interrupt flag + */ +#define CRC_CH2_TO 0x00001000U + +/** @def CRC_CH2_UR + * @brief Alias name for channel2 underrun interrupt flag + */ +#define CRC_CH2_UR 0x00000800U + +/** @def CRC_CH2_OR + * @brief Alias name for channel2 overrun interrupt flag + */ +#define CRC_CH2_OR 0x00000400U + +/** @def CRC_CH2_FAIL + * @brief Alias name for channel2 crc fail interrupt flag + */ +#define CRC_CH2_FAIL 0x00000200U + +/** @def CRC_CH2_CC + * @brief Alias name for channel2 compression complete interrupt flag + */ +#define CRC_CH2_CC 0x00000100U + +/** @def CRC_CH1_TO + * @brief Alias name for channel1 time out interrupt flag + */ +#define CRC_CH1_TO 0x00000010U + +/** @def CRC_CH1_UR + * @brief Alias name for channel1 underrun interrupt flag + */ +#define CRC_CH1_UR 0x00000008U + +/** @def CRC_CH1_OR + * @brief Alias name for channel1 overrun interrupt flag + */ +#define CRC_CH1_OR 0x00000004U + +/** @def CRC_CH1_FAIL + * @brief Alias name for channel1 crc fail interrupt flag + */ +#define CRC_CH1_FAIL 0x00000002U + +/** @def CRC_CH1_CC + * @brief Alias name for channel1 compression complete interrupt flag + */ +#define CRC_CH1_CC 0x00000001U + +/** @def CRC_CH1 + * @brief Alias name for channel1 + */ +#define CRC_CH1 0x00000000U + +/** @def CRC_CH1 + * @brief Alias name for channel2 + */ +#define CRC_CH2 0x00000001U + +/** @def CRC_CH3 + * @brief Alias name for channel3 + */ +#define CRC_CH3 0x00000002U + +/** @def CRC_CH4 + * @brief Alias name for channel4 + */ +#define CRC_CH4 0x00000003U + +/** @struct crcModConfig + * @brief CRC mode specific parameters + * + * This type is used to pass crc mode specific parameters + */ +/** @typedef crcModConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcModConfig +{ + uint32 mode; /**< Mode of operation */ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint64 * src_data_pat; /**< Pattern data */ + uint32 data_length; /**< Pattern data length.Number of 64 bit size word*/ +} crcModConfig_t; + +/** @struct crcConfig + * @brief CRC configuration for different modes + * + * This type is used to pass crc configuration + */ +/** @typedef crcConfig_t + * @brief CRC Data Type Definition + */ +typedef struct crcConfig +{ + uint32 crc_channel; /**< CRC channel-0,1 */ + uint32 mode; /**< Mode of operation */ + uint32 pcount; /**< Pattern count*/ + uint32 scount; /**< Sector count */ + uint32 wdg_preload; /**< Watchdog period */ + uint32 block_preload; /**< Block period*/ + +} crcConfig_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +typedef struct crc_config_reg +{ + uint32 CONFIG_CTRL0; + uint32 CONFIG_CTRL1; + uint32 CONFIG_CTRL2; + uint32 CONFIG_INTS; + uint32 CONFIG_PCOUNT_REG1; + uint32 CONFIG_SCOUNT_REG1; + uint32 CONFIG_WDTOPLD1; + uint32 CONFIG_BCTOPLD1; + uint32 CONFIG_PCOUNT_REG2; + uint32 CONFIG_SCOUNT_REG2; + uint32 CONFIG_WDTOPLD2; + uint32 CONFIG_BCTOPLD2; +} crc_config_reg_t; + +#define CRC1_CTRL0_CONFIGVALUE 0x00000000U +#define CRC1_CTRL1_CONFIGVALUE 0x00000000U +#define CRC1_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC1_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC1_PCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_SCOUNT_REG1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_WDTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_BCTOPLD1_CONFIGVALUE ( 0x00000000U ) +#define CRC1_PCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_SCOUNT_REG2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_WDTOPLD2_CONFIGVALUE ( 0x00000000U ) +#define CRC1_BCTOPLD2_CONFIGVALUE ( 0x00000000U ) + +#define CRC2_CTRL0_CONFIGVALUE 0x00000000U +#define CRC2_CTRL1_CONFIGVALUE 0x00000000U +#define CRC2_CTRL2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( CRC_FULL_CPU ) \ + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ) ) +#define CRC2_INTS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) +#define CRC2_PCOUNT_REG1_CONFIGVALUE ( 0U ) +#define CRC2_SCOUNT_REG1_CONFIGVALUE ( 0U ) +#define CRC2_WDTOPLD1_CONFIGVALUE ( 0U ) +#define CRC2_BCTOPLD1_CONFIGVALUE ( 0U ) +#define CRC2_PCOUNT_REG2_CONFIGVALUE ( 0U ) +#define CRC2_SCOUNT_REG2_CONFIGVALUE ( 0U ) +#define CRC2_WDTOPLD2_CONFIGVALUE ( 0U ) +#define CRC2_BCTOPLD2_CONFIGVALUE ( 0U ) + +/** + * @defgroup CRC CRC + * @brief Cyclic Redundancy Check Controller Module. + * + * The CRC controller is a module that is used to perform CRC (Cyclic Redundancy Check) + * to verify the integrity of memory system. A signature representing the contents of the + * memory is obtained when the contents of the memory are read into CRC controller. The + * responsibility of CRC controller is to calculate the signature for a set of data and + * then compare the calculated signature value against a pre-determined good signature + * value. CRC controller supports two channels to perform CRC calculation on multiple + * memories in parallel and can be used on any memory system. + * + * Related Files + * - reg_crc.h + * - crc.h + * - crc.c + * @addtogroup CRC + * @{ + */ + +/* CRC Interface Functions */ +void crcInit( void ); +void crcSendPowerDown( crcBASE_t * crc ); +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ); +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ); +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ); +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ); +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ); +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ); +void crcChannelReset( crcBASE_t * crc, uint32 channel ); +void crcEnableNotification( crcBASE_t * crc, uint32 flags ); +void crcDisableNotification( crcBASE_t * crc, uint32 flags ); +void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); +void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void crcNotification(crcBASE_t *crc, uint32 flags) + * @brief Interrupt callback + * @param[in] crc - crc module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void crcNotification( crcBASE_t * crc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h new file mode 100644 index 00000000000..d53db2648be --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dcc.h @@ -0,0 +1,353 @@ +/** @file dcc.h + * @brief DCC Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DCC_H__ +#define __DCC_H__ + +#include "reg_dcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DCC General Definitions */ + +/** @def dcc1CNT0_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 0 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_HFLPO 0x00000005U + +/** @def dcc1CNT0_CLKSRC_TCK + * @brief Alias name for DCC1 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc1CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc1CNT1_CLKSRC_PLL1 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL1 + * + * This is an alias name for the Clock Source PLL for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U + +/** @def dcc1CNT1_CLKSRC_PLL2 + * @brief Alias name for DCC1 Counter 1 Clock Source PLL2 + * + * This is an alias name for the Clock Source OSCIN for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U + +/** @def dcc1CNT1_CLKSRC_LFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source LFLPO + * + * This is an alias name for the Clock Source LFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_LFLPO 0x0000A002U + +/** @def dcc1CNT1_CLKSRC_HFLPO + * @brief Alias name for DCC1 Counter 1 Clock Source HFLPO + * + * This is an alias name for the Clock Source HFLPO for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_HFLPO 0x0000A003U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN1 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN1 + * + * This is an alias name for the Clock Source EXTCLKIN1 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN1 0x0000A005U + +/** @def dcc1CNT1_CLKSRC_EXTCLKIN2 + * @brief Alias name for DCC1 Counter 1 Clock Source EXTCLKIN2 + * + * This is an alias name for the Clock Source EXTCLKIN2 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_EXTCLKIN2 0x0000A006U + +/** @def dcc1CNT1_CLKSRC_VCLK + * @brief Alias name for DCC1 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc1CNT1_CLKSRC_N2HET1_31 + * @brief Alias name for DCC1 Counter 1 Clock Source N2HET1_31 + * + * This is an alias name for the Clock Source N2HET1_31 for DCC1 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc1CNT1_CLKSRC_N2HET1_31 0x0000500FU + +/** @def dcc2CNT0_CLKSRC_TCK + * @brief Alias name for DCC2 Counter 0 Clock Source TCK + * + * This is an alias name for the Clock Source TCK for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_TCK 0x0000000AU + +/** @def dcc1CNT0_CLKSRC_OSCIN + * @brief Alias name for DCC1 Counter 0 Clock Source OSCIN + * + * This is an alias name for the Clock Source OSCIN for DCC2 Counter 0. + * + * @note This value should be used for API argument @a cnt0_Clock_Source + */ +#define dcc2CNT0_CLKSRC_OSCIN 0x0000000FU + +/** @def dcc2CNT1_CLKSRC_VCLK + * @brief Alias name for DCC2 Counter 1 Clock Source VCLK + * + * This is an alias name for the Clock Source VCLK for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_VCLK 0x0000A008U + +/** @def dcc2CNT1_CLKSRC_ODCLK8 + * @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/8 + * + * This is an alias name for the Clock Source PLL2_post_ODCLK/8 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_ODCLK8 0x0000A001U + +/** @def dcc2CNT1_CLKSRC_ODCLK16 + * @brief Alias name for DCC2 Counter 1 Clock Source PLL2_post_ODCLK/16 + * + * This is an alias name for the Clock Source PLL2_post_ODCLK/16 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_ODCLK16 0x0000A002U + +/** @def dcc2CNT1_CLKSRC_N2HET1_0 + * @brief Alias name for DCC2 Counter 1 Clock Source N2HET2_0 + * + * This is an alias name for the Clock Source N2HET2_0 for DCC2 Counter 1. + * + * @note This value should be used for API argument @a cnt1_Clock_Source + */ +#define dcc2CNT1_CLKSRC_N2HET1_0 0x0000500FU + +/** @def dccNOTIFICATION_DONE + * @brief Alias name for DCC Done notification + * + * This is an alias name for the DCC Done notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_DONE 0x0000A000U + +/** @def dccNOTIFICATION_ERROR + * @brief Alias name for DCC Error notification + * + * This is an alias name for the DCC Error notification. + * + * @note This value should be used for API argument @a notification + */ +#define dccNOTIFICATION_ERROR 0x000000A0U + +/** @enum dcc1clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc1clocksource +{ + DCC1_CNT0_HF_LPO = 0x5U, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC1_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 1*/ + DCC1_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC1_CNT1_PLL1 = 0x0U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 0*/ + DCC1_CNT1_PLL2 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC1_CNT1_LF_LPO = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC1_CNT1_HF_LPO = 0x3U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 3*/ + DCC1_CNT1_EXTCLKIN1 = 0x5U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 4*/ + DCC1_CNT1_EXTCLKIN2 = 0x6U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 6*/ + DCC1_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC1_CNT1_N2HET1_31 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/** @enum dcc2clocksource + * @brief Alias names for dcc clock sources + * + * This enumeration is used to provide alias names for the clock sources: + */ +enum dcc2clocksource +{ + DCC2_CNT0_OSCIN = 0xFU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 0*/ + DCC2_CNT0_TCK = 0xAU, /**< Alias for DCC1 CNT 0 CLOCK SOURCE 2*/ + + DCC2_CNT1_VCLK = 0x8U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 8*/ + DCC2_CNT1_ODCLK8 = 0x1U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 1*/ + DCC2_CNT1_ODCLK16 = 0x2U, /**< Alias for DCC1 CNT 1 CLOCK SOURCE 2*/ + DCC2_CNT1_N2HET2_0 = 0xAU /**< Alias for DCC1 CNT 1 CLOCK SOURCE 9*/ +}; + +/* Configuration registers */ +typedef struct dcc_config_reg +{ + uint32 CONFIG_GCTRL; + uint32 CONFIG_CNT0SEED; + uint32 CONFIG_VALID0SEED; + uint32 CONFIG_CNT1SEED; + uint32 CONFIG_CNT1CLKSRC; + uint32 CONFIG_CNT0CLKSRC; +} dcc_config_reg_t; + +/* Configuration registers initial value */ +#define DCC1_GCTRL_CONFIGVALUE \ + ( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) ) +#define DCC1_CNT0SEED_CONFIGVALUE 39204U +#define DCC1_VALID0SEED_CONFIGVALUE 792U +#define DCC1_CNT1SEED_CONFIGVALUE 742500U +#define DCC1_CNT1CLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 10U << 12U ) | ( uint32 ) DCC1_CNT1_PLL1 ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define DCC1_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC1_CNT0_OSCIN ) + +#define DCC2_GCTRL_CONFIGVALUE \ + ( ( uint32 ) 0xAU | ( uint32 ) ( ( uint32 ) 0xAU << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | ( uint32 ) ( ( uint32 ) 0xAU << 12U ) ) +#define DCC2_CNT0SEED_CONFIGVALUE 0U +#define DCC2_VALID0SEED_CONFIGVALUE 0U +#define DCC2_CNT1SEED_CONFIGVALUE 0U +#define DCC2_CNT1CLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | ( uint32 ) DCC2_CNT1_VCLK ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define DCC2_CNT0CLKSRC_CONFIGVALUE ( ( uint32 ) DCC2_CNT0_OSCIN ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** + * @defgroup DCC DCC + * @brief Dual-Clock Comparator Module + * + * The primary purpose of a DCC module is to measure the frequency of a clock signal + * using a second known clock signal as a reference. This capability can be used to ensure + * the correct frequency range for several different device clock sources, thereby + * enhancing the system safety metrics. + * + * Related Files + * - reg_dcc.h + * - dcc.h + * - dcc .c + * @addtogroup DCC + * @{ + */ + +/* DCC Interface Functions */ +void dccInit( void ); +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ); +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ); +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ); +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ); +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ); +void dccEnable( dccBASE_t * dcc ); +void dccDisable( dccBASE_t * dcc ); +uint32 dccGetErrStatus( dccBASE_t * dcc ); + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ); +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ); +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ); +/** @fn void dccNotification(dccBASE_t *dcc,uint32 flags) + * @brief Interrupt callback + * @param[in] dcc - dcc module base address + * @param[in] flags - status flags + * + * This is a callback function provided by the application. It is call when + * a dcc is complete or detected error. + */ +void dccNotification( dccBASE_t * dcc, uint32 flags ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h new file mode 100644 index 00000000000..306c304460f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/dmm.h @@ -0,0 +1,164 @@ +/** @file dmm.h + * @brief DMM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __DMM_H__ +#define __DMM_H__ + +#include "reg_dmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct dmm_config_reg +{ + uint32 CONFIG_PC0; + uint32 CONFIG_PC1; + uint32 CONFIG_PC3; + uint32 CONFIG_PC6; + uint32 CONFIG_PC7; + uint32 CONFIG_PC8; +} dmm_config_reg_t; + +#define DMM_PC3_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC1_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +#define DMM_PC6_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC8_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +#define DMM_PC7_CONFIGVALUE \ + ( ( uint32 ) 0U | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) ) + +#define DMM_PC0_CONFIGVALUE \ + ( ( uint32 ) 1U | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 6U ) | ( uint32 ) ( ( uint32 ) 1U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 12U ) | ( uint32 ) ( ( uint32 ) 1U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 14U ) | ( uint32 ) ( ( uint32 ) 1U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) ) + +/** + * @defgroup DMM DMM + * @brief Data Modification Module. + * + * The DMM module provides the capability to modify data in the entire 4 GB address space + *of the device from an external peripheral, with minimal interruption of the application. + * + * Related Files + * - reg_dmm.h + * - dmm.h + * - dmm.c + * @addtogroup DMM + * @{ + */ +/* DMM Interface Functions */ + +void dmmInit( void ); +void dmmGetConfigValue( dmm_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h new file mode 100644 index 00000000000..8400703d3e1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ecap.h @@ -0,0 +1,347 @@ +/** @file ecap.h + * @brief ECAP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#include "reg_ecap.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @brief Enumeration to define the capture (CAP) interrupts + */ +typedef enum +{ + ecapInt_CTR_CMP = 0x0080U, /*< Denotes CTR = CMP interrupt */ + ecapInt_CTR_PRD = 0x0040U, /*< Denotes CTR = PRD interrupt */ + ecapInt_CTR_OVF = 0x0020U, /*< Denotes CTROVF interrupt */ + ecapInt_CEVT4 = 0x0010U, /*< Denotes CEVT4 interrupt */ + ecapInt_CEVT3 = 0x0008U, /*< Denotes CEVT3 interrupt */ + ecapInt_CEVT2 = 0x0004U, /*< Denotes CEVT2 interrupt */ + ecapInt_CEVT1 = 0x0002U, /*< Denotes CEVT1 interrupt */ + ecapInt_Global = 0x0001U, /*< Denotes Capture global interrupt */ + ecapInt_All = 0x00FFU /*< Denotes All interrupts */ +} ecapInterrupt_t; + +/** @brief Enumeration to define the capture (CAP) prescaler values + */ +typedef enum +{ + ecapPrescale_By_1 = ( ( uint16 ) 0U << 9U ), /*< Divide by 1 */ + ecapPrescale_By_2 = ( ( uint16 ) 1U << 9U ), /*< Divide by 2 */ + ecapPrescale_By_4 = ( ( uint16 ) 2U << 9U ), /*< Divide by 4 */ + ecapPrescale_By_6 = ( ( uint16 ) 3U << 9U ), /*< Divide by 6 */ + ecapPrescale_By_8 = ( ( uint16 ) 4U << 9U ), /*< Divide by 8 */ + ecapPrescale_By_10 = ( ( uint16 ) 5U << 9U ), /*< Divide by 10 */ + ecapPrescale_By_12 = ( ( uint16 ) 6U << 9U ), /*< Divide by 12 */ + ecapPrescale_By_14 = ( ( uint16 ) 7U << 9U ), /*< Divide by 14 */ + ecapPrescale_By_16 = ( ( uint16 ) 8U << 9U ), /*< Divide by 16 */ + ecapPrescale_By_18 = ( ( uint16 ) 9U << 9U ), /*< Divide by 18 */ + ecapPrescale_By_20 = ( ( uint16 ) 10U << 9U ), /*< Divide by 20 */ + ecapPrescale_By_22 = ( ( uint16 ) 11U << 9U ), /*< Divide by 22 */ + ecapPrescale_By_24 = ( ( uint16 ) 12U << 9U ), /*< Divide by 24 */ + ecapPrescale_By_26 = ( ( uint16 ) 13U << 9U ), /*< Divide by 26 */ + ecapPrescale_By_28 = ( ( uint16 ) 14U << 9U ), /*< Divide by 28 */ + ecapPrescale_By_30 = ( ( uint16 ) 15U << 9U ), /*< Divide by 30 */ + ecapPrescale_By_32 = ( ( uint16 ) 16U << 9U ), /*< Divide by 32 */ + ecapPrescale_By_34 = ( ( uint16 ) 17U << 9U ), /*< Divide by 34 */ + ecapPrescale_By_36 = ( ( uint16 ) 18U << 9U ), /*< Divide by 36 */ + ecapPrescale_By_38 = ( ( uint16 ) 19U << 9U ), /*< Divide by 38 */ + ecapPrescale_By_40 = ( ( uint16 ) 20U << 9U ), /*< Divide by 40 */ + ecapPrescale_By_42 = ( ( uint16 ) 21U << 9U ), /*< Divide by 42 */ + ecapPrescale_By_44 = ( ( uint16 ) 22U << 9U ), /*< Divide by 44 */ + ecapPrescale_By_46 = ( ( uint16 ) 23U << 9U ), /*< Divide by 46 */ + ecapPrescale_By_48 = ( ( uint16 ) 24U << 9U ), /*< Divide by 48 */ + ecapPrescale_By_50 = ( ( uint16 ) 25U << 9U ), /*< Divide by 50 */ + ecapPrescale_By_52 = ( ( uint16 ) 26U << 9U ), /*< Divide by 52 */ + ecapPrescale_By_54 = ( ( uint16 ) 27U << 9U ), /*< Divide by 54 */ + ecapPrescale_By_56 = ( ( uint16 ) 28U << 9U ), /*< Divide by 56 */ + ecapPrescale_By_58 = ( ( uint16 ) 29U << 9U ), /*< Divide by 58 */ + ecapPrescale_By_60 = ( ( uint16 ) 30U << 9U ), /*< Divide by 60 */ + ecapPrescale_By_62 = ( ( uint16 ) 31U << 9U ) /*< Divide by 62 */ +} ecapPrescale_t; + +/** @brief Enumeration to define the Sync Out options + */ +typedef enum +{ + SyncOut_SyncIn = ( ( uint16 ) 0U << 6U ), /*< Sync In used for Sync Out */ + SyncOut_CTRPRD = ( ( uint16 ) 1U << 6U ), /*< CTR = PRD used for Sync Out */ + SyncOut_None = ( ( uint16 ) 2U << 6U ) /*< Disables Sync Out */ +} ecapSyncOut_t; + +/** @brief Enumeration to define the Polarity + */ +typedef enum +{ + RISING_EDGE = 0U, + FALLING_EDGE = 1U +} ecapEdgePolarity_t; + +typedef enum +{ + ACTIVE_HIGH = 0U, + ACTIVE_LOW = 1U +} ecapAPWMPolarity_t; + +/** @brief Enumeration to define the Mode of operation + */ +typedef enum +{ + CONTINUOUS = 0U, + ONE_SHOT = 1U +} ecapMode_t; + +/** @brief Enumeration to define the capture events + */ +typedef enum +{ + CAPTURE_EVENT1 = 0U, + CAPTURE_EVENT2 = 1U, + CAPTURE_EVENT3 = 2U, + CAPTURE_EVENT4 = 3U +} ecapEvent_t; + +typedef enum +{ + RESET_ENABLE = 1U, + RESET_DISABLE = 0U +} ecapReset_t; + +typedef struct ecap_config_reg +{ + uint32 CONFIG_CTRPHS; + uint16 CONFIG_ECCTL1; + uint16 CONFIG_ECCTL2; + uint16 CONFIG_ECEINT; +} ecap_config_reg_t; + +#define ECAP1_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP1_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP1_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP1_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP2_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP2_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP2_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP2_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP3_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP3_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP3_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP3_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP4_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP4_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP4_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP4_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP5_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP5_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP5_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP5_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) + +#define ECAP6_CTRPHS_CONFIGVALUE 0x00000000U +#define ECAP6_ECCTL1_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) \ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) \ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) | ( uint16 ) ( ( uint16 ) 0U << 9U ) ) +#define ECAP6_ECCTL2_CONFIGVALUE \ + ( ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) \ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) \ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) | ( uint16 ) 0x00000010U ) +#define ECAP6_ECEINT_CONFIGVALUE \ + ( 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U | 0x0000U ) +/** + * @defgroup eCAP eCAP + * @brief Enhanced Capture Module. + * + * The enhanced Capture (eCAP) module is essential in systems where accurate timing of + *external events is important. This microcontroller implements 6 instances of the eCAP + *module. + * + * Related Files + * - reg_ecap.h + * - ecap.h + * - ecap.c + * @addtogroup eCAP + * @{ + */ +void ecapInit( void ); +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ); +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ); +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ); +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ); +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ); +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ); +void ecapEnableCapture( ecapBASE_t * ecap ); +void ecapDisableCapture( ecapBASE_t * ecap ); +void ecapStartCounter( ecapBASE_t * ecap ); +void ecapStopCounter( ecapBASE_t * ecap ); +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ); +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ); +void ecapDisableAPWMMode( ecapBASE_t * ecap ); +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ); +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ); +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ); +uint32 ecapGetCAP1( ecapBASE_t * ecap ); +uint32 ecapGetCAP2( ecapBASE_t * ecap ); +uint32 ecapGetCAP3( ecapBASE_t * ecap ); +uint32 ecapGetCAP4( ecapBASE_t * ecap ); +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ); + +/** @brief Interrupt callback + * @param[in] ecap Handle to CAP object + * @param[in] flags Copy of interrupt flags + */ +void ecapNotification( ecapBASE_t * ecap, uint16 flags ); + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /*end of _CAP_H_ definition */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h new file mode 100644 index 00000000000..11b377794cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac.h @@ -0,0 +1,438 @@ +/** + * \file emac.h + * + * \brief EMAC APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __EMAC_H__ +#define __EMAC_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "hw_reg_access.h" +#include "hw_emac.h" +#include "hw_emac_ctrl.h" +#include "mdio.h" +#include "emac_phyConfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/*****************************************************************************/ +/* +** Macros which can be used as speed parameter to the API EMACRMIISpeedSet +*/ +#define EMAC_RMIISPEED_10MBPS ( 0x00000000U ) +#define EMAC_RMIISPEED_100MBPS ( 0x00008000U ) + +/* Macros for enabling taken as inputs from HALCoGen GUI. */ +#define EMAC_TX_ENABLE ( 1U ) +#define EMAC_RX_ENABLE ( 1U ) +#define EMAC_MII_ENABLE ( 1U ) +#define EMAC_FULL_DUPLEX_ENABLE ( 1U ) +#define EMAC_LOOPBACK_ENABLE ( 0U ) +#define EMAC_BROADCAST_ENABLE ( 1U ) +#define EMAC_UNICAST_ENABLE ( 1U ) +#define EMAC_CHANNELNUMBER ( 0U ) +#define EMAC_PHYADDRESS ( 1U ) + +/* + * Macros to indicate EMAC Channel Numbers + */ +#define EMAC_CHANNEL_0 ( 0x00000000U ) +#define EMAC_CHANNEL_1 ( 0x00000001U ) +#define EMAC_CHANNEL_2 ( 0x00000002U ) +#define EMAC_CHANNEL_3 ( 0x00000003U ) +#define EMAC_CHANNEL_4 ( 0x00000004U ) +#define EMAC_CHANNEL_5 ( 0x00000005U ) +#define EMAC_CHANNEL_6 ( 0x00000006U ) +#define EMAC_CHANNEL_7 ( 0x00000007U ) +/* Macros which can be used as duplexMode parameter to the API +** EMACDuplexSet +*/ +#define EMAC_DUPLEX_FULL ( 0x00000001U ) +#define EMAC_DUPLEX_HALF ( 0x00000000U ) + +/* +** Macros which can be used as matchFilt parameters to the API +** EMACMACAddrSet +*/ +/* Address not used to match/filter incoming packets */ +#define EMAC_MACADDR_NO_MATCH_NO_FILTER ( 0x00000000U ) + +/* Address will be used to filter incoming packets */ +#define EMAC_MACADDR_FILTER ( 0x00100000U ) + +/* Address will be used to match incoming packets */ +#define EMAC_MACADDR_MATCH ( 0x00180000U ) + +/* +** Macros which can be passed as eoiFlag to EMACRxIntAckToClear API +*/ +#define EMAC_INT_CORE0_RX ( 0x1U ) +#define EMAC_INT_CORE1_RX ( 0x5U ) +#define EMAC_INT_CORE2_RX ( 0x9U ) + +/* +** Macros which can be passed as eoiFlag to EMACTxIntAckToClear API +*/ +#define EMAC_INT_CORE0_TX ( 0x2U ) +#define EMAC_INT_CORE1_TX ( 0x6U ) +#define EMAC_INT_CORE2_TX ( 0xAU ) +/* Base Addresses */ +#define EMAC_CTRL_RAM_0_BASE 0xFC520000U +#define EMAC_0_BASE 0xFCF78000U +#define EMAC_CTRL_0_BASE 0xFCF78800U +#define MDIO_0_BASE 0xFCF78900U + +/*MAC address length*/ +#define EMAC_HWADDR_LEN 6U +#define MAX_EMAC_INSTANCE 1U +#define SIZE_EMAC_CTRL_RAM 0x2000U +#define MAX_TRANSFER_UNIT 1514U +#define MAX_RX_PBUF_ALLOC ( 10U ) +#define MIN_PKT_LEN 60U +#define MIN_PACKET_SIZE ( 46U ) + +#define EMAC_BUF_DESC_OWNER 0x20000000U +#define EMAC_BUF_DESC_SOP 0x80000000U +#define EMAC_BUF_DESC_EOP 0x40000000U +#define EMAC_BUF_DESC_EOQ 0x10000000U + +#define EMAC_NETSTATREGS( n ) ( ( uint32 ) 0x200U + ( uint32 ) ( ( n ) * 4U ) ) + +/* Error Signalling Macros */ +#define EMAC_ERR_CONNECT 0x2U /* Not connected. */ +#define EMAC_ERR_OK 0x1U /* No error, everything OK. */ + +/* Macros for Configuration Value Registers */ +#define EMAC_TXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_RXCONTROL_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_TXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKSET_CONFIGVALUE 0x00000001U +#define EMAC_RXINTMASKCLEAR_CONFIGVALUE 0x00000001U +#define EMAC_MACSRCADDRHI_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 24U ) | ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MACSRCADDRLO_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0xFFU << 8U ) | ( uint32 ) ( ( uint32 ) 0xFFU ) ) +#define EMAC_MDIOCONTROL_CONFIGVALUE 0x4114001FU +#define EMAC_C0RXEN_CONFIGVALUE 0x00000001U +#define EMAC_C0TXEN_CONFIGVALUE 0x00000001U + +/* Structure to store pending status from the Tx Interrupt Status Registers. */ +typedef struct emac_tx_int_status +{ + volatile uint32 intstatmasked; /* Pending interrupt status read from the Transmit + Interrupt Status (Masked) Register (TXINTSTATMASKED) + */ + volatile uint32 intstatraw; /* Pending interrupt status read from the Transmit + Interrupt Status (Unmasked) Register (TXINTSTATRAW) */ +} emac_tx_int_status_t; + +/* Structure to store pending status from the Rx Interrupt Status Registers. */ +typedef struct emac_rx_int_status +{ + volatile uint32 intstatmasked_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatmasked_threshpend; /* Reads RXnTRHESHPEND value from the + Receive Interrupt Status (Unmasked) + Register (RXINTSTATRAW) */ + + volatile uint32 intstatraw_pend; /* Reads RXnPEND value from the Receive Interrupt + Status (Unmasked) Register (RXINTSTATRAW) */ + volatile uint32 intstatraw_threshpend; /* Reads RXnTRHESHPEND value from the Receive + Interrupt Status (Unmasked) Register + (RXINTSTATRAW) */ + +} emac_rx_int_status_t; + +/* EMAC TX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure.*/ +typedef struct emac_tx_bd +{ + volatile struct emac_tx_bd * next; + volatile uint32 bufptr; /* Pointer to the actual Buffer storing the data to be + transmitted. */ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each) */ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_tx_bd_t; + +/* EMAC RX Buffer descriptor data structure - Refer TRM for details about the buffer + * descriptor structure. */ +typedef struct emac_rx_bd +{ + volatile struct emac_rx_bd * next; /*Used as a pointer for next element in the linked + list of descriptors.*/ + volatile uint32 bufptr; /*Pointer to the actual Buffer which will store the received + data.*/ + volatile uint32 bufoff_len; /*Buffer Offset and Buffer Length (16 bits each)*/ + volatile uint32 flags_pktlen; /*Status flags and Packet Length. (16 bits each)*/ +} emac_rx_bd_t; + +/** + * Helper struct to hold the data used to operate on a particular + * receive channel + */ +typedef struct rxch_struct +{ + volatile emac_rx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can receive new data.*/ + volatile emac_rx_bd_t * active_head; /*Used to point to the active descriptor in the + chain which is receiving.*/ + volatile emac_rx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ +} rxch_t; + +/** + * Helper struct to hold the data used to operate on a particular + * transmit channel + */ +typedef struct txch_struct +{ + volatile emac_tx_bd_t * free_head; /*Used to point to the free buffer descriptor which + can transmit new data.*/ + volatile emac_tx_bd_t * active_tail; /*Used to point to the last descriptor in the + chain.*/ + volatile emac_tx_bd_t * next_bd_to_process; /*Used to point to the next descriptor in + the chain to be processed.*/ +} txch_t; +/** + * Helper struct to hold private data used to operate the ethernet interface. + */ +typedef struct hdkif_struct +{ + /* MAC Address of the Module. */ + uint8_t mac_addr[ 6 ]; + + /* emac base address */ + uint32 emac_base; + + /* emac controller base address */ + volatile uint32 emac_ctrl_base; + volatile uint32 emac_ctrl_ram; + + /* mdio base address */ + volatile uint32 mdio_base; + + /* phy parameters for this instance - for future use */ + uint32 phy_addr; + boolean ( *phy_autoneg )( uint32 param1, uint32 param2, uint16 param3 ); + boolean ( *phy_partnerability )( uint32 param4, uint32 param5, uint16 * param6 ); + + /* The tx/rx channels for the interface */ + txch_t txchptr; + rxch_t rxchptr; +} hdkif_t; + +/*Ethernet Frame Structure */ +typedef struct ethernet_frame +{ + uint8 dest_addr[ 6 ]; /* Destination MAC Address */ + uint8 src_addr[ 6 ]; /*Source MAC Address. */ + uint16 frame_length; /* Data Frame Length */ + uint8 data[ 1500 ]; /* Data */ +} ethernet_frame_t; + +/* Struct used to take packet data input from the user for transmit APIs. */ +typedef struct pbuf_struct +{ + /** next pbuf in singly linked pbuf chain */ + struct pbuf_struct * next; + + /** + * Pointer to the actual ethernet packet/packet fragment to be transmitted. + * The packet needs to be in the following format: + * |Destination MAC Address (6 bytes)| Source MAC Address (6 bytes)| Length/Type (2 + *bytes)| Data (46- 1500 bytes) The data can be split up over multiple pbufs which are + *linked as a linked list. + **/ + uint8 * payload; + + /** + * total length of this buffer and all next buffers in chain + * belonging to the same packet. + * + * For non-queue packet chains this is the invariant: + * p->tot_len == p->len + (p->next? p->next->tot_len: 0) + */ + uint16 tot_len; + + /** length of this buffer */ + uint16 len; + +} pbuf_t; + +/* Structure to hold the values of the EMAC Configuration Registers. */ +typedef struct emac_config_reg_struct +{ + /* EMAC Module Register Values */ + uint32 TXCONTROL; /* Transmit Control Register. */ + uint32 RXCONTROL; /* Receive Control Register */ + uint32 TXINTMASKSET; /* Transmit Interrupt Mask Set Register */ + uint32 TXINTMASKCLEAR; /* Transmit Interrupt Clear Register */ + uint32 RXINTMASKSET; /* Receive Interrupt Mask Set Register */ + uint32 RXINTMASKCLEAR; /*Receive Interrupt Mask Clear Register*/ + uint32 MACSRCADDRHI; /*MAC Source Address High Bytes Register*/ + uint32 MACSRCADDRLO; /*MAC Source Address Low Bytes Register*/ + + /*MDIO Module Registers */ + uint32 MDIOCONTROL; /*MDIO Control Register. */ + + /* EMAC Control Module Registers */ + uint32 C0RXEN; /*EMAC Control Module Receive Interrupt Enable Register*/ + uint32 C0TXEN; /*EMAC Control Module Transmit Interrupt Enable Register*/ +} emac_config_reg_t; +/*****************************************************************************/ +/** + * @defgroup EMACMDIO EMAC/MDIO + * @brief Ethernet Media Access Controller/Management Data Input/Output. + * + * The EMAC controls the flow of packet data from the system to the PHY. The MDIO module + *controls PHY configuration and status monitoring. + * + * Both the EMAC and the MDIO modules interface to the system core through a custom + *interface that allows efficient data transmission and reception. This custom interface + *is referred to as the EMAC control module and is considered integral to the EMAC/MDIO + *peripheral + * + * Related Files + * - emac.h + * - emac.c + * - hw_emac.h + * - hw_emac_ctrl.h + * - hw_mdio.h + * - hw_reg_access.h + * - mdio.h + * - mdio.c + * @addtogroup EMACMDIO + * @{ + */ +/* +** Prototypes for the APIs +*/ +extern uint32 EMACLinkSetup( hdkif_t * hdkif ); +extern void EMACInstConfig( hdkif_t * hdkif ); +extern void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ); +extern void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ); +extern void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ); +extern void EMACTxEnable( uint32 emacBase ); +extern void EMACTxDisable( uint32 emacBase ); +extern void EMACRxEnable( uint32 emacBase ); +extern void EMACRxDisable( uint32 emacBase ); +uint32 EMACSwizzleData( uint32 word ); +extern void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ); +extern void EMACInit( uint32 emacCtrlBase, uint32 emacBase ); +extern void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ); +extern void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ); +extern void EMACMIIEnable( uint32 emacBase ); +extern void EMACMIIDisable( uint32 emacBase ); +extern void EMACRxUnicastSet( uint32 emacBase, uint32 channel ); +extern void EMACRxUnicastClear( uint32 emacBase, uint32 channel ); +extern void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ); +extern void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ); +extern void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ); +extern void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ); +extern void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ); +extern uint32 EMACIntVectorGet( uint32 emacBase ); +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ); +void EMACTxTeardown( uint32 emacBase, uint32 channel ); +void EMACRxTeardown( uint32 emacBase, uint32 channel ); +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ); +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ); +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ); +void EMACEnableIdleState( uint32 emacBase ); +void EMACDisableIdleState( uint32 emacBase ); +void EMACEnableLoopback( uint32 emacBase ); +void EMACDisableLoopback( uint32 emacBase ); +void EMACTxFlowControlEnable( uint32 emacBase ); +void EMACTxFlowControlDisable( uint32 emacBase ); +void EMACRxFlowControlEnable( uint32 emacBase ); +void EMACRxFlowControlDisable( uint32 emacBase ); +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ); +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ); +void EMACDMAInit( hdkif_t * hdkif ); +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ); +void EMACTxIntHandler( hdkif_t * hdkif ); +void EMACReceive( hdkif_t * hdkif ); +/* Notification Function to which received packets are passed after processing */ +void emacTxNotification( hdkif_t * hdkif ); +void emacRxNotification( hdkif_t * hdkif ); +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ); +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ); +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __EMAC_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h new file mode 100644 index 00000000000..035722af057 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emac_phyConfig.h @@ -0,0 +1,45 @@ +/** + * \file emac_phyConfig.h + * + * \brief PHY Configuration file for selecting and configuring the required PHY. + * + * This file contains the mappings of the PHY APIs so that the right one is chosen based + * on the user's preference. + */ + +/* (c) Texas Instruments 2009-2014, All rights reserved. */ + +#ifndef _EMAC_PHYCONFIG_H_ +#define _EMAC_PHYCONFIG_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define PhyIDGet Dp83640IDGet +#define PhyLinkStatusGet Dp83640LinkStatusGet +#define PhyAutoNegotiate Dp83640AutoNegotiate +#define PhyPartnerAbilityGet Dp83640PartnerAbilityGet +#define PhyReset Dp83640Reset +#define PhyEnableLoopback Dp83640EnableLoopback +#define PhyDisableLoopback Dp83640DisableLoopback +#define PhyGetTimeStamp Dp83640GetTimeStamp +#define PhyPartnerSpdGet Dp83640PartnerSpdGet + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* _EMAC_PHYCONFIG_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h new file mode 100644 index 00000000000..8e65dcacc63 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/emif.h @@ -0,0 +1,216 @@ +/** @file emif.h + * @brief emif Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _EMIF_H_ +#define _EMIF_H_ + +#include "reg_emif.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum emif_pins + * @brief Alias for emif pins + * + */ +enum emif_pins +{ + emif_wait_pin0 = 0U, + emif_wait_pin1 = 1U +}; + +/** @enum emif_size + * @brief Alias for emif page size + * + */ +enum emif_size +{ + elements_256 = 0U, + elements_512 = 1U, + elements_1024 = 2U, + elements_2048 = 3U +}; + +/** @enum emif_port + * @brief Alias for emif port + * + */ +enum emif_port +{ + emif_8_bit_port = 0U, + emif_16_bit_port = 1U +}; + +/** @enum emif_pagesize + * @brief Alias for emif pagesize + * + */ +enum emif_pagesize +{ + emif_4_words = 0U, + emif_8_words = 1U +}; + +/** @enum emif_wait_polarity + * @brief Alias for emif wait polarity + * + */ +enum emif_wait_polarity +{ + emif_pin_low = 0U, + emif_pin_high = 1U +}; + +#define PTR ( ( volatile uint32 * ) ( 0x80000000U ) ) + +/* Configuration registers */ +typedef struct emif_config_reg +{ + uint32 CONFIG_AWCC; + uint32 CONFIG_SDCR; + uint32 CONFIG_SDRCR; + uint32 CONFIG_CE2CFG; + uint32 CONFIG_CE3CFG; + uint32 CONFIG_CE4CFG; + uint32 CONFIG_CE5CFG; + uint32 CONFIG_SDTIMR; + uint32 CONFIG_SDSRETR; + uint32 CONFIG_INTMSK; + uint32 CONFIG_PMCR; +} emif_config_reg_t; + +/* Configuration registers initial value for EMIF*/ +#define EMIF_AWCC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) \ + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) 0xC0000000U ) + +#define EMIF_SDCR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 31U ) | ( uint32 ) ( ( uint32 ) 1U << 14U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) elements_256 ) ) + +#define EMIF_SDRCR_CONFIGVALUE 0U + +#define EMIF_CE2CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE3CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE4CFG_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) \ + | ( uint32 ) ( ( uint32 ) 15U << 26U ) | ( uint32 ) ( ( uint32 ) 63U << 20U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 17U ) | ( uint32 ) ( ( uint32 ) 15U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 63U << 7U ) | ( uint32 ) ( ( uint32 ) 7U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) emif_8_bit_port ) ) + +#define EMIF_CE5CFG_CONFIGVALUE 0x3FFFFFFDU + +#define EMIF_SDTIMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | 0x00000000U ) + +#define EMIF_SDSRETR_CONFIGVALUE 0U +#define EMIF_INTMSK_CONFIGVALUE 0x00000000U +#define EMIF_PMCR_CONFIGVALUE \ + ( 0xFC000000U | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +/** + * @defgroup EMIF EMIF + * @brief External Memory Interface. + * + * This EMIF memory controller is compliant with the JESD21-C SDR SDRAM memories + *utilizing a 16-bit data bus. The purpose of this EMIF is to provide a means for the CPU + *to connect to a variety of external devices including: + * - Single data rate (SDR) SDRAM + * - Asynchronous devices including NOR Flash and SRAM + * The most common use for the EMIF is to interface with both a flash device and an SDRAM + *device simultaneously. contains an example of operating the EMIF in this configuration. + * + * Related Files + * - reg_emif.h + * - emif.h + * - emif.c + * @addtogroup EMIF + * @{ + */ +/* EMIF Interface Functions */ + +void emif_SDRAMInit( void ); +void emif_SDRAM_StartupInit( void ); +void emif_ASYNC1Init( void ); +void emif_ASYNC2Init( void ); +void emif_ASYNC3Init( void ); +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /*EMIF_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h new file mode 100644 index 00000000000..920b963568f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/epc.h @@ -0,0 +1,134 @@ +/** @file epc.h + * @brief EPC Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EPC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef SYS_EPC_H_ +#define SYS_EPC_H_ + +#include "reg_epc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +enum CAMIndex +{ + CAMIndex_0 = 0U, + CAMIndex_1 = 1U, + CAMIndex_2 = 2U, + CAMIndex_3 = 3U, + CAMIndex_4 = 4U, + CAMIndex_5 = 5U, + CAMIndex_6 = 6U, + CAMIndex_7 = 7U, + CAMIndex_8 = 8U, + CAMIndex_9 = 9U, + CAMIndex_10 = 10U, + CAMIndex_11 = 11U, + CAMIndex_12 = 12U, + CAMIndex_13 = 13U, + CAMIndex_14 = 14U, + CAMIndex_15 = 15U, + CAMIndex_16 = 16U, + CAMIndex_17 = 17U, + CAMIndex_18 = 18U, + CAMIndex_19 = 19U, + CAMIndex_20 = 20U, + CAMIndex_21 = 21U, + CAMIndex_22 = 22U, + CAMIndex_23 = 23U, + CAMIndex_24 = 24U, + CAMIndex_25 = 25U, + CAMIndex_26 = 26U, + CAMIndex_27 = 27U, + CAMIndex_28 = 28U, + CAMIndex_29 = 29U, + CAMIndex_30 = 30U, + CAMIndex_31 = 31U +}; + +/** + * @defgroup EPC EPC + * @brief Error Profiling Controller + * + * Related files: + * - reg_epc.h + * - sys_epc.h + * - sys_epc.c + * + * @addtogroup EPC + * @{ + */ + +void epcEnableIP1ErrorGen( void ); +void epcDisableIP1ErrorGen( void ); +void epcEnableIP2ErrorGen( void ); +void epcDisableIP2ErrorGen( void ); +void epcEnableSERREvent( void ); +void epcDisableSERREvent( void ); +void epcEnableInterrupt( void ); +void epcDisableInterrupt( void ); +void epcCAMInit( void ); +boolean epcDiagnosticTest( void ); +boolean epcAddCAMEEntry( uint32 address ); +boolean epcCheckCAMEntry( uint32 index ); + +void epcCAMFullNotification( void ); +void epcFIFOFullNotification( uint32 epcFIFOStatus ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* SYS_EPC_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h new file mode 100644 index 00000000000..274a69ca691 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/eqep.h @@ -0,0 +1,863 @@ +/** @file eqep.h + * @brief EQEP Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __eQEP_H__ +#define __eQEP_H__ + +#include "reg_eqep.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define QEP_BASE_ADDR ( 0x00006B00U ) /* "Reason - TI_Fee_Fix is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_Fix + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_Fee_None is a symbolic + * constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_HANDLING TI_Fee_None + #endif + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_MAXIMUM_BLOCKING_TIME is a + * symbolic constant"*/ + #define TI_FEE_MAXIMUM_BLOCKING_TIME FEE_MAXIMUM_BLOCKING_TIME + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_OPERATING_FREQUENCY is a + * symbolic constant."*/ + #define TI_FEE_OPERATING_FREQUENCY FEE_OPERATING_FREQUENCY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_ERROR_CORRECTION_ENABLE + * is a symbolic constant."*/ + #define TI_FEE_FLASH_ERROR_CORRECTION_ENABLE FEE_FLASH_ERROR_CORRECTION_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_CHECKSUM_ENABLE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_CHECKSUM_ENABLE FEE_FLASH_CHECKSUM_ENABLE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_FLASH_WRITECOUNTER_SAVE is a + * symbolic constant."*/ + #define TI_FEE_FLASH_WRITECOUNTER_SAVE FEE_FLASH_WRITECOUNTER_SAVE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - NVM_DATASET_SELECTION_BITS is a + * symbolic constant."*/ + #define TI_FEE_DATASELECT_BITS NVM_DATASET_SELECTION_BITS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EEPS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_EEPS FEE_NUMBER_OF_EEPS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_INDEX is a symbolic + * constant."*/ + #define TI_FEE_INDEX FEE_INDEX + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PAGE_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_PAGE_OVERHEAD FEE_PAGE_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_BLOCK_OVERHEAD is a symbolic + * constant."*/ + #define TI_FEE_BLOCK_OVERHEAD FEE_BLOCK_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_PAGE_SIZE is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_PAGE_SIZE FEE_VIRTUAL_PAGE_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUAL_SECTOR_OVERHEAD is a + * symbolic constant."*/ + #define TI_FEE_VIRTUAL_SECTOR_OVERHEAD FEE_VIRTUAL_SECTOR_OVERHEAD + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY is a symbolic constant."*/ + #define TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY \ + FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_EIGHTBYTEWRITES is a + * symbolic constant."*/ + #define TI_FEE_NUMBER_OF_EIGHTBYTEWRITES FEE_NUMBER_OF_EIGHTBYTEWRITES + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_END_NOTIFICATION is a + * symbolic constant."*/ + #define TI_FEE_NVM_JOB_END_NOTIFICATION FEE_NVM_JOB_END_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NVM_JOB_ERROR_NOTIFICATION is + * a symbolic constant."*/ + #define TI_FEE_NVM_JOB_ERROR_NOTIFICATION FEE_NVM_JOB_ERROR_NOTIFICATION + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_POLLING_MODE is a symbolic + * constant."*/ + #define TI_FEE_POLLING_MODE FEE_POLLING_MODE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #ifndef FEE_CHECK_BANK7_ACCESS + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #else + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_CHECK_BANK7_ACCESS is a + * symbolic constant."*/ + #define TI_FEE_CHECK_BANK7_ACCESS STD_ON + #endif + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_TOTAL_BLOCKS_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_TOTAL_BLOCKS_DATASETS FEE_TOTAL_BLOCKS_DATASETS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_VIRTUALSECTOR_SIZE is a + * symbolic constant."*/ + #define TI_FEE_VIRTUALSECTOR_SIZE FEE_VIRTUALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_PHYSICALSECTOR_SIZE is a + * symbolic constant."*/ + #define TI_FEE_PHYSICALSECTOR_SIZE FEE_PHYSICALSECTOR_SIZE + /*SAFETYMCUSW 79 S MR:19.4 "Reason - + * FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC is a symbolic constant."*/ + #define TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC \ + FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_USEPARTIALERASEDSECTOR is a + * symbolic constant."*/ + #define TI_FEE_USEPARTIALERASEDSECTOR FEE_USEPARTIALERASEDSECTOR + + /*----------------------------------------------------------------------------*/ + /* Virtual Sector Configuration */ + + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS is a + * symbolic constant."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS FEE_NUMBER_OF_VIRTUAL_SECTORS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + * is a symbolic constant."*/ + /*SAFETYMCUSW 384 S MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + /*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - Similar Identifier name is + * required here."*/ + #define TI_FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 FEE_NUMBER_OF_VIRTUAL_SECTORS_EEP1 + + /*----------------------------------------------------------------------------*/ + /* Block Configuration */ + /*SAFETYMCUSW 79 S MR:19.4 "Reason - FEE_NUMBER_OF_BLOCKS is a symbolic + * constant."*/ + #define TI_FEE_NUMBER_OF_BLOCKS FEE_NUMBER_OF_BLOCKS + /*SAFETYMCUSW 79 S MR:19.4 "Reason - TI_FEE_VARIABLE_DATASETS is a + * symbolic constant."*/ + #define TI_FEE_VARIABLE_DATASETS STD_ON + + #endif /* TI_FEE_DRIVER */ + +#endif /* FEE_INTERFACE_H */ +/********************************************************************************************************************** + * END OF FILE: fee_interface.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h new file mode 100644 index 00000000000..ea64d9e5806 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/gio.h @@ -0,0 +1,182 @@ +/** @file gio.h + * @brief GIO Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __GIO_H__ +#define __GIO_H__ + +#include "reg_gio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef struct gio_config_reg +{ + uint32 CONFIG_INTDET; + uint32 CONFIG_POL; + uint32 CONFIG_INTENASET; + uint32 CONFIG_LVLSET; + + uint32 CONFIG_PORTADIR; + uint32 CONFIG_PORTAPDR; + uint32 CONFIG_PORTAPSL; + uint32 CONFIG_PORTAPULDIS; + + uint32 CONFIG_PORTBDIR; + uint32 CONFIG_PORTBPDR; + uint32 CONFIG_PORTBPSL; + uint32 CONFIG_PORTBPULDIS; +} gio_config_reg_t; + +#define GIO_INTDET_CONFIGVALUE 0U +#define GIO_POL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_INTENASET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_LVLSET_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) ) + +#define GIO_PORTADIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTAPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +#define GIO_PORTBDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) +#define GIO_PORTBPULDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) ) + +/** + * @defgroup GIO GIO + * @brief General-Purpose Input/Output Module. + * + * The GIO module provides the family of devices with input/output (I/O) capability. + * The I/O pins are bidirectional and bit-programmable. + * The GIO module also supports external interrupt capability. + * + * Related Files + * - reg_gio.h + * - gio.h + * - gio.c + * @addtogroup GIO + * @{ + */ + +/* GIO Interface Functions */ +void gioInit( void ); +void gioSetDirection( gioPORT_t * port, uint32 dir ); +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ); +void gioSetPort( gioPORT_t * port, uint32 value ); +uint32 gioGetBit( gioPORT_t * port, uint32 bit ); +uint32 gioGetPort( gioPORT_t * port ); +void gioToggleBit( gioPORT_t * port, uint32 bit ); +void gioEnableNotification( gioPORT_t * port, uint32 bit ); +void gioDisableNotification( gioPORT_t * port, uint32 bit ); +void gioNotification( gioPORT_t * port, uint32 bit ); +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h new file mode 100644 index 00000000000..1def1eafe6e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hal_stdtypes.h @@ -0,0 +1,185 @@ +/** @file hal_stdtypes.h + * @brief HALCoGen standard types header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Type and Global definitions which are relevant for all drivers. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HAL_STDTYPES_H__ +#define __HAL_STDTYPES_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include +#include + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ +/************************************************************/ +/* Type Definitions */ +/************************************************************/ +#ifndef _UINT64_DECLARED +typedef uint64_t uint64; + #define _UINT64_DECLARED +#endif + +#ifndef _UINT32_DECLARED +typedef uint32_t uint32; + #define _UINT32_DECLARED +#endif + +#ifndef _UINT16_DECLARED +typedef uint16_t uint16; + #define _UINT16_DECLARED +#endif + +#ifndef _UINT8_DECLARED +typedef uint8_t uint8; + #define _UINT8_DECLARED +#endif + +#ifndef _BOOLEAN_DECLARED + #ifdef __cplusplus +typedef bool boolean; + #else +typedef _Bool boolean; + #endif + #define _BOOLEAN_DECLARED +#endif + +#ifndef _SINT64_DECLARED +typedef int64_t sint64; + #define _SINT64_DECLARED +#endif + +#ifndef _SINT32_DECLARED +typedef int32_t sint32; + #define _SINT32_DECLARED +#endif + +#ifndef _SINT16_DECLARED +typedef int16_t sint16; + #define _SINT16_DECLARED +#endif + +#ifndef _SINT8_DECLARED +typedef int8_t sint8; + #define _SINT8_DECLARED +#endif + +#ifndef _FLOAT32_DECLARED +typedef float float32; + #define _FLOAT32_DECLARED +#endif + +#ifndef _FLOAT64_DECLARED +typedef double float64; + #define _FLOAT64_DECLARED +#endif + +typedef uint8 Std_ReturnType; + +typedef struct +{ + uint16 vendorID; + uint16 moduleID; + uint8 instanceID; + uint8 sw_major_version; + uint8 sw_minor_version; + uint8 sw_patch_version; +} Std_VersionInfoType; + +/*****************************************************************************/ +/* SYMBOL DEFINITIONS */ +/*****************************************************************************/ +#ifndef STATUSTYPEDEFINED + #define STATUSTYPEDEFINED + #define E_OK 0x00U + +typedef unsigned char StatusType; +#endif + +#ifndef E_NOT_OK + #define E_NOT_OK 0x01U +#endif + +#ifndef STD_ON + #define STD_ON 0x01U +#endif + +#ifndef STD_OFF + #define STD_OFF 0x00U +#endif + +/************************************************************/ +/* Global Definitions */ +/************************************************************/ +/** @def NULL + * @brief NULL definition + */ +#ifndef NULL + #define NULL ( ( void * ) 0U ) +#endif + +/** @def TRUE + * @brief definition for TRUE + */ +#ifndef TRUE + #define TRUE true +#endif + +/** @def FALSE + * @brief BOOLEAN definition for FALSE + */ +#ifndef FALSE + #define FALSE false +#endif + +/*****************************************************************************/ +/* Define: NULL_PTR */ +/* Description: Void pointer to 0 */ +/*****************************************************************************/ +#ifndef NULL_PTR + #define NULL_PTR ( ( void * ) 0x0U ) +#endif +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif /* __HAL_STDTYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h new file mode 100644 index 00000000000..ba0e72753eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/het.h @@ -0,0 +1,633 @@ +/** @file het.h + * @brief HET Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HET_H__ +#define __HET_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "reg_het.h" +#include + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @def pwm0 + * @brief Pwm signal 0 + * + * Alias for pwm signal 0 + */ +#define pwm0 0U + +/** @def pwm1 + * @brief Pwm signal 1 + * + * Alias for pwm signal 1 + */ +#define pwm1 1U + +/** @def pwm2 + * @brief Pwm signal 2 + * + * Alias for pwm signal 2 + */ +#define pwm2 2U + +/** @def pwm3 + * @brief Pwm signal 3 + * + * Alias for pwm signal 3 + */ +#define pwm3 3U + +/** @def pwm4 + * @brief Pwm signal 4 + * + * Alias for pwm signal 4 + */ +#define pwm4 4U + +/** @def pwm5 + * @brief Pwm signal 5 + * + * Alias for pwm signal 5 + */ +#define pwm5 5U + +/** @def pwm6 + * @brief Pwm signal 6 + * + * Alias for pwm signal 6 + */ +#define pwm6 6U + +/** @def pwm7 + * @brief Pwm signal 7 + * + * Alias for pwm signal 7 + */ +#define pwm7 7U + +/** @def edge0 + * @brief Edge signal 0 + * + * Alias for edge signal 0 + */ +#define edge0 0U + +/** @def edge1 + * @brief Edge signal 1 + * + * Alias for edge signal 1 + */ +#define edge1 1U + +/** @def edge2 + * @brief Edge signal 2 + * + * Alias for edge signal 2 + */ +#define edge2 2U + +/** @def edge3 + * @brief Edge signal 3 + * + * Alias for edge signal 3 + */ +#define edge3 3U + +/** @def edge4 + * @brief Edge signal 4 + * + * Alias for edge signal 4 + */ +#define edge4 4U + +/** @def edge5 + * @brief Edge signal 5 + * + * Alias for edge signal 5 + */ +#define edge5 5U + +/** @def edge6 + * @brief Edge signal 6 + * + * Alias for edge signal 6 + */ +#define edge6 6U + +/** @def edge7 + * @brief Edge signal 7 + * + * Alias for edge signal 7 + */ +#define edge7 7U + +/** @def cap0 + * @brief Capture signal 0 + * + * Alias for capture signal 0 + */ +#define cap0 0U + +/** @def cap1 + * @brief Capture signal 1 + * + * Alias for capture signal 1 + */ +#define cap1 1U + +/** @def cap2 + * @brief Capture signal 2 + * + * Alias for capture signal 2 + */ +#define cap2 2U + +/** @def cap3 + * @brief Capture signal 3 + * + * Alias for capture signal 3 + */ +#define cap3 3U + +/** @def cap4 + * @brief Capture signal 4 + * + * Alias for capture signal 4 + */ +#define cap4 4U + +/** @def cap5 + * @brief Capture signal 5 + * + * Alias for capture signal 5 + */ +#define cap5 5U + +/** @def cap6 + * @brief Capture signal 6 + * + * Alias for capture signal 6 + */ +#define cap6 6U + +/** @def cap7 + * @brief Capture signal 7 + * + * Alias for capture signal 7 + */ +#define cap7 7U + +/** @def pwmEND_OF_DUTY + * @brief Pwm end of duty + * + * Alias for pwm end of duty notification + */ +#define pwmEND_OF_DUTY 2U + +/** @def pwmEND_OF_PERIOD + * @brief Pwm end of period + * + * Alias for pwm end of period notification + */ +#define pwmEND_OF_PERIOD 4U + +/** @def pwmEND_OF_BOTH + * @brief Pwm end of duty and period + * + * Alias for pwm end of duty and period notification + */ +#define pwmEND_OF_BOTH 6U + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/** @struct hetBase + * @brief HET Register Definition + * + * This structure is used to access the HET module registers. + */ +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +enum hetPinSelect +{ + PIN_HET_0 = 0U, + PIN_HET_1 = 1U, + PIN_HET_2 = 2U, + PIN_HET_3 = 3U, + PIN_HET_4 = 4U, + PIN_HET_5 = 5U, + PIN_HET_6 = 6U, + PIN_HET_7 = 7U, + PIN_HET_8 = 8U, + PIN_HET_9 = 9U, + PIN_HET_10 = 10U, + PIN_HET_11 = 11U, + PIN_HET_12 = 12U, + PIN_HET_13 = 13U, + PIN_HET_14 = 14U, + PIN_HET_15 = 15U, + PIN_HET_16 = 16U, + PIN_HET_17 = 17U, + PIN_HET_18 = 18U, + PIN_HET_19 = 19U, + PIN_HET_20 = 20U, + PIN_HET_21 = 21U, + PIN_HET_22 = 22U, + PIN_HET_23 = 23U, + PIN_HET_24 = 24U, + PIN_HET_25 = 25U, + PIN_HET_26 = 26U, + PIN_HET_27 = 27U, + PIN_HET_28 = 28U, + PIN_HET_29 = 29U, + PIN_HET_30 = 30U, + PIN_HET_31 = 31U +}; + +/** @struct hetSignal + * @brief HET Signal Definition + * + * This structure is used to define a pwm signal. + */ +/** @typedef hetSIGNAL_t + * @brief HET Signal Type Definition + * + * This type is used to access HET Signal Information. + */ +typedef struct hetSignal +{ + uint32 duty; /**< Duty cycle in % of the period */ + float64 period; /**< Period in us */ +} hetSIGNAL_t; + +/* Configuration registers */ +typedef struct het_config_reg +{ + uint32 CONFIG_GCR; + uint32 CONFIG_PFR; + uint32 CONFIG_INTENAS; + uint32 CONFIG_INTENAC; + uint32 CONFIG_PRY; + uint32 CONFIG_AND; + uint32 CONFIG_HRSH; + uint32 CONFIG_XOR; + uint32 CONFIG_DIR; + uint32 CONFIG_PDR; + uint32 CONFIG_PULDIS; + uint32 CONFIG_PSL; + uint32 CONFIG_PCR; +} het_config_reg_t; + +/* Configuration registers initial value for HET1*/ +#define HET1_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET1_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET1_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U ) + +#define HET1_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET1_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET1_GCR_CONFIGVALUE \ + ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ) + +/* Configuration registers initial value for HET2*/ +#define HET2_DIR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PULDIS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PSL_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_HRSH_CONFIGVALUE \ + ( ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U | ( uint32 ) 0x00002000U \ + | ( uint32 ) 0x00001000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U | ( uint32 ) 0x00000002U \ + | ( uint32 ) 0x00000001U ) + +#define HET2_AND_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_XOR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U ) + +#define HET2_PFR_CONFIGVALUE ( ( ( uint32 ) 6U << 8U ) | ( uint32 ) 0U ) + +#define HET2_PRY_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAC_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_INTENAS_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U \ + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ) + +#define HET2_PCR_CONFIGVALUE ( ( uint32 ) 0x00000005U ) +#define HET2_GCR_CONFIGVALUE \ + ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ) + +/** + * @defgroup HET HET + * @brief HighEnd Timer Module. + * + * The HET is a software-controlled timer with a dedicated specialized timer micromachine + *and a set of 30 instructions. The HET micromachine is connected to a port of up to 32 + *input/output (I/O) pins. + * + * Related Files + * - reg_het.h + * - het.h + * - het.c + * - reg_htu.h + * - htu.h + * - std_nhet.h + * @addtogroup HET + * @{ + */ + +/* HET Interface Functions */ +void hetInit( void ); + +/* PWM Interface Functions */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ); +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ); +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ); +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ); +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ); + +/* Edge Interface Functions */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ); +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ); +void edgeNotification( hetBASE_t * hetREG, uint32 edge ); + +/* Captured Signal Interface Functions */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ); + +/* Timestamp Interface Functions */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ); +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ); +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void hetNotification(hetBASE_t *het, uint32 offset) + * @brief het interrupt callback + * @param[in] het - Het module base address + * - hetREG1: HET1 module base address pointer + * - hetREG2: HET2 module base address pointer + * @param[in] offset - het interrupt offset / Source number + * + * @note This function has to be provide by the user. + * + * This is a interrupt callback that is provided by the application and is call upon + * an het interrupt. The parameter passed to the callback is a copy of the interrupt + * offset register which is used to decode the interrupt source. + */ +void hetNotification( hetBASE_t * het, uint32 offset ); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h new file mode 100644 index 00000000000..414c09fc037 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/htu.h @@ -0,0 +1,70 @@ +/** @file htu.h + * @brief HTU Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __HTU_H__ +#define __HTU_H__ + +#include "reg_htu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* HTU General Definitions */ + +#define HTU1PARLOC ( *( volatile uint32 * ) 0xFF4E0200U ) +#define HTU2PARLOC ( *( volatile uint32 * ) 0xFF4C0200U ) + +#define HTU1RAMLOC ( *( volatile uint32 * ) 0xFF4E0000U ) +#define HTU2RAMLOC ( *( volatile uint32 * ) 0xFF4C0000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h new file mode 100644 index 00000000000..7ca60027f51 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac.h @@ -0,0 +1,1304 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_H_ +#define _HW_EMAC_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_BASE ( 0xFCF78000U ) +#define EMAC_CTRL_BASE ( 0xFCF78800U ) +#define EMAC_CTRL_RAM_BASE ( 0xFC520000U ) + +#define EMAC_TXREVID ( 0x0U ) +#define EMAC_TXCONTROL ( 0x4U ) +#define EMAC_TXTEARDOWN ( 0x8U ) +#define EMAC_RXREVID ( 0x10U ) +#define EMAC_RXCONTROL ( 0x14U ) +#define EMAC_RXTEARDOWN ( 0x18U ) +#define EMAC_TXINTSTATRAW ( 0x80U ) +#define EMAC_TXINTSTATMASKED ( 0x84U ) +#define EMAC_TXINTMASKSET ( 0x88U ) +#define EMAC_TXINTMASKCLEAR ( 0x8CU ) +#define EMAC_MACINVECTOR ( 0x90U ) +#define EMAC_MACEOIVECTOR ( 0x94U ) +#define EMAC_RXINTSTATRAW ( 0xA0U ) +#define EMAC_RXINTSTATMASKED ( 0xA4U ) +#define EMAC_RXINTMASKSET ( 0xA8U ) +#define EMAC_RXINTMASKCLEAR ( 0xACU ) +#define EMAC_MACINTSTATRAW ( 0xB0U ) +#define EMAC_MACINTSTATMASKED ( 0xB4U ) +#define EMAC_MACINTMASKSET ( 0xB8U ) +#define EMAC_MACINTMASKCLEAR ( 0xBCU ) +#define EMAC_RXMBPENABLE ( 0x100U ) +#define EMAC_RXUNICASTSET ( 0x104U ) +#define EMAC_RXUNICASTCLEAR ( 0x108U ) +#define EMAC_RXMAXLEN ( 0x10CU ) +#define EMAC_RXBUFFEROFFSET ( 0x110U ) +#define EMAC_RXFILTERLOWTHRESH ( 0x114U ) +#define EMAC_RXFLOWTHRESH( n ) ( ( uint32 ) 0x120U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXFREEBUFFER( n ) ( ( uint32 ) 0x140U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_MACCONTROL ( 0x160U ) +#define EMAC_MACSTATUS ( 0x164U ) +#define EMAC_EMCONTROL ( 0x168U ) +#define EMAC_FIFOCONTROL ( 0x16CU ) +#define EMAC_MACCONFIG ( 0x170U ) +#define EMAC_SOFTRESET ( 0x174U ) +#define EMAC_MACSRCADDRLO ( 0x1D0U ) +#define EMAC_MACSRCADDRHI ( 0x1D4U ) +#define EMAC_MACHASH1 ( 0x1D8U ) +#define EMAC_MACHASH2 ( 0x1DCU ) +#define EMAC_BOFFTEST ( 0x1E0U ) +#define EMAC_TPACETEST ( 0x1E4U ) +#define EMAC_RXPAUSE ( 0x1E8U ) +#define EMAC_TXPAUSE ( 0x1ECU ) +#define EMAC_RXGOODFRAMES ( 0x200U ) +#define EMAC_RXBCASTFRAMES ( 0x204U ) +#define EMAC_RXMCASTFRAMES ( 0x208U ) +#define EMAC_RXPAUSEFRAMES ( 0x20CU ) +#define EMAC_RXCRCERRORS ( 0x210U ) +#define EMAC_RXALIGNCODEERRORS ( 0x214U ) +#define EMAC_RXOVERSIZED ( 0x218U ) +#define EMAC_RXJABBER ( 0x21CU ) +#define EMAC_RXUNDERSIZED ( 0x220U ) +#define EMAC_RXFRAGMENTS ( 0x224U ) +#define EMAC_RXFILTERED ( 0x228U ) +#define EMAC_RXQOSFILTERED ( 0x22CU ) +#define EMAC_RXOCTETS ( 0x230U ) +#define EMAC_TXGOODFRAMES ( 0x234U ) +#define EMAC_TXBCASTFRAMES ( 0x238U ) +#define EMAC_TXMCASTFRAMES ( 0x23CU ) +#define EMAC_TXPAUSEFRAMES ( 0x240U ) +#define EMAC_TXDEFERRED ( 0x244U ) +#define EMAC_TXCOLLISION ( 0x248U ) +#define EMAC_TXSINGLECOLL ( 0x24CU ) +#define EMAC_TXMULTICOLL ( 0x250U ) +#define EMAC_TXEXCESSIVECOLL ( 0x254U ) +#define EMAC_TXLATECOLL ( 0x258U ) +#define EMAC_TXUNDERRUN ( 0x25CU ) +#define EMAC_TXCARRIERSENSE ( 0x260U ) +#define EMAC_TXOCTETS ( 0x264U ) +#define EMAC_FRAME64 ( 0x268U ) +#define EMAC_FRAME65T127 ( 0x26CU ) +#define EMAC_FRAME128T255 ( 0x270U ) +#define EMAC_FRAME256T511 ( 0x274U ) +#define EMAC_FRAME512T1023 ( 0x278U ) +#define EMAC_FRAME1024TUP ( 0x27CU ) +#define EMAC_NETOCTETS ( 0x208U ) +#define EMAC_RXSOFOVERRUNS ( 0x284U ) +#define EMAC_RXMOFOVERRUNS ( 0x288U ) +#define EMAC_RXDMAOVERRUNS ( 0x28CU ) +#define EMAC_MACADDRLO ( 0x500U ) +#define EMAC_MACADDRHI ( 0x504U ) +#define EMAC_MACINDEX ( 0x508U ) +#define EMAC_TXHDP( n ) ( ( uint32 ) 0x600U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXHDP( n ) ( ( uint32 ) 0x620U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_TXCP( n ) ( ( uint32 ) 0x640U + ( uint32 ) ( ( n ) * 4U ) ) +#define EMAC_RXCP( n ) ( ( uint32 ) 0x660U + ( uint32 ) ( ( n ) * 4U ) ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* TXREVID */ + +#define EMAC_TXREVID_TXREV ( 0xFFFFFFFFU ) +#define EMAC_TXREVID_TXREV_SHIFT ( 0x00000000U ) + +/* TXCONTROL */ + +#define EMAC_TXCONTROL_TXEN ( 0x00000001U ) +#define EMAC_TXCONTROL_TXEN_SHIFT ( 0x00000000U ) +#define EMAC_TXCONTROL_TXDIS ( 0x00000000U ) + +/* TXTEARDOWN */ + +#define EMAC_TXTEARDOWN_TXTDNCH ( 0x00000007U ) +#define EMAC_TXTEARDOWN_TXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_TXTEARDOWN_TXTDNCH_CHA7 ( 0x00000007U ) + +/* RXREVID */ + +#define EMAC_RXREVID_RXREV ( 0xFFFFFFFFU ) +#define EMAC_RXREVID_RXREV_SHIFT ( 0x00000000U ) + +/* RXCONTROL */ + +#define EMAC_RXCONTROL_RXEN ( 0x00000001U ) +#define EMAC_RXCONTROL_RXEN_SHIFT ( 0x00000000U ) +#define EMAC_RXCONTROL_RXDIS ( 0x00000000U ) + +/* RXTEARDOWN */ + +#define EMAC_RXTEARDOWN_RXTDNCH ( 0x00000007U ) +#define EMAC_RXTEARDOWN_RXTDNCH_SHIFT ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA0 ( 0x00000000U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA1 ( 0x00000001U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA2 ( 0x00000002U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA3 ( 0x00000003U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA4 ( 0x00000004U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA5 ( 0x00000005U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA6 ( 0x00000006U ) +#define EMAC_RXTEARDOWN_RXTDNCH_CHA7 ( 0x00000007U ) + +/* TXINTSTATRAW */ + +#define EMAC_TXINTSTATRAW_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATRAW_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATRAW_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATRAW_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATRAW_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATRAW_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATRAW_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATRAW_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATRAW_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATRAW_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATRAW_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATRAW_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATRAW_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATRAW_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATRAW_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATRAW_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTSTATMASKED */ + +#define EMAC_TXINTSTATMASKED_TX7PEND ( 0x00000080U ) +#define EMAC_TXINTSTATMASKED_TX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTSTATMASKED_TX6PEND ( 0x00000040U ) +#define EMAC_TXINTSTATMASKED_TX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTSTATMASKED_TX5PEND ( 0x00000020U ) +#define EMAC_TXINTSTATMASKED_TX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTSTATMASKED_TX4PEND ( 0x00000010U ) +#define EMAC_TXINTSTATMASKED_TX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTSTATMASKED_TX3PEND ( 0x00000008U ) +#define EMAC_TXINTSTATMASKED_TX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTSTATMASKED_TX2PEND ( 0x00000004U ) +#define EMAC_TXINTSTATMASKED_TX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTSTATMASKED_TX1PEND ( 0x00000002U ) +#define EMAC_TXINTSTATMASKED_TX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTSTATMASKED_TX0PEND ( 0x00000001U ) +#define EMAC_TXINTSTATMASKED_TX0PEND_SHIFT ( 0x00000000U ) + +/* TXINTMASKSET */ + +#define EMAC_TXINTMASKSET_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKSET_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKSET_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKSET_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKSET_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKSET_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKSET_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKSET_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKSET_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKSET_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKSET_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKSET_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKSET_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKSET_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKSET_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKSET_TX0MASK_SHIFT ( 0x00000000U ) + +/* TXINTMASKCLEAR */ + +#define EMAC_TXINTMASKCLEAR_TX7MASK ( 0x00000080U ) +#define EMAC_TXINTMASKCLEAR_TX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_TXINTMASKCLEAR_TX6MASK ( 0x00000040U ) +#define EMAC_TXINTMASKCLEAR_TX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_TXINTMASKCLEAR_TX5MASK ( 0x00000020U ) +#define EMAC_TXINTMASKCLEAR_TX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_TXINTMASKCLEAR_TX4MASK ( 0x00000010U ) +#define EMAC_TXINTMASKCLEAR_TX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_TXINTMASKCLEAR_TX3MASK ( 0x00000008U ) +#define EMAC_TXINTMASKCLEAR_TX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_TXINTMASKCLEAR_TX2MASK ( 0x00000004U ) +#define EMAC_TXINTMASKCLEAR_TX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_TXINTMASKCLEAR_TX1MASK ( 0x00000002U ) +#define EMAC_TXINTMASKCLEAR_TX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_TXINTMASKCLEAR_TX0MASK ( 0x00000001U ) +#define EMAC_TXINTMASKCLEAR_TX0MASK_SHIFT ( 0x00000000U ) + +/* MACINVECTOR */ + +#define EMAC_MACINVECTOR_STATPEND ( 0x08000000U ) +#define EMAC_MACINVECTOR_STATPEND_SHIFT ( 0x0000001BU ) + +#define EMAC_MACINVECTOR_HOSTPEND ( 0x04000000U ) +#define EMAC_MACINVECTOR_HOSTPEND_SHIFT ( 0x0000001AU ) + +#define EMAC_MACINVECTOR_LINKINT0 ( 0x02000000U ) +#define EMAC_MACINVECTOR_LINKINT0_SHIFT ( 0x00000019U ) + +#define EMAC_MACINVECTOR_USERINT0 ( 0x01000000U ) +#define EMAC_MACINVECTOR_USERINT0_SHIFT ( 0x00000018U ) + +#define EMAC_MACINVECTOR_TXPEND ( 0x00FF0000U ) +#define EMAC_MACINVECTOR_TXPEND_SHIFT ( 0x00000010U ) + +#define EMAC_MACINVECTOR_RXTHRESHPEND ( 0x0000FF00U ) +#define EMAC_MACINVECTOR_RXTHRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_MACINVECTOR_RXPEND ( 0x000000FFU ) +#define EMAC_MACINVECTOR_RXPEND_SHIFT ( 0x00000000U ) + +/* MACEOIVECTOR */ + +#define EMAC_MACEOIVECTOR_INTVECT ( 0x0000001FU ) +#define EMAC_MACEOIVECTOR_INTVECT_SHIFT ( 0x00000000U ) +/*----INTVECT Tokens----*/ +#define EMAC_MACEOIVECTOR_INTVECT_C0RXTHRESH ( 0x00000000U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0RX ( 0x00000001U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0TX ( 0x00000002U ) +#define EMAC_MACEOIVECTOR_INTVECT_C0MISC ( 0x00000003U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RXTHRESH ( 0x00000004U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1RX ( 0x00000005U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1TX ( 0x00000006U ) +#define EMAC_MACEOIVECTOR_INTVECT_C1MISC ( 0x00000007U ) + +/* RXINTSTATRAW */ + +#define EMAC_RXINTSTATRAW_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATRAW_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATRAW_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATRAW_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATRAW_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATRAW_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATRAW_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATRAW_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATRAW_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATRAW_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATRAW_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATRAW_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATRAW_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATRAW_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATRAW_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATRAW_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATRAW_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATRAW_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATRAW_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATRAW_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATRAW_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATRAW_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATRAW_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATRAW_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATRAW_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATRAW_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATRAW_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATRAW_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATRAW_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATRAW_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATRAW_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATRAW_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTSTATMASKED */ + +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND ( 0x00008000U ) +#define EMAC_RXINTSTATMASKED_RX7THRESHPEND_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND ( 0x00004000U ) +#define EMAC_RXINTSTATMASKED_RX6THRESHPEND_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND ( 0x00002000U ) +#define EMAC_RXINTSTATMASKED_RX5THRESHPEND_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND ( 0x00001000U ) +#define EMAC_RXINTSTATMASKED_RX4THRESHPEND_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND ( 0x00000800U ) +#define EMAC_RXINTSTATMASKED_RX3THRESHPEND_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND ( 0x00000400U ) +#define EMAC_RXINTSTATMASKED_RX2THRESHPEND_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND ( 0x00000200U ) +#define EMAC_RXINTSTATMASKED_RX1THRESHPEND_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND ( 0x00000100U ) +#define EMAC_RXINTSTATMASKED_RX0THRESHPEND_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTSTATMASKED_RX7PEND ( 0x00000080U ) +#define EMAC_RXINTSTATMASKED_RX7PEND_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTSTATMASKED_RX6PEND ( 0x00000040U ) +#define EMAC_RXINTSTATMASKED_RX6PEND_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTSTATMASKED_RX5PEND ( 0x00000020U ) +#define EMAC_RXINTSTATMASKED_RX5PEND_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTSTATMASKED_RX4PEND ( 0x00000010U ) +#define EMAC_RXINTSTATMASKED_RX4PEND_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTSTATMASKED_RX3PEND ( 0x00000008U ) +#define EMAC_RXINTSTATMASKED_RX3PEND_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTSTATMASKED_RX2PEND ( 0x00000004U ) +#define EMAC_RXINTSTATMASKED_RX2PEND_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTSTATMASKED_RX1PEND ( 0x00000002U ) +#define EMAC_RXINTSTATMASKED_RX1PEND_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTSTATMASKED_RX0PEND ( 0x00000001U ) +#define EMAC_RXINTSTATMASKED_RX0PEND_SHIFT ( 0x00000000U ) + +/* RXINTMASKSET */ + +#define EMAC_RXINTMASKSET_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKSET_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKSET_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKSET_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKSET_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKSET_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKSET_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKSET_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKSET_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKSET_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKSET_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKSET_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKSET_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKSET_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKSET_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKSET_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKSET_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKSET_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKSET_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKSET_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKSET_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKSET_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKSET_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKSET_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKSET_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKSET_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKSET_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKSET_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKSET_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKSET_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKSET_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKSET_RX0MASK_SHIFT ( 0x00000000U ) + +/* RXINTMASKCLEAR */ + +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK ( 0x00008000U ) +#define EMAC_RXINTMASKCLEAR_RX7THRESHMASK_SHIFT ( 0x0000000FU ) + +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK ( 0x00004000U ) +#define EMAC_RXINTMASKCLEAR_RX6THRESHMASK_SHIFT ( 0x0000000EU ) + +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK ( 0x00002000U ) +#define EMAC_RXINTMASKCLEAR_RX5THRESHMASK_SHIFT ( 0x0000000DU ) + +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK ( 0x00001000U ) +#define EMAC_RXINTMASKCLEAR_RX4THRESHMASK_SHIFT ( 0x0000000CU ) + +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK ( 0x00000800U ) +#define EMAC_RXINTMASKCLEAR_RX3THRESHMASK_SHIFT ( 0x0000000BU ) + +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK ( 0x00000400U ) +#define EMAC_RXINTMASKCLEAR_RX2THRESHMASK_SHIFT ( 0x0000000AU ) + +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK ( 0x00000200U ) +#define EMAC_RXINTMASKCLEAR_RX1THRESHMASK_SHIFT ( 0x00000009U ) + +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK ( 0x00000100U ) +#define EMAC_RXINTMASKCLEAR_RX0THRESHMASK_SHIFT ( 0x00000008U ) + +#define EMAC_RXINTMASKCLEAR_RX7MASK ( 0x00000080U ) +#define EMAC_RXINTMASKCLEAR_RX7MASK_SHIFT ( 0x00000007U ) + +#define EMAC_RXINTMASKCLEAR_RX6MASK ( 0x00000040U ) +#define EMAC_RXINTMASKCLEAR_RX6MASK_SHIFT ( 0x00000006U ) + +#define EMAC_RXINTMASKCLEAR_RX5MASK ( 0x00000020U ) +#define EMAC_RXINTMASKCLEAR_RX5MASK_SHIFT ( 0x00000005U ) + +#define EMAC_RXINTMASKCLEAR_RX4MASK ( 0x00000010U ) +#define EMAC_RXINTMASKCLEAR_RX4MASK_SHIFT ( 0x00000004U ) + +#define EMAC_RXINTMASKCLEAR_RX3MASK ( 0x00000008U ) +#define EMAC_RXINTMASKCLEAR_RX3MASK_SHIFT ( 0x00000003U ) + +#define EMAC_RXINTMASKCLEAR_RX2MASK ( 0x00000004U ) +#define EMAC_RXINTMASKCLEAR_RX2MASK_SHIFT ( 0x00000002U ) + +#define EMAC_RXINTMASKCLEAR_RX1MASK ( 0x00000002U ) +#define EMAC_RXINTMASKCLEAR_RX1MASK_SHIFT ( 0x00000001U ) + +#define EMAC_RXINTMASKCLEAR_RX0MASK ( 0x00000001U ) +#define EMAC_RXINTMASKCLEAR_RX0MASK_SHIFT ( 0x00000000U ) + +/* MACINTSTATRAW */ + +#define EMAC_MACINTSTATRAW_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATRAW_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATRAW_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATRAW_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTSTATMASKED */ + +#define EMAC_MACINTSTATMASKED_HOSTPEND ( 0x00000002U ) +#define EMAC_MACINTSTATMASKED_HOSTPEND_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTSTATMASKED_STATPEND ( 0x00000001U ) +#define EMAC_MACINTSTATMASKED_STATPEND_SHIFT ( 0x00000000U ) + +/* MACINTMASKSET */ + +#define EMAC_MACINTMASKSET_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKSET_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKSET_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKSET_STATMASK_SHIFT ( 0x00000000U ) + +/* MACINTMASKCLEAR */ + +#define EMAC_MACINTMASKCLEAR_HOSTMASK ( 0x00000002U ) +#define EMAC_MACINTMASKCLEAR_HOSTMASK_SHIFT ( 0x00000001U ) + +#define EMAC_MACINTMASKCLEAR_STATMASK ( 0x00000001U ) +#define EMAC_MACINTMASKCLEAR_STATMASK_SHIFT ( 0x00000000U ) + +/* RXMBPENABLE */ + +#define EMAC_RXMBPENABLE_RXPASSCRC ( 0x40000000U ) +#define EMAC_RXMBPENABLE_RXPASSCRC_SHIFT ( 0x0000001EU ) +#define EMAC_RXMBPENABLE_RXQOSEN ( 0x20000000U ) +#define EMAC_RXMBPENABLE_RXQOSEN_SHIFT ( 0x0000001DU ) +#define EMAC_RXMBPENABLE_RXNOCHAIN ( 0x10000000U ) +#define EMAC_RXMBPENABLE_RXNOCHAIN_SHIFT ( 0x0000001CU ) +#define EMAC_RXMBPENABLE_RXCMFEN ( 0x01000000U ) +#define EMAC_RXMBPENABLE_RXCMFEN_SHIFT ( 0x00000018U ) +#define EMAC_RXMBPENABLE_RXCSFEN ( 0x00800000U ) +#define EMAC_RXMBPENABLE_RXCSFEN_SHIFT ( 0x00000017U ) +#define EMAC_RXMBPENABLE_RXCEFEN ( 0x00400000U ) +#define EMAC_RXMBPENABLE_RXCEFEN_SHIFT ( 0x00000016U ) +#define EMAC_RXMBPENABLE_RXCAFEN ( 0x00200000U ) +#define EMAC_RXMBPENABLE_RXCAFEN_SHIFT ( 0x00000015U ) +/*----RXCAFEN Tokens----*/ +#define EMAC_RXMBPENABLE_RXPROMCH ( 0x00070000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_SHIFT ( 0x00000010U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXPROMCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXBROADEN ( 0x00002000U ) +#define EMAC_RXMBPENABLE_RXBROADEN_SHIFT ( 0x0000000DU ) +#define EMAC_RXMBPENABLE_RXBROADCH ( 0x00000700U ) +#define EMAC_RXMBPENABLE_RXBROADCH_SHIFT ( 0x00000008U ) +/*----RXBROADCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXBROADCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXBROADCH_CHA7 ( 0x00000007U ) + +#define EMAC_RXMBPENABLE_RXMULTEN ( 0x00000020U ) +#define EMAC_RXMBPENABLE_RXMULTEN_SHIFT ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH ( 0x00000007U ) +#define EMAC_RXMBPENABLE_RXMULTCH_SHIFT ( 0x00000000U ) +/*----RXMULTCH Tokens----*/ +#define EMAC_RXMBPENABLE_RXMULTCH_CHA0 ( 0x00000000U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA1 ( 0x00000001U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA2 ( 0x00000002U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA3 ( 0x00000003U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA4 ( 0x00000004U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA5 ( 0x00000005U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA6 ( 0x00000006U ) +#define EMAC_RXMBPENABLE_RXMULTCH_CHA7 ( 0x00000007U ) + +/* RXUNICASTSET */ + +#define EMAC_RXUNICASTSET_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTSET_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTSET_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTSET_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTSET_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTSET_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTSET_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTSET_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTSET_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTSET_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTSET_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTSET_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTSET_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXUNICASTCLEAR */ + +#define EMAC_RXUNICASTCLEAR_RXCH7EN ( 0x00000080U ) +#define EMAC_RXUNICASTCLEAR_RXCH7EN_SHIFT ( 0x00000007U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN ( 0x00000040U ) +#define EMAC_RXUNICASTCLEAR_RXCH6EN_SHIFT ( 0x00000006U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN ( 0x00000020U ) +#define EMAC_RXUNICASTCLEAR_RXCH5EN_SHIFT ( 0x00000005U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN ( 0x00000010U ) +#define EMAC_RXUNICASTCLEAR_RXCH4EN_SHIFT ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN ( 0x00000008U ) +#define EMAC_RXUNICASTCLEAR_RXCH3EN_SHIFT ( 0x00000003U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN ( 0x00000004U ) +#define EMAC_RXUNICASTCLEAR_RXCH2EN_SHIFT ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN ( 0x00000002U ) +#define EMAC_RXUNICASTCLEAR_RXCH1EN_SHIFT ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN ( 0x00000001U ) +#define EMAC_RXUNICASTCLEAR_RXCH0EN_SHIFT ( 0x00000000U ) + +/* RXMAXLEN */ + +#define EMAC_RXMAXLEN_RXMAXLEN ( 0x0000FFFFU ) +#define EMAC_RXMAXLEN_RXMAXLEN_SHIFT ( 0x00000000U ) + +/* RXBUFFEROFFSET */ + +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET ( 0x0000FFFFU ) +#define EMAC_RXBUFFEROFFSET_RXBUFFEROFFSET_SHIFT ( 0x00000000U ) + +/* RXFILTERLOWTHRESH */ + +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH ( 0x000000FFU ) +#define EMAC_RXFILTERLOWTHRESH_RXFILTERTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FLOWTHRESH */ + +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX0FLOWTHRESH_RX0FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX1FLOWTHRESH */ + +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX1FLOWTHRESH_RX1FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX2FLOWTHRESH */ + +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX2FLOWTHRESH_RX2FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX3FLOWTHRESH */ + +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX3FLOWTHRESH_RX3FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX4FLOWTHRESH */ + +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX4FLOWTHRESH_RX4FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX5FLOWTHRESH */ + +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX5FLOWTHRESH_RX5FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX6FLOWTHRESH */ + +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX6FLOWTHRESH_RX6FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX7FLOWTHRESH */ + +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH ( 0x000000FFU ) +#define EMAC_RX7FLOWTHRESH_RX7FLOWTHRESH_SHIFT ( 0x00000000U ) + +/* RX0FREEBUFFER */ + +#define EMAC_RX0FREEBUFFER_RX0FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX0FREEBUFFER_RX0FREEBUF_SHIFT ( 0x00000000U ) + +/* RX1FREEBUFFER */ + +#define EMAC_RX1FREEBUFFER_RX1FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX1FREEBUFFER_RX1FREEBUF_SHIFT ( 0x00000000U ) + +/* RX2FREEBUFFER */ + +#define EMAC_RX2FREEBUFFER_RX2FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX2FREEBUFFER_RX2FREEBUF_SHIFT ( 0x00000000U ) + +/* RX3FREEBUFFER */ + +#define EMAC_RX3FREEBUFFER_RX3FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX3FREEBUFFER_RX3FREEBUF_SHIFT ( 0x00000000U ) + +/* RX4FREEBUFFER */ + +#define EMAC_RX4FREEBUFFER_RX4FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX4FREEBUFFER_RX4FREEBUF_SHIFT ( 0x00000000U ) + +/* RX5FREEBUFFER */ + +#define EMAC_RX5FREEBUFFER_RX5FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX5FREEBUFFER_RX5FREEBUF_SHIFT ( 0x00000000U ) + +/* RX6FREEBUFFER */ + +#define EMAC_RX6FREEBUFFER_RX6FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX6FREEBUFFER_RX6FREEBUF_SHIFT ( 0x00000000U ) + +/* RX7FREEBUFFER */ + +#define EMAC_RX7FREEBUFFER_RX7FREEBUF ( 0x0000FFFFU ) +#define EMAC_RX7FREEBUFFER_RX7FREEBUF_SHIFT ( 0x00000000U ) + +/* MACCONTROL */ + +#define EMAC_MACCONTROL_RMIISPEED ( 0x00008000U ) +#define EMAC_MACCONTROL_RMIISPEED_SHIFT ( 0x0000000FU ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK ( 0x00004000U ) +#define EMAC_MACCONTROL_RXOFFLENBLOCK_SHIFT ( 0x0000000EU ) +#define EMAC_MACCONTROL_RXOWNERSHIP ( 0x00002000U ) +#define EMAC_MACCONTROL_RXOWNERSHIP_SHIFT ( 0x0000000DU ) +#define EMAC_MACCONTROL_CMDIDLE ( 0x00000800U ) +#define EMAC_MACCONTROL_CMDIDLE_SHIFT ( 0x0000000BU ) +#define EMAC_MACCONTROL_TXSHORTGAPEN ( 0x00000400U ) +#define EMAC_MACCONTROL_TXSHORTGAPEN_SHIFT ( 0x0000000AU ) +#define EMAC_MACCONTROL_TXPTYPE ( 0x00000200U ) +#define EMAC_MACCONTROL_TXPTYPE_SHIFT ( 0x00000009U ) +#define EMAC_MACCONTROL_TXPACE ( 0x00000040U ) +#define EMAC_MACCONTROL_TXPACE_SHIFT ( 0x00000006U ) +#define EMAC_MACCONTROL_GMIIEN ( 0x00000020U ) +#define EMAC_MACCONTROL_GMIIEN_SHIFT ( 0x00000005U ) +#define EMAC_MACCONTROL_TXFLOWEN ( 0x00000010U ) +#define EMAC_MACCONTROL_TXFLOWEN_SHIFT ( 0x00000004U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN ( 0x00000008U ) +#define EMAC_MACCONTROL_RXBUFFERFLOWEN_SHIFT ( 0x00000003U ) +#define EMAC_MACCONTROL_LOOPBACK ( 0x00000002U ) +#define EMAC_MACCONTROL_LOOPBACK_SHIFT ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX ( 0x00000001U ) +#define EMAC_MACCONTROL_FULLDUPLEX_SHIFT ( 0x00000000U ) + +/* MACSTATUS */ + +#define EMAC_MACSTATUS_IDLE ( 0x80000000U ) +#define EMAC_MACSTATUS_IDLE_SHIFT ( 0x0000001FU ) +#define EMAC_MACSTATUS_TXERRCODE ( 0x00F00000U ) +#define EMAC_MACSTATUS_TXERRCODE_SHIFT ( 0x00000014U ) +/*----TXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_TXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCODE_SOPERROR ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCODE_NOEOP ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLPTR ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCODE_NULLEN ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCODE_LENERROR ( 0x00000006U ) + +#define EMAC_MACSTATUS_TXERRCH ( 0x00070000U ) +#define EMAC_MACSTATUS_TXERRCH_SHIFT ( 0x00000010U ) +/*----TXERRCH Tokens----*/ +#define EMAC_MACSTATUS_TXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_TXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_TXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_TXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_TXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_TXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_TXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_TXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXERRCODE ( 0x0000F000U ) +#define EMAC_MACSTATUS_RXERRCODE_SHIFT ( 0x0000000CU ) +/*----RXERRCODE Tokens----*/ +#define EMAC_MACSTATUS_RXERRCODE_NOERROR ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCODE_OWNERSHIP ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCODE_NULLPTR ( 0x00000004U ) + +#define EMAC_MACSTATUS_RXERRCH ( 0x00000700U ) +#define EMAC_MACSTATUS_RXERRCH_SHIFT ( 0x00000008U ) +/*----RXERRCH Tokens----*/ +#define EMAC_MACSTATUS_RXERRCH_CHA0 ( 0x00000000U ) +#define EMAC_MACSTATUS_RXERRCH_CHA1 ( 0x00000001U ) +#define EMAC_MACSTATUS_RXERRCH_CHA2 ( 0x00000002U ) +#define EMAC_MACSTATUS_RXERRCH_CHA3 ( 0x00000003U ) +#define EMAC_MACSTATUS_RXERRCH_CHA4 ( 0x00000004U ) +#define EMAC_MACSTATUS_RXERRCH_CHA5 ( 0x00000005U ) +#define EMAC_MACSTATUS_RXERRCH_CHA6 ( 0x00000006U ) +#define EMAC_MACSTATUS_RXERRCH_CHA7 ( 0x00000007U ) + +#define EMAC_MACSTATUS_RXQOSACT ( 0x00000004U ) +#define EMAC_MACSTATUS_RXQOSACT_SHIFT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT ( 0x00000002U ) +#define EMAC_MACSTATUS_RXFLOWACT_SHIFT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT ( 0x00000001U ) +#define EMAC_MACSTATUS_TXFLOWACT_SHIFT ( 0x00000000U ) + +/* EMCONTROL */ + +#define EMAC_EMCONTROL_SOFT ( 0x00000002U ) +#define EMAC_EMCONTROL_SOFT_SHIFT ( 0x00000001U ) + +#define EMAC_EMCONTROL_FREE ( 0x00000001U ) +#define EMAC_EMCONTROL_FREE_SHIFT ( 0x00000000U ) + +/* FIFOCONTROL */ + +#define EMAC_FIFOCONTROL_TXCELLTHRESH ( 0x00000003U ) +#define EMAC_FIFOCONTROL_TXCELLTHRESH_SHIFT ( 0x00000000U ) + +/* MACCONFIG */ + +#define EMAC_MACCONFIG_TXCELLDEPTH ( 0xFF000000U ) +#define EMAC_MACCONFIG_TXCELLDEPTH_SHIFT ( 0x00000018U ) + +#define EMAC_MACCONFIG_RXCELLDEPTH ( 0x00FF0000U ) +#define EMAC_MACCONFIG_RXCELLDEPTH_SHIFT ( 0x00000010U ) + +#define EMAC_MACCONFIG_ADDRESSTYPE ( 0x0000FF00U ) +#define EMAC_MACCONFIG_ADDRESSTYPE_SHIFT ( 0x00000008U ) + +#define EMAC_MACCONFIG_MACCFIG ( 0x000000FFU ) +#define EMAC_MACCONFIG_MACCFIG_SHIFT ( 0x00000000U ) + +/* SOFTRESET */ + +#define EMAC_SOFTRESET_SOFTRESET ( 0x00000001U ) +#define EMAC_SOFTRESET_SOFTRESET_SHIFT ( 0x00000000U ) + +/* MACSRCADDRLO */ + +#define EMAC_MACSRCADDRLO_MACSRCADDR0 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1 ( 0x000000FFU ) +#define EMAC_MACSRCADDRLO_MACSRCADDR1_SHIFT ( 0x00000000U ) + +/* MACSRCADDRHI */ + +#define EMAC_MACSRCADDRHI_MACSRCADDR2 ( 0xFF000000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR3 ( 0x00FF0000U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR4 ( 0x0000FF00U ) +#define EMAC_MACSRCADDRHI_MACSRCADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACSRCADDRHI_MACSRCADDR5 ( 0x000000FFU ) +#define EMAC_MACSRCADDRHI_MACSRCADDR5_SHIFT ( 0x00000000U ) + +/* MACHASH1 */ + +#define EMAC_MACHASH1_MACHASH1 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH1_MACHASH1_SHIFT ( 0x00000000U ) + +/* MACHASH2 */ + +#define EMAC_MACHASH2_MACHASH2 ( 0xFFFFFFFFU ) +#define EMAC_MACHASH2_MACHASH2_SHIFT ( 0x00000000U ) + +/* BOFFTEST */ + +#define EMAC_BOFFTEST_RNDNUM ( 0x03FF0000U ) +#define EMAC_BOFFTEST_RNDNUM_SHIFT ( 0x00000010U ) + +#define EMAC_BOFFTEST_COLLCOUNT ( 0x0000F000U ) +#define EMAC_BOFFTEST_COLLCOUNT_SHIFT ( 0x0000000CU ) + +#define EMAC_BOFFTEST_TXBACKOFF ( 0x000003FFU ) +#define EMAC_BOFFTEST_TXBACKOFF_SHIFT ( 0x00000000U ) + +/* TPACETEST */ + +#define EMAC_TPACETEST_PACEVAL ( 0x0000001FU ) +#define EMAC_TPACETEST_PACEVAL_SHIFT ( 0x00000000U ) + +/* RXPAUSE */ + +#define EMAC_RXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_RXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* TXPAUSE */ + +#define EMAC_TXPAUSE_PAUSETIMER ( 0x0000FFFFU ) +#define EMAC_TXPAUSE_PAUSETIMER_SHIFT ( 0x00000000U ) + +/* RXGOODFRAMES */ + +#define EMAC_RXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXBCASTFRAMES */ + +#define EMAC_RXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXMCASTFRAMES */ + +#define EMAC_RXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXPAUSEFRAMES */ + +#define EMAC_RXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* RXCRCERRORS */ + +#define EMAC_RXCRCERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXCRCERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXALIGNCODEERRORS */ + +#define EMAC_RXALIGNCODEERRORS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXALIGNCODEERRORS_COUNT_SHIFT ( 0x00000000U ) + +/* RXOVERSIZED */ + +#define EMAC_RXOVERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOVERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXJABBER */ + +#define EMAC_RXJABBER_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXJABBER_COUNT_SHIFT ( 0x00000000U ) + +/* RXUNDERSIZED */ + +#define EMAC_RXUNDERSIZED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXUNDERSIZED_COUNT_SHIFT ( 0x00000000U ) + +/* RXFRAGMENTS */ + +#define EMAC_RXFRAGMENTS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFRAGMENTS_COUNT_SHIFT ( 0x00000000U ) + +/* RXFILTERED */ + +#define EMAC_RXFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXQOSFILTERED */ + +#define EMAC_RXQOSFILTERED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXQOSFILTERED_COUNT_SHIFT ( 0x00000000U ) + +/* RXOCTETS */ + +#define EMAC_RXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* TXGOODFRAMES */ + +#define EMAC_TXGOODFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXGOODFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXBCASTFRAMES */ + +#define EMAC_TXBCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXBCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXMCASTFRAMES */ + +#define EMAC_TXMCASTFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMCASTFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXPAUSEFRAMES */ + +#define EMAC_TXPAUSEFRAMES_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXPAUSEFRAMES_COUNT_SHIFT ( 0x00000000U ) + +/* TXDEFERRED */ + +#define EMAC_TXDEFERRED_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXDEFERRED_COUNT_SHIFT ( 0x00000000U ) + +/* TXCOLLISION */ + +#define EMAC_TXCOLLISION_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCOLLISION_COUNT_SHIFT ( 0x00000000U ) + +/* TXSINGLECOLL */ + +#define EMAC_TXSINGLECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXSINGLECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXMULTICOLL */ + +#define EMAC_TXMULTICOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXMULTICOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXEXCESSIVECOLL */ + +#define EMAC_TXEXCESSIVECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXEXCESSIVECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXLATECOLL */ + +#define EMAC_TXLATECOLL_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXLATECOLL_COUNT_SHIFT ( 0x00000000U ) + +/* TXUNDERRUN */ + +#define EMAC_TXUNDERRUN_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXUNDERRUN_COUNT_SHIFT ( 0x00000000U ) + +/* TXCARRIERSENSE */ + +#define EMAC_TXCARRIERSENSE_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXCARRIERSENSE_COUNT_SHIFT ( 0x00000000U ) + +/* TXOCTETS */ + +#define EMAC_TXOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_TXOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME64 */ + +#define EMAC_FRAME64_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME64_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME65T127 */ + +#define EMAC_FRAME65T127_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME65T127_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME128T255 */ + +#define EMAC_FRAME128T255_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME128T255_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME256T511 */ + +#define EMAC_FRAME256T511_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME256T511_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME512T1023 */ + +#define EMAC_FRAME512T1023_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME512T1023_COUNT_SHIFT ( 0x00000000U ) + +/* FRAME1024TUP */ + +#define EMAC_FRAME1024TUP_COUNT ( 0xFFFFFFFFU ) +#define EMAC_FRAME1024TUP_COUNT_SHIFT ( 0x00000000U ) + +/* NETOCTETS */ + +#define EMAC_NETOCTETS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_NETOCTETS_COUNT_SHIFT ( 0x00000000U ) + +/* RXSOFOVERRUNS */ + +#define EMAC_RXSOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXSOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXMOFOVERRUNS */ + +#define EMAC_RXMOFOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXMOFOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* RXDMAOVERRUNS */ + +#define EMAC_RXDMAOVERRUNS_COUNT ( 0xFFFFFFFFU ) +#define EMAC_RXDMAOVERRUNS_COUNT_SHIFT ( 0x00000000U ) + +/* MACADDRLO */ + +#define EMAC_MACADDRLO_VALID ( 0x00100000U ) +#define EMAC_MACADDRLO_VALID_SHIFT ( 0x00000014U ) +#define EMAC_MACADDRLO_MATCHFILT ( 0x00080000U ) +#define EMAC_MACADDRLO_MATCHFILT_SHIFT ( 0x00000013U ) +#define EMAC_MACADDRLO_CHANNEL ( 0x00070000U ) +#define EMAC_MACADDRLO_CHANNEL_SHIFT ( 0x00000010U ) +#define EMAC_MACADDRLO_MACADDR0 ( 0x0000FF00U ) +#define EMAC_MACADDRLO_MACADDR0_SHIFT ( 0x00000008U ) +#define EMAC_MACADDRLO_MACADDR1 ( 0x000000FFU ) +#define EMAC_MACADDRLO_MACADDR1_SHIFT ( 0x00000000U ) + +/* MACADDRHI */ + +#define EMAC_MACADDRHI_MACADDR2 ( 0xFF000000U ) +#define EMAC_MACADDRHI_MACADDR2_SHIFT ( 0x00000018U ) + +#define EMAC_MACADDRHI_MACADDR3 ( 0x00FF0000U ) +#define EMAC_MACADDRHI_MACADDR3_SHIFT ( 0x00000010U ) + +#define EMAC_MACADDRHI_MACADDR4 ( 0x0000FF00U ) +#define EMAC_MACADDRHI_MACADDR4_SHIFT ( 0x00000008U ) + +#define EMAC_MACADDRHI_MACADDR5 ( 0x000000FFU ) +#define EMAC_MACADDRHI_MACADDR5_SHIFT ( 0x00000000U ) + +/* MACINDEX */ + +#define EMAC_MACINDEX_MACINDEX ( 0x0000001FU ) +#define EMAC_MACINDEX_MACINDEX_SHIFT ( 0x00000000U ) + +/* TX0HDP */ + +#define EMAC_TX0HDP_TX0HDP ( 0xFFFFFFFFU ) +#define EMAC_TX0HDP_TX0HDP_SHIFT ( 0x00000000U ) + +/* TX1HDP */ + +#define EMAC_TX1HDP_TX1HDP ( 0xFFFFFFFFU ) +#define EMAC_TX1HDP_TX1HDP_SHIFT ( 0x00000000U ) + +/* TX2HDP */ + +#define EMAC_TX2HDP_TX2HDP ( 0xFFFFFFFFU ) +#define EMAC_TX2HDP_TX2HDP_SHIFT ( 0x00000000U ) + +/* TX3HDP */ + +#define EMAC_TX3HDP_TX3HDP ( 0xFFFFFFFFU ) +#define EMAC_TX3HDP_TX3HDP_SHIFT ( 0x00000000U ) + +/* TX4HDP */ + +#define EMAC_TX4HDP_TX4HDP ( 0xFFFFFFFFU ) +#define EMAC_TX4HDP_TX4HDP_SHIFT ( 0x00000000U ) + +/* TX5HDP */ + +#define EMAC_TX5HDP_TX5HDP ( 0xFFFFFFFFU ) +#define EMAC_TX5HDP_TX5HDP_SHIFT ( 0x00000000U ) + +/* TX6HDP */ + +#define EMAC_TX6HDP_TX6HDP ( 0xFFFFFFFFU ) +#define EMAC_TX6HDP_TX6HDP_SHIFT ( 0x00000000U ) + +/* TX7HDP */ + +#define EMAC_TX7HDP_TX7HDP ( 0xFFFFFFFFU ) +#define EMAC_TX7HDP_TX7HDP_SHIFT ( 0x00000000U ) + +/* RX0HDP */ + +#define EMAC_RX0HDP_RX0HDP ( 0xFFFFFFFFU ) +#define EMAC_RX0HDP_RX0HDP_SHIFT ( 0x00000000U ) + +/* RX1HDP */ + +#define EMAC_RX1HDP_RX1HDP ( 0xFFFFFFFFU ) +#define EMAC_RX1HDP_RX1HDP_SHIFT ( 0x00000000U ) + +/* RX2HDP */ + +#define EMAC_RX2HDP_RX2HDP ( 0xFFFFFFFFU ) +#define EMAC_RX2HDP_RX2HDP_SHIFT ( 0x00000000U ) + +/* RX3HDP */ + +#define EMAC_RX3HDP_RX3HDP ( 0xFFFFFFFFU ) +#define EMAC_RX3HDP_RX3HDP_SHIFT ( 0x00000000U ) + +/* RX4HDP */ + +#define EMAC_RX4HDP_RX4HDP ( 0xFFFFFFFFU ) +#define EMAC_RX4HDP_RX4HDP_SHIFT ( 0x00000000U ) + +/* RX5HDP */ + +#define EMAC_RX5HDP_RX5HDP ( 0xFFFFFFFFU ) +#define EMAC_RX5HDP_RX5HDP_SHIFT ( 0x00000000U ) + +/* RX6HDP */ + +#define EMAC_RX6HDP_RX6HDP ( 0xFFFFFFFFU ) +#define EMAC_RX6HDP_RX6HDP_SHIFT ( 0x00000000U ) + +/* RX7HDP */ + +#define EMAC_RX7HDP_RX7HDP ( 0xFFFFFFFFU ) +#define EMAC_RX7HDP_RX7HDP_SHIFT ( 0x00000000U ) + +/* TX0CP */ + +#define EMAC_TX0CP_TX0CP ( 0xFFFFFFFFU ) +#define EMAC_TX0CP_TX0CP_SHIFT ( 0x00000000U ) + +/* TX1CP */ + +#define EMAC_TX1CP_TX1CP ( 0xFFFFFFFFU ) +#define EMAC_TX1CP_TX1CP_SHIFT ( 0x00000000U ) + +/* TX2CP */ + +#define EMAC_TX2CP_TX2CP ( 0xFFFFFFFFU ) +#define EMAC_TX2CP_TX2CP_SHIFT ( 0x00000000U ) + +/* TX3CP */ + +#define EMAC_TX3CP_TX3CP ( 0xFFFFFFFFU ) +#define EMAC_TX3CP_TX3CP_SHIFT ( 0x00000000U ) + +/* TX4CP */ + +#define EMAC_TX4CP_TX4CP ( 0xFFFFFFFFU ) +#define EMAC_TX4CP_TX4CP_SHIFT ( 0x00000000U ) + +/* TX5CP */ + +#define EMAC_TX5CP_TX5CP ( 0xFFFFFFFFU ) +#define EMAC_TX5CP_TX5CP_SHIFT ( 0x00000000U ) + +/* TX6CP */ + +#define EMAC_TX6CP_TX6CP ( 0xFFFFFFFFU ) +#define EMAC_TX6CP_TX6CP_SHIFT ( 0x00000000U ) + +/* TX7CP */ + +#define EMAC_TX7CP_TX7CP ( 0xFFFFFFFFU ) +#define EMAC_TX7CP_TX7CP_SHIFT ( 0x00000000U ) + +/* RX0CP */ + +#define EMAC_RX0CP_RX0CP ( 0xFFFFFFFFU ) +#define EMAC_RX0CP_RX0CP_SHIFT ( 0x00000000U ) + +/* RX1CP */ + +#define EMAC_RX1CP_RX1CP ( 0xFFFFFFFFU ) +#define EMAC_RX1CP_RX1CP_SHIFT ( 0x00000000U ) + +/* RX2CP */ + +#define EMAC_RX2CP_RX2CP ( 0xFFFFFFFFU ) +#define EMAC_RX2CP_RX2CP_SHIFT ( 0x00000000U ) + +/* RX3CP */ + +#define EMAC_RX3CP_RX3CP ( 0xFFFFFFFFU ) +#define EMAC_RX3CP_RX3CP_SHIFT ( 0x00000000U ) + +/* RX4CP */ + +#define EMAC_RX4CP_RX4CP ( 0xFFFFFFFFU ) +#define EMAC_RX4CP_RX4CP_SHIFT ( 0x00000000U ) + +/* RX5CP */ + +#define EMAC_RX5CP_RX5CP ( 0xFFFFFFFFU ) +#define EMAC_RX5CP_RX5CP_SHIFT ( 0x00000000U ) + +/* RX6CP */ + +#define EMAC_RX6CP_RX6CP ( 0xFFFFFFFFU ) +#define EMAC_RX6CP_RX6CP_SHIFT ( 0x00000000U ) + +/* RX7CP */ + +#define EMAC_RX7CP_RX7CP ( 0xFFFFFFFFU ) +#define EMAC_RX7CP_RX7CP_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h new file mode 100644 index 00000000000..764e8f748f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_emac_ctrl.h @@ -0,0 +1,92 @@ +/* + * hw_emac1.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_EMAC_CTRL_H_ +#define _HW_EMAC_CTRL_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define EMAC_CTRL_REVID ( 0x0U ) +#define EMAC_CTRL_SOFTRESET ( 0x4U ) +#define EMAC_CTRL_INTCONTROL ( 0xCU ) +#define EMAC_CTRL_C0RXTHRESHEN ( 0x10U ) +#define EMAC_CTRL_CnRXEN( n ) ( ( uint32 ) 0x14u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnTXEN( n ) ( ( uint32 ) 0x18u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnMISCEN( n ) \ + ( ( uint32 ) 0x1Cu + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_CnRXTHRESHEN( n ) \ + ( ( uint32 ) 0x20u + ( uint32 ) ( ( uint32 ) ( n ) << 4 ) ) +#define EMAC_CTRL_C0RXTHRESHSTAT ( 0x40U ) +#define EMAC_CTRL_C0RXSTAT ( 0x44U ) +#define EMAC_CTRL_C0TXSTAT ( 0x48U ) +#define EMAC_CTRL_C0MISCSTAT ( 0x4CU ) +#define EMAC_CTRL_C1RXTHRESHSTAT ( 0x50U ) +#define EMAC_CTRL_C1RXSTAT ( 0x54U ) +#define EMAC_CTRL_C1TXSTAT ( 0x58U ) +#define EMAC_CTRL_C1MISCSTAT ( 0x5CU ) +#define EMAC_CTRL_C2RXTHRESHSTAT ( 0x60U ) +#define EMAC_CTRL_C2RXSTAT ( 0x64U ) +#define EMAC_CTRL_C2TXSTAT ( 0x68U ) +#define EMAC_CTRL_C2MISCSTAT ( 0x6CU ) +#define EMAC_CTRL_C0RXIMAX ( 0x70U ) +#define EMAC_CTRL_C0TXIMAX ( 0x74U ) +#define EMAC_CTRL_C1RXIMAX ( 0x78U ) +#define EMAC_CTRL_C1TXIMAX ( 0x7CU ) +#define EMAC_CTRL_C2RXIMAX ( 0x80U ) +#define EMAC_CTRL_C2TXIMAX ( 0x84U ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h new file mode 100644 index 00000000000..d12203353d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_mdio.h @@ -0,0 +1,235 @@ +/* + * hw_mdio.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_MDIO_H_ +#define _HW_MDIO_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#define MDIO_BASE ( 0xFCF78900U ) + +#define MDIO_REVID ( 0x0U ) +#define MDIO_CONTROL ( 0x4U ) +#define MDIO_ALIVE ( 0x8U ) +#define MDIO_LINK ( 0xCU ) +#define MDIO_LINKINTRAW ( 0x10U ) +#define MDIO_LINKINTMASKED ( 0x14U ) +#define MDIO_USERINTRAW ( 0x20U ) +#define MDIO_USERINTMASKED ( 0x24U ) +#define MDIO_USERINTMASKSET ( 0x28U ) +#define MDIO_USERINTMASKCLEAR ( 0x2CU ) +#define MDIO_USERACCESS0 ( 0x80U ) +#define MDIO_USERPHYSEL0 ( 0x84U ) +#define MDIO_USERACCESS1 ( 0x88U ) +#define MDIO_USERPHYSEL1 ( 0x8CU ) + +/**************************************************************************\ +* Field Definition Macros +\**************************************************************************/ + +/* REVID */ + +#define MDIO_REVID_REV ( 0xFFFFFFFFU ) +#define MDIO_REVID_REV_SHIFT ( 0x00000000U ) + +/* CONTROL */ + +#define MDIO_CONTROL_IDLE ( 0x80000000U ) +#define MDIO_CONTROL_IDLE_SHIFT ( 0x0000001FU ) +/*----IDLE Tokens----*/ +#define MDIO_CONTROL_IDLE_NO ( 0x00000000U ) +#define MDIO_CONTROL_IDLE_YES ( 0x00000001U ) + +#define MDIO_CONTROL_ENABLE ( 0x40000000U ) +#define MDIO_CONTROL_ENABLE_SHIFT ( 0x0000001EU ) + +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL ( 0x1F000000U ) +#define MDIO_CONTROL_HIGHEST_USER_CHANNEL_SHIFT ( 0x00000018U ) + +#define MDIO_CONTROL_PREAMBLE ( 0x00100000U ) +#define MDIO_CONTROL_PREAMBLE_SHIFT ( 0x00000014U ) +/*----PREAMBLE Tokens----*/ + +#define MDIO_CONTROL_FAULT ( 0x00080000U ) +#define MDIO_CONTROL_FAULT_SHIFT ( 0x00000013U ) + +#define MDIO_CONTROL_FAULTENB ( 0x00040000U ) +#define MDIO_CONTROL_FAULTENB_SHIFT ( 0x00000012U ) +/*----FAULTENB Tokens----*/ + +#define MDIO_CONTROL_CLKDIV ( 0x0000FFFFU ) +#define MDIO_CONTROL_CLKDIV_SHIFT ( 0x00000000U ) +/*----CLKDIV Tokens----*/ + +/* ALIVE */ + +#define MDIO_ALIVE_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_ALIVE_REGVAL_SHIFT ( 0x00000000U ) + +/* LINK */ + +#define MDIO_LINK_REGVAL ( 0xFFFFFFFFU ) +#define MDIO_LINK_REGVAL_SHIFT ( 0x00000000U ) + +/* LINKINTRAW */ + +#define MDIO_LINKINTRAW_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTRAW_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTRAW_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTRAW_USERPHY0_SHIFT ( 0x00000000U ) + +/* LINKINTMASKED */ + +#define MDIO_LINKINTMASKED_USERPHY1 ( 0x00000002U ) +#define MDIO_LINKINTMASKED_USERPHY1_SHIFT ( 0x00000001U ) + +#define MDIO_LINKINTMASKED_USERPHY0 ( 0x00000001U ) +#define MDIO_LINKINTMASKED_USERPHY0_SHIFT ( 0x00000000U ) + +/* USERINTRAW */ + +#define MDIO_USERINTRAW_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTRAW_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTRAW_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTRAW_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKED */ + +#define MDIO_USERINTMASKED_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKED_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKED_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKED_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKSET */ + +#define MDIO_USERINTMASKSET_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKSET_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKSET_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKSET_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERINTMASKCLEAR */ + +#define MDIO_USERINTMASKCLEAR_USERACCESS1 ( 0x00000002U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS1_SHIFT ( 0x00000001U ) + +#define MDIO_USERINTMASKCLEAR_USERACCESS0 ( 0x00000001U ) +#define MDIO_USERINTMASKCLEAR_USERACCESS0_SHIFT ( 0x00000000U ) + +/* USERACCESS0 */ + +#define MDIO_USERACCESS0_GO ( 0x80000000U ) +#define MDIO_USERACCESS0_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS0_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS0_READ ( 0x00000000U ) +#define MDIO_USERACCESS0_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS0_ACK ( 0x20000000U ) +#define MDIO_USERACCESS0_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS0_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS0_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS0_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS0_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS0_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS0_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL0 */ + +#define MDIO_USERPHYSEL0_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL0_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL0_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL0_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL0_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL0_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USERACCESS1 */ + +#define MDIO_USERACCESS1_GO ( 0x80000000U ) +#define MDIO_USERACCESS1_GO_SHIFT ( 0x0000001FU ) + +#define MDIO_USERACCESS1_WRITE ( 0x40000000U ) +#define MDIO_USERACCESS1_WRITE_SHIFT ( 0x0000001EU ) + +#define MDIO_USERACCESS1_ACK ( 0x20000000U ) +#define MDIO_USERACCESS1_ACK_SHIFT ( 0x0000001DU ) + +#define MDIO_USERACCESS1_REGADR ( 0x03E00000U ) +#define MDIO_USERACCESS1_REGADR_SHIFT ( 0x00000015U ) + +#define MDIO_USERACCESS1_PHYADR ( 0x001F0000U ) +#define MDIO_USERACCESS1_PHYADR_SHIFT ( 0x00000010U ) + +#define MDIO_USERACCESS1_DATA ( 0x0000FFFFU ) +#define MDIO_USERACCESS1_DATA_SHIFT ( 0x00000000U ) + +/* USERPHYSEL1 */ + +#define MDIO_USERPHYSEL1_LINKSEL ( 0x00000080U ) +#define MDIO_USERPHYSEL1_LINKSEL_SHIFT ( 0x00000007U ) + +#define MDIO_USERPHYSEL1_LINKINTENB ( 0x00000040U ) +#define MDIO_USERPHYSEL1_LINKINTENB_SHIFT ( 0x00000006U ) + +#define MDIO_USERPHYSEL1_PHYADRMON ( 0x0000001FU ) +#define MDIO_USERPHYSEL1_PHYADRMON_SHIFT ( 0x00000000U ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h new file mode 100644 index 00000000000..f1417768169 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/hw_reg_access.h @@ -0,0 +1,80 @@ +/* + * hw_reg_access.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _HW_REG_ACCESS_H_ +#define _HW_REG_ACCESS_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * + * Macros for hardware access, both direct and via the bit-band region. + * + *****************************************************************************/ +#define HWREG( x ) ( *( ( volatile uint32 * ) ( x ) ) ) +#define HWREGH( x ) ( *( ( volatile uint16 * ) ( x ) ) ) +#define HWREGB( x ) ( *( ( volatile uint8 * ) ( x ) ) ) +#define HWREGBITW( x, b ) \ + ( HWREG( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITH( x, b ) \ + ( HWREGH( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) +#define HWREGBITB( x, b ) \ + ( HWREGB( ( ( uint32 ) ( x ) & 0xF0000000U ) | ( uint32 ) 0x02000000U \ + | ( ( ( uint32 ) ( x ) & 0x000FFFFFU ) << 5U ) \ + | ( uint32 ) ( ( uint32 ) ( b ) << 2U ) ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HW_TYPES_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h new file mode 100644 index 00000000000..5cb77563052 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/i2c.h @@ -0,0 +1,290 @@ +/** @file I2C.h + * @brief I2C Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __I2C_H__ +#define __I2C_H__ + +#include "reg_i2c.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum i2cMode + * @brief Alias names for i2c modes + * This enumeration is used to provide alias names for I2C modes: + */ +enum i2cMode +{ + I2C_FD_FORMAT = 0x0008U, /* Free Data Format */ + I2C_START_BYTE = 0x0010U, + I2C_RESET_OUT = 0x0020U, + I2C_RESET_IN = 0x0000U, + I2C_DLOOPBACK = 0x0040U, + I2C_REPEATMODE = 0x0080U, /* In Master Mode only */ + I2C_10BIT_AMODE = 0x0100U, + I2C_7BIT_AMODE = 0x0000U, + I2C_TRANSMITTER = 0x0200U, + I2C_RECEIVER = 0x0000U, + I2C_MASTER = 0x0400U, + I2C_SLAVE = 0x0000U, + I2C_STOP_COND = 0x0800U, /* In Master Mode only */ + I2C_START_COND = 0x2000U, /* In Master Mode only */ + I2C_FREE_RUN = 0x4000U, + I2C_NACK_MODE = 0x8000U +}; + +/** @enum i2cBitCount + * @brief Alias names for i2c bit count + * This enumeration is used to provide alias names for I2C bit count: + */ +enum i2cBitCount +{ + I2C_2_BIT = 0x2U, + I2C_3_BIT = 0x3U, + I2C_4_BIT = 0x4U, + I2C_5_BIT = 0x5U, + I2C_6_BIT = 0x6U, + I2C_7_BIT = 0x7U, + I2C_8_BIT = 0x0U +}; + +/** @enum i2cIntFlags + * @brief Interrupt Flag Definitions + * + * Used with I2CEnableNotification, I2CDisableNotification + */ +enum i2cIntFlags +{ + I2C_AL_INT = 0x0001U, /* arbitration lost */ + I2C_NACK_INT = 0x0002U, /* no acknowledgment */ + I2C_ARDY_INT = 0x0004U, /* access ready */ + I2C_RX_INT = 0x0008U, /* receive data ready */ + I2C_TX_INT = 0x0010U, /* transmit data ready */ + I2C_SCD_INT = 0x0020U, /* stop condition detect */ + I2C_AAS_INT = 0x0040U /* address as slave */ +}; + +/** @enum i2cStatFlags + * @brief Interrupt Status Definitions + * + */ +enum i2cStatFlags +{ + I2C_AL = 0x0001U, /* arbitration lost */ + I2C_NACK = 0x0002U, /* no acknowledgement */ + I2C_ARDY = 0x0004U, /* access ready */ + I2C_RX = 0x0008U, /* receive data ready */ + I2C_TX = 0x0010U, /* transmit data ready */ + I2C_SCD = 0x0020U, /* stop condition detect */ + I2C_AD0 = 0x0100U, /* address Zero Status */ + I2C_AAS = 0x0200U, /* address as slave */ + I2C_XSMT = 0x0400U, /* Transmit shift empty not */ + I2C_RXFULL = 0x0800U, /* receive full */ + I2C_BUSBUSY = 0x1000U, /* bus busy */ + I2C_NACKSNT = 0x2000U, /* No Ack Sent */ + I2C_SDIR = 0x4000U /* Slave Direction */ +}; + +/** @enum i2cDMA + * @brief I2C DMA definitions + * + * Used before i2c transfer + */ +enum i2cDMA +{ + I2C_TXDMA = 0x20U, + I2C_RXDMA = 0x10U +}; + +/* Configuration registers */ +typedef struct i2c_config_reg +{ + uint32 CONFIG_OAR; + uint32 CONFIG_IMR; + uint32 CONFIG_CLKL; + uint32 CONFIG_CLKH; + uint32 CONFIG_CNT; + uint32 CONFIG_SAR; + uint32 CONFIG_MDR; + uint32 CONFIG_EMDR; + uint32 CONFIG_PSC; + uint32 CONFIG_DMAC; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; +} i2c_config_reg_t; + +/* Configuration registers initial value for I2C*/ +#define I2C1_OAR_CONFIGVALUE 0x00000000U +#define I2C1_IMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( ( uint32 ) 0U ) ) + +#define I2C1_CLKL_CONFIGVALUE 37U +#define I2C1_CLKH_CONFIGVALUE 37U +#define I2C1_CNT_CONFIGVALUE 8U +#define I2C1_SAR_CONFIGVALUE 0x000003FFU +#define I2C1_MDR_CONFIGVALUE \ + ( 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( ( uint32 ) I2C_TRANSMITTER ) \ + | ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \ + | ( ( uint32 ) 0U ) | ( ( uint32 ) I2C_8_BIT ) | ( uint32 ) I2C_RESET_OUT ) + +#define I2C1_EMDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PSC_CONFIGVALUE 8U +#define I2C1_DMAC_CONFIGVALUE 0x00000000U +#define I2C1_FUN_CONFIGVALUE 0U +#define I2C1_DIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_ODR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PD_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C1_PSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) ) + +/* Configuration registers initial value for I2C*/ +#define I2C2_OAR_CONFIGVALUE 0x00000000U +#define I2C2_IMR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( ( uint32 ) 0U ) ) + +#define I2C2_CLKL_CONFIGVALUE 37U +#define I2C2_CLKH_CONFIGVALUE 37U +#define I2C2_CNT_CONFIGVALUE 8U +#define I2C2_SAR_CONFIGVALUE 0x000003FFU +#define I2C2_MDR_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 1U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) \ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) | ( uint32 ) ( ( uint32 ) 0 << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) | ( uint32 ) ( ( uint32 ) I2C_2_BIT ) \ + | ( uint32 ) I2C_RESET_OUT ) + +#define I2C2_EMDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PSC_CONFIGVALUE 8U +#define I2C2_DMAC_CONFIGVALUE 0x00000000U +#define I2C2_FUN_CONFIGVALUE 0U +#define I2C2_DIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_ODR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PD_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) +#define I2C2_PSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 1U ) | ( uint32 ) ( ( uint32 ) 1U ) ) + +/** + * @defgroup I2C I2C + * @brief Inter-Integrated Circuit Module. + * + * The I2C is a multi-master communication module providing an interface between the + * Texas Instruments (TI) microcontroller and devices compliant with Philips Semiconductor + * I2C-bus specification version 2.1 and connected by an I2Cbus. This module will support + * any slave or master I2C compatible device. + * + * Related Files + * - reg_i2c.h + * - i2c.h + * - i2c.c + * @addtogroup I2C + * @{ + */ + +/* I2C Interface Functions */ +void i2cInit( void ); +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ); +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ); +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ); +uint32 i2cIsTxReady( i2cBASE_t * i2c ); +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ); +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ); +uint32 i2cIsRxReady( i2cBASE_t * i2c ); +uint32 i2cIsStopDetected( i2cBASE_t * i2c ); +void i2cClearSCD( i2cBASE_t * i2c ); +uint32 i2cRxError( i2cBASE_t * i2c ); +uint8 i2cReceiveByte( i2cBASE_t * i2c ); +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ); +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ); +void i2cSetStart( i2cBASE_t * i2c ); +void i2cSetStop( i2cBASE_t * i2c ); +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ); +void i2cEnableLoopback( i2cBASE_t * i2c ); +void i2cDisableLoopback( i2cBASE_t * i2c ); +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ); +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ); +bool i2cIsMasterReady( i2cBASE_t * i2c ); +bool i2cIsBusBusy( i2cBASE_t * i2c ); +void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); +void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void i2cNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Interrupt callback + * @param[in] i2c - I2C module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h new file mode 100644 index 00000000000..36d037b8fe3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/lin.h @@ -0,0 +1,317 @@ +/** @file lin.h + * @brief LIN Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __LIN_H__ +#define __LIN_H__ + +#include "reg_lin.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def LIN_BREAK_INT + * @brief Alias for break detect interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BREAK_INT 0x00000001U + +/** @def LIN_WAKEUP_INT + * @brief Alias for wakeup interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_WAKEUP_INT 0x00000002U + +/** @def LIN_TO_INT + * @brief Alias for time out interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TO_INT 0x00000010U + +/** @def LIN_TOAWUS_INT + * @brief Alias for time out after wakeup signal interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOAWUS_INT 0x00000040U + +/** @def LIN_TOA3WUS_INT + * @brief Alias for time out after 3 wakeup signals interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_TOA3WUS_INT 0x00000080U + +/** @def LIN_TX_READY + * @brief Alias for transmit buffer ready flag + * + * Used with linIsTxReady. + */ +#define LIN_TX_READY 0x00000100U + +/** @def LIN_RX_INT + * @brief Alias for receive buffer ready interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_RX_INT 0x00000200U + +/** @def LIN_ID_INT + * @brief Alias for received matching identifier interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ID_INT 0x00002000U + +/** @def LIN_PE_INT + * @brief Alias for parity error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PE_INT 0x01000000U + +/** @def LIN_OE_INT + * @brief Alias for overrun error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_OE_INT 0x02000000U + +/** @def LIN_FE_INT + * @brief Alias for framing error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_FE_INT 0x04000000U + +/** @def LIN_NRE_INT + * @brief Alias for no response error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_NRE_INT 0x08000000U + +/** @def LIN_ISFE_INT + * @brief Alias for inconsistent sync field error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_ISFE_INT 0x10000000U + +/** @def LIN_CE_INT + * @brief Alias for checksum error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_CE_INT 0x20000000U + +/** @def LIN_PBE_INT + * @brief Alias for physical bus error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_PBE_INT 0x40000000U + +/** @def LIN_BE_INT + * @brief Alias for bit error interrupt flag + * + * Used with linEnableNotification, linDisableNotification. + */ +#define LIN_BE_INT 0x80000000U + +/** @struct linBase + * @brief LIN Register Definition + * + * This structure is used to access the LIN module registers. + */ +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +enum linPinSelect +{ + PIN_LIN_TX = 4U, + PIN_LIN_RX = 2U +}; + +/* Configuration registers */ +typedef struct lin_config_reg +{ + uint32 CONFIG_GCR0; + uint32 CONFIG_GCR1; + uint32 CONFIG_GCR2; + uint32 CONFIG_SETINT; + uint32 CONFIG_SETINTLVL; + uint32 CONFIG_FORMAT; + uint32 CONFIG_BRSR; + uint32 CONFIG_FUN; + uint32 CONFIG_DIR; + uint32 CONFIG_ODR; + uint32 CONFIG_PD; + uint32 CONFIG_PSL; + uint32 CONFIG_COMP; + uint32 CONFIG_MASK; + uint32 CONFIG_MBRSR; +} lin_config_reg_t; + +/* Configuration registers initial value for LIN*/ +#define LIN1_GCR0_CONFIGVALUE 0x00000001U +#define LIN1_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN1_GCR2_CONFIGVALUE 0x00000000U +#define LIN1_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN1_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN1_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN1_BRSR_CONFIGVALUE ( 233U ) +#define LIN1_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN1_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN1_MBRSR_CONFIGVALUE ( 3370U ) +#define LIN1_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN1_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN1_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/* Configuration registers initial value for LIN*/ +#define LIN2_GCR0_CONFIGVALUE 0x00000001U +#define LIN2_GCR1_CONFIGVALUE \ + ( 0x03000CC0U | ( uint32 ) ( ( uint32 ) 1U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) ) +#define LIN2_GCR2_CONFIGVALUE 0x00000000U +#define LIN2_SETINTLVL_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN2_SETINT_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U ) + +#define LIN2_FORMAT_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) ) +#define LIN2_BRSR_CONFIGVALUE ( 233U ) +#define LIN2_COMP_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) | ( 13U - 13U ) ) +#define LIN2_MASK_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | 0xFFU ) +#define LIN2_MBRSR_CONFIGVALUE ( 3370U ) +#define LIN2_FUN_CONFIGVALUE ( 4U | 2U | 0U ) +#define LIN2_DIR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_ODR_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_PD_CONFIGVALUE ( 0U | 0U | 0U ) +#define LIN2_PSL_CONFIGVALUE ( 4U | 2U | 1U ) + +/** + * @defgroup LIN LIN + * @brief Local Interconnect Network Module. + * + * The LIN standard is based on the SCI (UART) serial data link format. The communication + *concept is single-master/multiple-slave with a message identification for multi-cast + *transmission between any network nodes. + * + * Related Files + * - reg_lin.h + * - lin.h + * - lin.c + * @addtogroup LIN + * @{ + */ + +/* LIN Interface Functions */ +void linInit( void ); +void linSetFunctional( linBASE_t * lin, uint32 port ); +void linSendHeader( linBASE_t * lin, uint8 identifier ); +void linSendWakupSignal( linBASE_t * lin ); +void linEnterSleep( linBASE_t * lin ); +void linSoftwareReset( linBASE_t * lin ); +uint32 linIsTxReady( linBASE_t * lin ); +void linSetLength( linBASE_t * lin, uint32 length ); +void linSend( linBASE_t * lin, uint8 * data ); +uint32 linIsRxReady( linBASE_t * lin ); +uint32 linTxRxError( linBASE_t * lin ); +uint32 linGetIdentifier( linBASE_t * lin ); +void linGetData( linBASE_t * lin, uint8 * const data ); +void linEnableNotification( linBASE_t * lin, uint32 flags ); +void linDisableNotification( linBASE_t * lin, uint32 flags ); +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ); +void linDisableLoopback( linBASE_t * lin ); +void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ); +uint32 linGetStatusFlag( linBASE_t * lin ); +void linClearStatusFlag( linBASE_t * lin, uint32 flags ); + +/** @fn void linNotification(linBASE_t *lin, uint32 flags) + * @brief Interrupt callback + * @param[in] lin - lin module base address + * @param[in] flags - copy of error interrupt flags + * + * This is a callback that is provided by the application and is called upon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void linNotification( linBASE_t * lin, uint32 flags ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h new file mode 100644 index 00000000000..f936f915c91 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mdio.h @@ -0,0 +1,94 @@ +/** + * \file mdio.h + * + * \brief MDIO APIs and macros. + * + * This file contains the driver API prototypes and macro definitions. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MDIO_H__ +#define __MDIO_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "system.h" +#include "hw_mdio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* MDIO input and output frequencies in Hz */ +#define MDIO_FREQ_INPUT ( ( uint32 ) ( VCLK3_FREQ * 1000000.00F ) ) +#define MDIO_FREQ_OUTPUT 1000000U +/*****************************************************************************/ + +/** + * @addtogroup EMACMDIO + * @{ + */ +/* +** Prototypes for the APIs +*/ +extern uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ); +extern uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ); +extern void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ); +extern boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ); +extern void MDIOPhyRegWrite( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + uint16 RegVal ); +extern void MDIOEnable( uint32 baseAddr ); +extern void MDIODisable( uint32 baseAddr ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* __MDIO_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h new file mode 100644 index 00000000000..71d7b98f224 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/mibspi.h @@ -0,0 +1,885 @@ +/** @file mibspi.h + * @brief MIBSPI Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __MIBSPI_H__ +#define __MIBSPI_H__ + +#include "reg_mibspi.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum triggerEvent + * @brief Transfer Group Trigger Event + */ +enum triggerEvent +{ + TRG_NEVER = 0U, + TRG_RISING = 1U, + TRG_FALLING = 2U, + TRG_BOTH = 3U, + TRG_HIGH = 5U, + TRG_LOW = 6U, + TRG_ALWAYS = 7U +}; + +/** @enum triggerSource + * @brief Transfer Group Trigger Source + */ +enum triggerSource +{ + TRG_DISABLED, + TRG_GIOA0, + TRG_GIOA1, + TRG_GIOA2, + TRG_GIOA3, + TRG_GIOA4, + TRG_GIOA5, + TRG_GIOA6, + TRG_GIOA7, + TRG_HET1_8, + TRG_HET1_10, + TRG_HET1_12, + TRG_HET1_14, + TRG_HET1_16, + TRG_HET1_18, + TRG_TICK +}; + +/** @enum mibspiPinSelect + * @brief mibspi Pin Select + */ +enum mibspiPinSelect +{ + PIN_CS0 = 0U, + PIN_CS1 = 1U, + PIN_CS2 = 2U, + PIN_CS3 = 3U, + PIN_CS4 = 4U, + PIN_CS5 = 5U, + PIN_CS6 = 6U, + PIN_CS7 = 7U, + PIN_ENA = 8U, + PIN_CLK = 9U, + PIN_SIMO = 10U, + PIN_SOMI = 11U, + PIN_SIMO_1 = 17U, + PIN_SIMO_2 = 18U, + PIN_SIMO_3 = 19U, + PIN_SIMO_4 = 20U, + PIN_SIMO_5 = 21U, + PIN_SIMO_6 = 22U, + PIN_SIMO_7 = 23U, + PIN_SOMI_1 = 25U, + PIN_SOMI_2 = 26U, + PIN_SOMI_3 = 27U, + PIN_SOMI_4 = 28U, + PIN_SOMI_5 = 29U, + PIN_SOMI_6 = 30U, + PIN_SOMI_7 = 31U +}; + +/** @enum chipSelect + * @brief Transfer Group Chip Select + */ +enum chipSelect +{ + CS_NONE = 0xFFU, + CS_0 = 0xFEU, + CS_1 = 0xFDU, + CS_2 = 0xFBU, + CS_3 = 0xF7U, + CS_4 = 0xEFU, + CS_5 = 0xDFU, + CS_6 = 0xBFU, + CS_7 = 0x7FU +}; + +/** @typedef mibspiPmode_t + * @brief Mibspi Parellel mode Type Definition + * + * This type is used to represent Mibspi Parellel mode. + */ +typedef enum mibspiPmode +{ + PMODE_NORMAL = 0x0U, + PMODE_2_DATALINE = 0x1U, + PMODE_4_DATALINE = 0x2U, + PMODE_8_DATALINE = 0x3U +} mibspiPmode_t; + +/** @typedef mibspiDFMT_t + * @brief Mibspi Data format selection Type Definition + * + * This type is used to represent Mibspi Data format selection. + */ +typedef enum mibspiDFMT +{ + DATA_FORMAT0 = 0x0U, + DATA_FORMAT1 = 0x1U, + DATA_FORMAT2 = 0x2U, + DATA_FORMAT3 = 0x3U +} mibspiDFMT_t; + +typedef struct mibspi_config_reg +{ + uint32 CONFIG_GCR1; + uint32 CONFIG_INT0; + uint32 CONFIG_LVL; + uint32 CONFIG_PCFUN; + uint32 CONFIG_PCDIR; + uint32 CONFIG_PCPDR; + uint32 CONFIG_PCDIS; + uint32 CONFIG_PCPSL; + uint32 CONFIG_DELAY; + uint32 CONFIG_FMT0; + uint32 CONFIG_FMT1; + uint32 CONFIG_FMT2; + uint32 CONFIG_FMT3; + uint32 CONFIG_MIBSPIE; + uint32 CONFIG_LTGPEND; + uint32 CONFIG_TGCTRL[ 8U ]; + uint32 CONFIG_PAR_ECC_CTRL; +} mibspi_config_reg_t; + +#define MIBSPI1_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI1_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI1_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) +#define MIBSPI1_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) ) +#define MIBSPI1_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) ) + +#define MIBSPI1_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI1_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI1_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI1_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI1_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI1_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI1_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI1_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI1_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI2_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI2_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) +#define MIBSPI2_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define MIBSPI2_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI2_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI2_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI2_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI2_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI2_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI2_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI2_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI2_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI2_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI2_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI2_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI3_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI3_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI3_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI3_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI3_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI3_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI3_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI3_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI3_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI3_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI3_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI3_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI3_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI3_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI4_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI4_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U ) ) +#define MIBSPI4_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U ) ) + +#define MIBSPI4_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) +#define MIBSPI4_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) ) +#define MIBSPI4_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define MIBSPI4_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI4_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI4_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI4_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI4_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI4_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI4_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI4_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI4_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +#define MIBSPI5_GCR1_CONFIGVALUE ( 0x01000000U | ( uint32 ) ( ( uint32 ) 1U << 1U ) | 1U ) +#define MIBSPI5_INT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) +#define MIBSPI5_LVL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_PCFUN_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) +#define MIBSPI5_PCDIR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPDR_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) ) +#define MIBSPI5_PCPSL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 1U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) 1U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) | ( uint32 ) ( ( uint32 ) 1U << 24U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) | ( uint32 ) ( ( uint32 ) 1U << 18U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) | ( uint32 ) ( ( uint32 ) 1U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) | ( uint32 ) ( ( uint32 ) 1U << 27U ) ) + +#define MIBSPI5_DELAY_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ) ) + +#define MIBSPI5_FMT0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) +#define MIBSPI5_FMT3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 74U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 16U << 0U ) ) + +#define MIBSPI5_MIBSPIE_CONFIGVALUE 0x501U +#define MIBSPI5_LTGPEND_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) << 8U ) ) + +#define MIBSPI5_TGCTRL0_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) ) ) +#define MIBSPI5_TGCTRL1_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) 8U << 8U ) ) ) +#define MIBSPI5_TGCTRL2_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL3_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL4_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL5_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL6_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) +#define MIBSPI5_TGCTRL7_CONFIGVALUE \ + ( ( ( uint32 ) ( ( uint32 ) 1U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) \ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U ) ) ) + +#define MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE ( 0x050A0000U | 0x00000005U ) + +/** + * @defgroup MIBSPI MIBSPI + * @brief Multi-Buffered Serial Peripheral Interface Module. + * + * The MibSPI/MibSPIP is a high-speed synchronous serial input/output port that allows a + *serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the + *device at a programmed bit-transfer rate. The MibSPI has a programmable buffer memory + *that enables programmed transmission to be completed without CPU intervention + * + * Related Files + * - reg_mibspi.h + * - mibspi.h + * - mibspi.c + * @addtogroup MIBSPI + * @{ + */ + +/* MIBSPI Interface Functions */ +void mibspiInit( void ); +boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi ); +void mibspiOutofReset( mibspiBASE_t * mibspi ); +void mibspiReset( mibspiBASE_t * mibspi ); +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ); +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ); +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ); +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ); +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ); +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ); +void mibspiDisableLoopback( mibspiBASE_t * mibspi ); +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ); +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ); + +/** @fn void mibspiNotification(mibspiBASE_t *mibspi, uint32 flags) + * @brief Error interrupt callback + * @param[in] mibspi - mibSpi module base address + * @param[in] flags - Copy of error interrupt flags + * + * This is a error callback that is provided by the application and is call upon + * an error interrupt. The paramer passed to the callback is a copy of the error + * interrupt flag register. + */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ); + +/** @fn void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Transfer complete notification callback + * @param[in] mibspi - mibSpi module base address + * @param[in] group - Transfer group + * + * This is a callback function provided by the application. It is call when + * a transfer is complete. The parameter is the transfer group that triggered + * the interrupt. + */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h new file mode 100644 index 00000000000..47bd39fa1b2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/nmpu.h @@ -0,0 +1,165 @@ +/** @file nmpu.h + * @brief NMPU Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef NMPU_H_ +#define NMPU_H_ + +#include "reg_nmpu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef enum nmpuRegion +{ + NMPU_REGION0 = 0U, + NMPU_REGION1 = 1U, + NMPU_REGION2 = 2U, + NMPU_REGION3 = 3U, + NMPU_REGION4 = 4U, + NMPU_REGION5 = 5U, + NMPU_REGION6 = 6U, + NMPU_REGION7 = 7U +} nmpuReg_t; + +typedef enum nmpuAccessPermission +{ + NMPU_PRIV_NA_USER_NA = 0U, + NMPU_PRIV_RW_USER_NA = 1U, + NMPU_PRIV_RW_USER_RO = 2U, + NMPU_PRIV_RW_USER_RW = 3U, + NMPU_PRIV_RO_USER_NA = 5U, + NMPU_PRIV_RO_USER_RO = 6U +} nmpuAP_t; + +typedef enum nmpuRegionSize +{ + NMPU_SIZE_32_BYTES = 0x4U, + NMPU_SIZE_64_BYTES = 0x5U, + NMPU_SIZE_128_BYTES = 0x6U, + NMPU_SIZE_256_BYTES = 0x7U, + NMPU_SIZE_512_BYTES = 0x8U, + NMPU_SIZE_1_KB = 0x9U, + NMPU_SIZE_2_KB = 0xAU, + NMPU_SIZE_4_KB = 0xBU, + NMPU_SIZE_8_KB = 0xCU, + NMPU_SIZE_16_KB = 0xDU, + NMPU_SIZE_32_KB = 0xEU, + NMPU_SIZE_64_KB = 0xFU, + NMPU_SIZE_128_KB = 0x10U, + NMPU_SIZE_256_KB = 0x11U, + NMPU_SIZE_512_KB = 0x12U, + NMPU_SIZE_1_MB = 0x13U, + NMPU_SIZE_2_MB = 0x14U, + NMPU_SIZE_4_MB = 0x15U, + NMPU_SIZE_8_MB = 0x16U, + NMPU_SIZE_16_MB = 0x17U, + NMPU_SIZE_32_MB = 0x18U, + NMPU_SIZE_64_MB = 0x19U, + NMPU_SIZE_128_MB = 0x1AU, + NMPU_SIZE_256_MB = 0x1BU, + NMPU_SIZE_512_MB = 0x1CU, + NMPU_SIZE_1_GB = 0x1DU, + NMPU_SIZE_2_GB = 0x1EU, + NMPU_SIZE_4_GB = 0x1FU +} nmpuRegionSize_t; + +typedef enum nmpuError +{ + NMPU_ERROR_NONE, + NMPU_ERROR_AP_READ, + NMPU_ERROR_AP_WRITE, + NMPU_ERROR_BG_READ, + NMPU_ERROR_BG_WRITE +} nmpuErr_t; + +typedef struct nmpuRegionAttributes +{ + uint32 baseaddr; + nmpuReg_t regionsize; + nmpuAP_t accesspermission; +} nmpuRegionAttributes_t; + +/** + * @defgroup NMPU NMPU + * @brief System Memory Protection Unit + * + * Related files: + * - reg_nmpu.h + * - sys_nmpu.h + * - sys_nmpu.c + * + * @addtogroup NMPU + * @{ + */ + +void nmpuEnable( nmpuBASE_t * nmpu ); +void nmpuDisable( nmpuBASE_t * nmpu ); +void nmpuEnableErrorGen( nmpuBASE_t * nmpu ); +void nmpuDisableErrorGen( nmpuBASE_t * nmpu ); +boolean nmpuEnableRegion( nmpuBASE_t * nmpu, + nmpuReg_t region, + nmpuRegionAttributes_t config ); +boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region ); +nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu ); +nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu ); +uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu ); +void nmpuClearErrorStatus( nmpuBASE_t * nmpu ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* NMPU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h new file mode 100644 index 00000000000..98d1837da4c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_dp83640.h @@ -0,0 +1,139 @@ +/* + * DP83640.h + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef _PHY_DP83640_H_ +#define _PHY_DP83640_H_ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Dp83640GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define DP83640_PHY_ID ( 0x0007C0F0u ) +#define DP83640_PHY_ID_REV_MASK ( 0x0000000Fu ) + +/* Pause operations */ +#define DP83640_PAUSE_NIL ( 0x0000u ) +#define DP83640_PAUSE_SYM ( 0x0400u ) +#define DP83640_PAUSE_ASYM ( 0x0800u ) +#define DP83640_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define DP83640_100BTX_HD ( 0x0000u ) +#define DP83640_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define DP83640_NO_100BTX ( 0x0000u ) +#define DP83640_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define DP83640_10BT_HD ( 0x0000u ) +#define DP83640_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define DP83640_NO_10BT ( 0x0000u ) +#define DP83640_10BT ( 0x0020u ) + +/************************************************************************** + API function Prototypes +***************************************************************************/ +extern uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h new file mode 100644 index 00000000000..610217ea173 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/phy_tlk111.h @@ -0,0 +1,156 @@ +/* + * Tlk111.h + */ + +/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com + * ALL RIGHTS RESERVED + */ + +#ifndef _PHY_TLK111_H_ +#define _PHY_TLK111_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** @enum PHY_timestamp + * @brief Alias names for transmit and receive timestamps + * This enumeration is used to provide alias names for getting the transmit and receive + * timestamps from the Tlk111GetTimeStamp API. + */ +typedef enum phyTimeStamp +{ + Txtimestamp = 1, /*Transmit Timestamp*/ + Rxtimestamp = 2 /*Receive Timestamp */ +} phyTimeStamp_t; +/* PHY register offset definitions */ +#define PHY_BCR ( 0u ) +#define PHY_BSR ( 1u ) +#define PHY_ID1 ( 2u ) +#define PHY_ID2 ( 3u ) +#define PHY_AUTONEG_ADV ( 4u ) +#define PHY_LINK_PARTNER_ABLTY ( 5u ) +#define PHY_LINK_PARTNER_SPD ( 16u ) +#define PHY_SWSCR1 ( 9u ) +#define PHY_SWSCR2 ( 10u ) +#define PHY_SWSCR3 ( 11u ) +#define PHY_TXTS ( 28u ) +#define PHY_RXTS ( 29u ) + +/* PHY status definitions */ +#define PHY_ID_SHIFT ( 16u ) +#define PHY_SOFTRESET ( 0x8000U ) +#define PHY_AUTONEG_ENABLE ( 0x1000u ) +#define PHY_AUTONEG_RESTART ( 0x0200u ) +#define PHY_AUTONEG_COMPLETE ( 0x0020u ) +#define PHY_AUTONEG_INCOMPLETE ( 0x0000u ) +#define PHY_AUTONEG_STATUS ( 0x0020u ) +#define PHY_AUTONEG_ABLE ( 0x0008u ) +#define PHY_LPBK_ENABLE ( 0x4000u ) +#define PHY_LINK_STATUS ( 0x0004u ) +#define PHY_INVALID_TYPE ( 0x0u ) + +/* PHY ID. The LSB nibble will vary between different phy revisions */ +#define Tlk111_PHY_ID ( 0x2000A212 ) +#define Tlk111_PHY_ID_REV_MASK ( 0x0000000Fu ) +#define Tlk111_PHY_ID_OUI ( 0x2000A000 ) +#define Tlk111_PHY_ID_OUI_MASK ( 0xFFFFFC00 ) + +/* Pause operations */ +#define Tlk111_PAUSE_NIL ( 0x0000u ) +#define Tlk111_PAUSE_SYM ( 0x0400u ) +#define Tlk111_PAUSE_ASYM ( 0x0800u ) +#define Tlk111_PAUSE_BOTH_SYM_ASYM ( 0x0C00u ) + +/* 100 Base TX Full Duplex capablity */ +#define Tlk111_100BTX_HD ( 0x0000u ) +#define Tlk111_100BTX_FD ( 0x0100u ) + +/* 100 Base TX capability */ +#define Tlk111_NO_100BTX ( 0x0000u ) +#define Tlk111_100BTX ( 0x0080u ) + +/* 10 BaseT duplex capabilities */ +#define Tlk111_10BT_HD ( 0x0000u ) +#define Tlk111_10BT_FD ( 0x0040u ) + +/* 10 BaseT ability*/ +#define Tlk111_NO_10BT ( 0x0000u ) +#define Tlk111_10BT ( 0x0020u ) + +/* Software Strap Register 1 */ +#define Tlk111_SWStrapDone ( 1u << 15 ) +#define Tlk111_Auto_MDIX_Ena ( 1u << 14 ) +#define Tlk111_Auto_Neg_Ena ( 1u << 13 ) +#define Tlk111_Auto_AnMode_10BT_HD ( 0u << 11 ) +#define Tlk111_Auto_AnMode_10BT_FD ( 1u << 11 ) +#define Tlk111_Auto_AnMode_100BT_HD ( 2u << 11 ) +#define Tlk111_Auto_AnMode_100BT_FD ( 3u << 11 ) +#define Tlk111_Force_LEDMode1 ( 1u << 10 ) +#define Tlk111_RMII_Enhanced ( 1u << 9 ) +#define Tlk111_TDR_AutoRun ( 1u << 8 ) +#define Tlk111_LinkLoss_Recovery ( 1u << 8 ) +#define Tlk111_FastAutoMdix ( 1u << 6 ) +#define Tlk111_RobustAutoMdix ( 1u << 5 ) +#define Tlk111_FastAnEn ( 1u << 4 ) +#define Tlk111_FastAnSel0 ( 0u << 2 ) +#define Tlk111_FastAnSel1 ( 1u << 2 ) +#define Tlk111_FastAnSel2 ( 2u << 2 ) +#define Tlk111_FastRxDvDetect ( 1u << 1 ) +#define Tlk111_IntPdn_InterruptOut ( 1u << 0 ) + +/* Software Strap Register 2 */ +#define Tlk111_100BT_Force_FE_LinkDrop ( 1u << 15 ) +#define Tlk111_Rsv1 ( 2u << 7 ) +#define Tlk111_FastLinkUpParallel ( 1u << 6 ) +#define Tlk111_ExtendedFDAbility ( 1u << 5 ) +#define Tlk111_ExtendedLEDLink ( 1u << 4 ) +#define Tlk111_IsolateMII_100BT_HD ( 1u << 3 ) +#define Tlk111_RXERR_DuringIdle ( 1u << 2 ) +#define Tlk111_OddNibbleDetectDisable ( 1u << 1 ) +#define Tlk111_RMII_Use_RXCLK ( 1u << 0 ) +#define Tlk111_RMII_Use_XI ( 0u << 0 ) + +/* Software Strap Register 2 */ +#define Tlk111_FastLinkDown ( 1u << 10 ) +#define Tlk111_PolaritySwap ( 1u << 6 ) +#define Tlk111_MDIXSwap ( 1u << 5 ) +#define Tlk111_Bypass4B5B ( 1u << 4 ) +#define Tlk111_FastLinkDownRxErrCnt ( 1u << 3 ) +#define Tlk111_FastLinkDownMLT3ErrCnt ( 1u << 2 ) +#define Tlk111_FastLinkDownLowSnr ( 1u << 1 ) +#define Tlk111_FastLinkDownSigLoss ( 1u << 0 ) + +/* The Values for SWSCR Registers */ +#define Tlk111_SWSCR1_Val \ + ( Tlk111_Auto_MDIX_Ena | Tlk111_Auto_Neg_Ena | Tlk111_Auto_AnMode_100BT_FD \ + | Tlk111_Force_LEDMode1 | Tlk111_IntPdn_InterruptOut ) +#define Tlk111_SWSCR2_Val ( Tlk111_Rsv1 | Tlk111_RXERR_DuringIdle ) +#define Tlk111_SWSCR3_Val ( 0u ) + +/************************************************************************** + API function Prototypes +***************************************************************************/ +extern uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ); +extern boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); +extern boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ); +extern uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr, + uint32 phyAddr, + phyTimeStamp_t type ); +extern void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ); +extern boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h new file mode 100644 index 00000000000..2ec2e899db4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pinmux.h @@ -0,0 +1,1762 @@ +/** @file pinmux.h + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __PINMUX_H__ +#define __PINMUX_H__ + +#include "reg_pinmux.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define PINMUX_BALL_N19_SHIFT 0U +#define PINMUX_BALL_D4_SHIFT 8U +#define PINMUX_BALL_D5_SHIFT 16U +#define PINMUX_BALL_C4_SHIFT 24U +#define PINMUX_BALL_C5_SHIFT 0U +#define PINMUX_BALL_C6_SHIFT 8U +#define PINMUX_BALL_C7_SHIFT 16U +#define PINMUX_BALL_C8_SHIFT 24U +#define PINMUX_BALL_C9_SHIFT 0U +#define PINMUX_BALL_C10_SHIFT 8U +#define PINMUX_BALL_C11_SHIFT 16U +#define PINMUX_BALL_C12_SHIFT 24U +#define PINMUX_BALL_C13_SHIFT 0U +#define PINMUX_BALL_D14_SHIFT 8U +#define PINMUX_BALL_C14_SHIFT 16U +#define PINMUX_BALL_D15_SHIFT 24U +#define PINMUX_BALL_C15_SHIFT 0U +#define PINMUX_BALL_C16_SHIFT 8U +#define PINMUX_BALL_C17_SHIFT 16U +#define PINMUX_BALL_D16_SHIFT 24U +#define PINMUX_BALL_K3_SHIFT 0U +#define PINMUX_BALL_R4_SHIFT 8U +#define PINMUX_BALL_N17_SHIFT 16U +#define PINMUX_BALL_L17_SHIFT 24U +#define PINMUX_BALL_K17_SHIFT 0U +#define PINMUX_BALL_M17_SHIFT 8U +#define PINMUX_BALL_R3_SHIFT 16U +#define PINMUX_BALL_P3_SHIFT 24U +#define PINMUX_BALL_D17_SHIFT 0U +#define PINMUX_BALL_E9_SHIFT 8U +#define PINMUX_BALL_E8_SHIFT 16U +#define PINMUX_BALL_E7_SHIFT 24U +#define PINMUX_BALL_E6_SHIFT 0U +#define PINMUX_BALL_E13_SHIFT 8U +#define PINMUX_BALL_E12_SHIFT 16U +#define PINMUX_BALL_E11_SHIFT 24U +#define PINMUX_BALL_E10_SHIFT 0U +#define PINMUX_BALL_K15_SHIFT 8U +#define PINMUX_BALL_L15_SHIFT 16U +#define PINMUX_BALL_M15_SHIFT 24U +#define PINMUX_BALL_N15_SHIFT 0U +#define PINMUX_BALL_E5_SHIFT 8U +#define PINMUX_BALL_F5_SHIFT 16U +#define PINMUX_BALL_G5_SHIFT 24U +#define PINMUX_BALL_K5_SHIFT 0U +#define PINMUX_BALL_L5_SHIFT 8U +#define PINMUX_BALL_M5_SHIFT 16U +#define PINMUX_BALL_N5_SHIFT 24U +#define PINMUX_BALL_P5_SHIFT 0U +#define PINMUX_BALL_R5_SHIFT 8U +#define PINMUX_BALL_R6_SHIFT 16U +#define PINMUX_BALL_R7_SHIFT 24U +#define PINMUX_BALL_R8_SHIFT 0U +#define PINMUX_BALL_R9_SHIFT 8U +#define PINMUX_BALL_R10_SHIFT 16U +#define PINMUX_BALL_R11_SHIFT 24U +#define PINMUX_BALL_B15_SHIFT 0U +#define PINMUX_BALL_B8_SHIFT 8U +#define PINMUX_BALL_B16_SHIFT 16U +#define PINMUX_BALL_B9_SHIFT 24U +#define PINMUX_BALL_C1_SHIFT 0U +#define PINMUX_BALL_E1_SHIFT 8U +#define PINMUX_BALL_B5_SHIFT 16U +#define PINMUX_BALL_H3_SHIFT 24U +#define PINMUX_BALL_M1_SHIFT 0U +#define PINMUX_BALL_F2_SHIFT 8U +#define PINMUX_BALL_W10_SHIFT 16U +#define PINMUX_BALL_J2_SHIFT 24U +#define PINMUX_BALL_F1_SHIFT 0U +#define PINMUX_BALL_R2_SHIFT 8U +#define PINMUX_BALL_F3_SHIFT 16U +#define PINMUX_BALL_G3_SHIFT 24U +#define PINMUX_BALL_J3_SHIFT 0U +#define PINMUX_BALL_G19_SHIFT 8U +#define PINMUX_BALL_V9_SHIFT 16U +#define PINMUX_BALL_V10_SHIFT 24U +#define PINMUX_BALL_V5_SHIFT 0U +#define PINMUX_BALL_B2_SHIFT 8U +#define PINMUX_BALL_C3_SHIFT 16U +#define PINMUX_BALL_W9_SHIFT 24U +#define PINMUX_BALL_W8_SHIFT 0U +#define PINMUX_BALL_V8_SHIFT 8U +#define PINMUX_BALL_H19_SHIFT 16U +#define PINMUX_BALL_E19_SHIFT 24U +#define PINMUX_BALL_B6_SHIFT 0U +#define PINMUX_BALL_W6_SHIFT 8U +#define PINMUX_BALL_T12_SHIFT 16U +#define PINMUX_BALL_H18_SHIFT 24U +#define PINMUX_BALL_J19_SHIFT 0U +#define PINMUX_BALL_E16_SHIFT 8U +#define PINMUX_BALL_H17_SHIFT 16U +#define PINMUX_BALL_G17_SHIFT 24U +#define PINMUX_BALL_J18_SHIFT 0U +#define PINMUX_BALL_E17_SHIFT 8U +#define PINMUX_BALL_H16_SHIFT 16U +#define PINMUX_BALL_G16_SHIFT 24U +#define PINMUX_BALL_K18_SHIFT 0U +#define PINMUX_BALL_V2_SHIFT 8U +#define PINMUX_BALL_W5_SHIFT 16U +#define PINMUX_BALL_U1_SHIFT 24U +#define PINMUX_BALL_B12_SHIFT 0U +#define PINMUX_BALL_V6_SHIFT 8U +#define PINMUX_BALL_W3_SHIFT 16U +#define PINMUX_BALL_T1_SHIFT 24U +#define PINMUX_BALL_E18_SHIFT 0U +#define PINMUX_BALL_V7_SHIFT 8U +#define PINMUX_BALL_D19_SHIFT 16U +#define PINMUX_BALL_E3_SHIFT 24U +#define PINMUX_BALL_B4_SHIFT 0U +#define PINMUX_BALL_N2_SHIFT 8U +#define PINMUX_BALL_N1_SHIFT 16U +#define PINMUX_BALL_A4_SHIFT 24U +#define PINMUX_BALL_A13_SHIFT 0U +#define PINMUX_BALL_J1_SHIFT 8U +#define PINMUX_BALL_B13_SHIFT 16U +#define PINMUX_BALL_P2_SHIFT 24U +#define PINMUX_BALL_H4_SHIFT 0U +#define PINMUX_BALL_B3_SHIFT 8U +#define PINMUX_BALL_J4_SHIFT 16U +#define PINMUX_BALL_P1_SHIFT 24U +#define PINMUX_BALL_A14_SHIFT 0U +#define PINMUX_BALL_K19_SHIFT 8U +#define PINMUX_BALL_B11_SHIFT 16U +#define PINMUX_BALL_D8_SHIFT 24U +#define PINMUX_BALL_D7_SHIFT 0U +#define PINMUX_BALL_D3_SHIFT 8U +#define PINMUX_BALL_D2_SHIFT 16U +#define PINMUX_BALL_D1_SHIFT 24U +#define PINMUX_BALL_P4_SHIFT 0U +#define PINMUX_BALL_T5_SHIFT 8U +#define PINMUX_BALL_T4_SHIFT 16U +#define PINMUX_BALL_U7_SHIFT 24U +#define PINMUX_BALL_E2_SHIFT 0U +#define PINMUX_BALL_N3_SHIFT 8U + +#define PINMUX_GATE_EMIF_CLK_SHIFT 0U +#define PINMUX_EMIF_OUTPUT_ENABLE_SHIFT 8U +#define PINMUX_GIOA_DISABLE_HET1_SHIFT 8U +#define PINMUX_GIOB_DISABLE_HET2_SHIFT 0U +#define PINMUX_ALT_ADC_TRIGGER_SHIFT 0U +#define PINMUX_ETHERNET_SHIFT 24U +#define PINMUX_ETPWM1_SHIFT 0U +#define PINMUX_ETPWM2_SHIFT 8U +#define PINMUX_ETPWM3_SHIFT 16U +#define PINMUX_ETPWM4_SHIFT 24U +#define PINMUX_ETPWM5_SHIFT 0U +#define PINMUX_ETPWM6_SHIFT 8U +#define PINMUX_ETPWM7_SHIFT 16U +#define PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT 24U +#define PINMUX_ETPWM_TBCLK_SYNC_SHIFT 0U +#define PINMUX_TZ1_SHIFT 16U +#define PINMUX_TZ2_SHIFT 24U +#define PINMUX_TZ3_SHIFT 0U +#define PINMUX_EPWM1SYNCI_SHIFT 8U +#define PINMUX_ETPWM_SOC1A_SHIFT 0U +#define PINMUX_ETPWM_SOC2A_SHIFT 8U +#define PINMUX_ETPWM_SOC3A_SHIFT 16U +#define PINMUX_ETPWM_SOC4A_SHIFT 24U +#define PINMUX_ETPWM_SOC5A_SHIFT 0U +#define PINMUX_ETPWM_SOC6A_SHIFT 8U +#define PINMUX_ETPWM_SOC7A_SHIFT 16U +#define PINMUX_EQEP1A_FILTER_SHIFT 16U +#define PINMUX_EQEP1B_FILTER_SHIFT 24U +#define PINMUX_EQEP1I_FILTER_SHIFT 0U +#define PINMUX_EQEP1S_FILTER_SHIFT 8U +#define PINMUX_EQEP2A_FILTER_SHIFT 16U +#define PINMUX_EQEP2B_FILTER_SHIFT 24U +#define PINMUX_EQEP2I_FILTER_SHIFT 0U +#define PINMUX_EQEP2S_FILTER_SHIFT 8U +#define PINMUX_ECAP1_FILTER_SHIFT 0U +#define PINMUX_ECAP2_FILTER_SHIFT 8U +#define PINMUX_ECAP3_FILTER_SHIFT 16U +#define PINMUX_ECAP4_FILTER_SHIFT 24U +#define PINMUX_ECAP5_FILTER_SHIFT 0U +#define PINMUX_ECAP6_FILTER_SHIFT 8U +#define PINMUX_GIOA0_DMA_SHIFT 0U +#define PINMUX_GIOA1_DMA_SHIFT 8U +#define PINMUX_GIOA2_DMA_SHIFT 16U +#define PINMUX_GIOA3_DMA_SHIFT 24U +#define PINMUX_GIOA4_DMA_SHIFT 0U +#define PINMUX_GIOA5_DMA_SHIFT 8U +#define PINMUX_GIOA6_DMA_SHIFT 16U +#define PINMUX_GIOA7_DMA_SHIFT 24U +#define PINMUX_GIOB0_DMA_SHIFT 0U +#define PINMUX_GIOB1_DMA_SHIFT 8U +#define PINMUX_GIOB2_DMA_SHIFT 16U +#define PINMUX_GIOB3_DMA_SHIFT 24U +#define PINMUX_GIOB4_DMA_SHIFT 0U +#define PINMUX_GIOB5_DMA_SHIFT 8U +#define PINMUX_GIOB6_DMA_SHIFT 16U +#define PINMUX_GIOB7_DMA_SHIFT 24U +#define PINMUX_TEMP1_ENABLE_SHIFT 16U +#define PINMUX_TEMP2_ENABLE_SHIFT 24U +#define PINMUX_TEMP3_ENABLE_SHIFT 0U + +#define PINMUX_BALL_N19_MASK \ + ( ~( uint32 ) ( ( uint32 ) uint32 )( ( uint32 ) 0xFFU << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_D4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_C4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C7_SHIFT ) ) +#define PINMUX_BALL_C8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C8_SHIFT ) ) +#define PINMUX_BALL_C9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C9_SHIFT ) ) +#define PINMUX_BALL_C10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C10_SHIFT ) ) +#define PINMUX_BALL_C11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C11_SHIFT ) ) +#define PINMUX_BALL_C12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C12_SHIFT ) ) +#define PINMUX_BALL_C13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C13_SHIFT ) ) +#define PINMUX_BALL_D14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D14_SHIFT ) ) +#define PINMUX_BALL_C14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C14_SHIFT ) ) +#define PINMUX_BALL_D15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D15_SHIFT ) ) +#define PINMUX_BALL_C15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C15_SHIFT ) ) +#define PINMUX_BALL_C16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C16_SHIFT ) ) +#define PINMUX_BALL_C17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C17_SHIFT ) ) +#define PINMUX_BALL_D16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_K3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_R4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R4_SHIFT ) ) +#define PINMUX_BALL_N17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_L17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L17_SHIFT ) ) +#define PINMUX_BALL_K17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_M17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_R3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R3_SHIFT ) ) +#define PINMUX_BALL_P3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P3_SHIFT ) ) +#define PINMUX_BALL_D17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_E9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E9_SHIFT ) ) +#define PINMUX_BALL_E8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E8_SHIFT ) ) +#define PINMUX_BALL_E7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E7_SHIFT ) ) +#define PINMUX_BALL_E6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E6_SHIFT ) ) +#define PINMUX_BALL_E13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E13_SHIFT ) ) +#define PINMUX_BALL_E12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E12_SHIFT ) ) +#define PINMUX_BALL_E11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E11_SHIFT ) ) +#define PINMUX_BALL_E10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E10_SHIFT ) ) +#define PINMUX_BALL_K15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K15_SHIFT ) ) +#define PINMUX_BALL_L15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L15_SHIFT ) ) +#define PINMUX_BALL_M15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M15_SHIFT ) ) +#define PINMUX_BALL_N15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N15_SHIFT ) ) +#define PINMUX_BALL_E5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E5_SHIFT ) ) +#define PINMUX_BALL_F5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F5_SHIFT ) ) +#define PINMUX_BALL_G5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G5_SHIFT ) ) +#define PINMUX_BALL_K5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K5_SHIFT ) ) +#define PINMUX_BALL_L5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_M5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_N5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_P5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_R5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R10_SHIFT ) ) +#define PINMUX_BALL_R11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R11_SHIFT ) ) +#define PINMUX_BALL_B15_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B15_SHIFT ) ) +#define PINMUX_BALL_B8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B8_SHIFT ) ) +#define PINMUX_BALL_B16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B16_SHIFT ) ) +#define PINMUX_BALL_B9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B9_SHIFT ) ) +#define PINMUX_BALL_C1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_E1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_B5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_H3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_M1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_F2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F2_SHIFT ) ) +#define PINMUX_BALL_W10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_J2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J2_SHIFT ) ) +#define PINMUX_BALL_F1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_R2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_F3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_G3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_J3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_G19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_V9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V10_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_B2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_C3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_W9_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_V8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_H19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_E19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_B6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B6_SHIFT ) ) +#define PINMUX_BALL_W6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W6_SHIFT ) ) +#define PINMUX_BALL_T12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_H18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_J19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_E16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_H17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_G17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_J18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_E17_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_H16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_G16_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_K18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_V2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_W5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_U1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_B12_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_V6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_W3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_T1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_E18_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_V7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_D19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_E3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_B4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_N2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_A4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_J1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_B13_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_P2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_H4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_H4_SHIFT ) ) +#define PINMUX_BALL_B3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_J4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_J4_SHIFT ) ) +#define PINMUX_BALL_P1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_A14_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_K19_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_B11_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_D8_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D8_SHIFT ) ) +#define PINMUX_BALL_D7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D7_SHIFT ) ) +#define PINMUX_BALL_D3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D2_SHIFT ) ) +#define PINMUX_BALL_D1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_D1_SHIFT ) ) +#define PINMUX_BALL_P4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_P4_SHIFT ) ) +#define PINMUX_BALL_T5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T5_SHIFT ) ) +#define PINMUX_BALL_T4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_T4_SHIFT ) ) +#define PINMUX_BALL_U7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_U7_SHIFT ) ) +#define PINMUX_BALL_E2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_E2_SHIFT ) ) +#define PINMUX_BALL_N3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_BALL_N3_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_MASK ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_EQEP2S_FILTER_SHIFT ) ) +#define PINMUX_ECAP1_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_ECAP6_FILTER_SHIFT ) ) + +#define PINMUX_GIOA0_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_MASK \ + ( ~( uint32 ) ( ( uint32 ) 0xFFU << PINMUX_TEMP3_ENABLE_SHIFT ) ) + +#define PINMUX_BALL_N19_AD1EVT ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_MII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_RMII_RX_ER \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N19_SHIFT ) ) +#define PINMUX_BALL_N19_nTZ1_1 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N19_SHIFT ) ) + +#define PINMUX_BALL_D4_EMIF_ADDR_00 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D4_SHIFT ) ) +#define PINMUX_BALL_D4_N2HET2_01 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D4_SHIFT ) ) + +#define PINMUX_BALL_D5_EMIF_ADDR_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D5_SHIFT ) ) +#define PINMUX_BALL_D5_N2HET2_03 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D5_SHIFT ) ) + +#define PINMUX_BALL_C4_EMIF_ADDR_06 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_RTP_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C4_SHIFT ) ) +#define PINMUX_BALL_C4_N2HET2_11 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C4_SHIFT ) ) + +#define PINMUX_BALL_C5_EMIF_ADDR_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_RTP_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C5_SHIFT ) ) +#define PINMUX_BALL_C5_N2HET2_13 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C5_SHIFT ) ) + +#define PINMUX_BALL_C6_EMIF_ADDR_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_RTP_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C6_SHIFT ) ) +#define PINMUX_BALL_C6_N2HET2_15 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C6_SHIFT ) ) + +#define PINMUX_BALL_C7_EMIF_ADDR_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C7_SHIFT ) ) +#define PINMUX_BALL_C7_RTP_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C7_SHIFT ) ) + +#define PINMUX_BALL_C8_EMIF_ADDR_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C8_SHIFT ) ) +#define PINMUX_BALL_C8_RTP_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C8_SHIFT ) ) + +#define PINMUX_BALL_C9_EMIF_ADDR_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C9_SHIFT ) ) +#define PINMUX_BALL_C9_RTP_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C9_SHIFT ) ) + +#define PINMUX_BALL_C10_EMIF_ADDR_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C10_SHIFT ) ) +#define PINMUX_BALL_C10_RTP_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C10_SHIFT ) ) + +#define PINMUX_BALL_C11_EMIF_ADDR_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C11_SHIFT ) ) +#define PINMUX_BALL_C11_RTP_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C11_SHIFT ) ) + +#define PINMUX_BALL_C12_EMIF_ADDR_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C12_SHIFT ) ) +#define PINMUX_BALL_C12_RTP_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C12_SHIFT ) ) + +#define PINMUX_BALL_C13_EMIF_ADDR_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C13_SHIFT ) ) +#define PINMUX_BALL_C13_RTP_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C13_SHIFT ) ) + +#define PINMUX_BALL_D14_EMIF_ADDR_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D14_SHIFT ) ) +#define PINMUX_BALL_D14_RTP_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D14_SHIFT ) ) + +#define PINMUX_BALL_C14_EMIF_ADDR_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C14_SHIFT ) ) +#define PINMUX_BALL_C14_RTP_DATA_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C14_SHIFT ) ) + +#define PINMUX_BALL_D15_EMIF_ADDR_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D15_SHIFT ) ) +#define PINMUX_BALL_D15_RTP_DATA_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D15_SHIFT ) ) + +#define PINMUX_BALL_C15_EMIF_ADDR_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C15_SHIFT ) ) +#define PINMUX_BALL_C15_RTP_nENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C15_SHIFT ) ) + +#define PINMUX_BALL_C16_EMIF_ADDR_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C16_SHIFT ) ) +#define PINMUX_BALL_C16_RTP_nSYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C16_SHIFT ) ) + +#define PINMUX_BALL_C17_EMIF_ADDR_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C17_SHIFT ) ) +#define PINMUX_BALL_C17_RTP_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C17_SHIFT ) ) + +#define PINMUX_BALL_D16_EMIF_BA_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_8_25 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D16_SHIFT ) ) +#define PINMUX_BALL_D16_N2HET2_05 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D16_SHIFT ) ) + +#define PINMUX_BALL_K3_RESERVED ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_K3_EMIF_CLK ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K3_SHIFT ) ) +#define PINMUX_BALL_K3_ECLK2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K3_SHIFT ) ) + +#define PINMUX_BALL_R4_EMIF_nCAS \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R4_SHIFT ) ) +#define PINMUX_BALL_R4_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R4_SHIFT ) ) + +#define PINMUX_BALL_N17_EMIF_nCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_RTP_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N17_SHIFT ) ) +#define PINMUX_BALL_N17_N2HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N17_SHIFT ) ) + +#define PINMUX_BALL_L17_EMIF_nCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L17_SHIFT ) ) +#define PINMUX_BALL_L17_GIOB_4 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_L17_SHIFT ) ) + +#define PINMUX_BALL_K17_EMIF_nCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_RTP_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K17_SHIFT ) ) +#define PINMUX_BALL_K17_N2HET2_09 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K17_SHIFT ) ) + +#define PINMUX_BALL_M17_EMIF_nCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_M17_RTP_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M17_SHIFT ) ) +#define PINMUX_BALL_M17_GIOB_5 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M17_SHIFT ) ) + +#define PINMUX_BALL_R3_EMIF_nRAS \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R3_SHIFT ) ) +#define PINMUX_BALL_R3_GIOB_6 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R3_SHIFT ) ) + +#define PINMUX_BALL_P3_EMIF_nWAIT \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P3_SHIFT ) ) +#define PINMUX_BALL_P3_GIOB_7 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P3_SHIFT ) ) + +#define PINMUX_BALL_D17_EMIF_nWE \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D17_SHIFT ) ) +#define PINMUX_BALL_D17_EMIF_RNW \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D17_SHIFT ) ) + +#define PINMUX_BALL_E9_ETMDATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E9_SHIFT ) ) +#define PINMUX_BALL_E9_EMIF_ADDR_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E9_SHIFT ) ) + +#define PINMUX_BALL_E8_ETMDATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E8_SHIFT ) ) +#define PINMUX_BALL_E8_EMIF_ADDR_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E8_SHIFT ) ) + +#define PINMUX_BALL_E7_ETMDATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E7_SHIFT ) ) +#define PINMUX_BALL_E7_EMIF_ADDR_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E7_SHIFT ) ) + +#define PINMUX_BALL_E6_ETMDATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E6_SHIFT ) ) +#define PINMUX_BALL_E6_EMIF_ADDR_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E6_SHIFT ) ) + +#define PINMUX_BALL_E13_ETMDATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E13_SHIFT ) ) +#define PINMUX_BALL_E13_EMIF_BA_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E13_SHIFT ) ) + +#define PINMUX_BALL_E12_ETMDATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E12_SHIFT ) ) +#define PINMUX_BALL_E12_EMIF_nOE \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E12_SHIFT ) ) + +#define PINMUX_BALL_E11_ETMDATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E11_SHIFT ) ) +#define PINMUX_BALL_E11_EMIF_nDQM_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E11_SHIFT ) ) + +#define PINMUX_BALL_E10_ETMDATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E10_SHIFT ) ) +#define PINMUX_BALL_E10_EMIF_nDQM_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E10_SHIFT ) ) + +#define PINMUX_BALL_K15_ETMDATA_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K15_SHIFT ) ) +#define PINMUX_BALL_K15_EMIF_DATA_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K15_SHIFT ) ) + +#define PINMUX_BALL_L15_ETMDATA_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L15_SHIFT ) ) +#define PINMUX_BALL_L15_EMIF_DATA_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_L15_SHIFT ) ) + +#define PINMUX_BALL_M15_ETMDATA_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M15_SHIFT ) ) +#define PINMUX_BALL_M15_EMIF_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M15_SHIFT ) ) + +#define PINMUX_BALL_N15_ETMDATA_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N15_SHIFT ) ) +#define PINMUX_BALL_N15_EMIF_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N15_SHIFT ) ) + +#define PINMUX_BALL_E5_ETMDATA_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E5_SHIFT ) ) +#define PINMUX_BALL_E5_EMIF_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E5_SHIFT ) ) + +#define PINMUX_BALL_F5_ETMDATA_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F5_SHIFT ) ) +#define PINMUX_BALL_F5_EMIF_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F5_SHIFT ) ) + +#define PINMUX_BALL_G5_ETMDATA_22 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G5_SHIFT ) ) +#define PINMUX_BALL_G5_EMIF_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G5_SHIFT ) ) + +#define PINMUX_BALL_K5_ETMDATA_23 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K5_SHIFT ) ) +#define PINMUX_BALL_K5_EMIF_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K5_SHIFT ) ) + +#define PINMUX_BALL_L5_ETMDATA_24 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_EMIF_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_N2HET2_24 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_L5_SHIFT ) ) +#define PINMUX_BALL_L5_MIBSPI5NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_L5_SHIFT ) ) + +#define PINMUX_BALL_M5_ETMDATA_25 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_EMIF_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_N2HET2_25 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M5_SHIFT ) ) +#define PINMUX_BALL_M5_MIBSPI5NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_M5_SHIFT ) ) + +#define PINMUX_BALL_N5_ETMDATA_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_N5_EMIF_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N5_SHIFT ) ) +#define PINMUX_BALL_N5_N2HET2_26 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_N5_SHIFT ) ) + +#define PINMUX_BALL_P5_ETMDATA_27 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_P5_EMIF_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P5_SHIFT ) ) +#define PINMUX_BALL_P5_N2HET2_27 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P5_SHIFT ) ) + +#define PINMUX_BALL_R5_ETMDATA_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_EMIF_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_N2HET2_28 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R5_SHIFT ) ) +#define PINMUX_BALL_R5_GIOA_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R5_SHIFT ) ) + +#define PINMUX_BALL_R6_ETMDATA_29 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_EMIF_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_N2HET2_29 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R6_SHIFT ) ) +#define PINMUX_BALL_R6_GIOA_1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R6_SHIFT ) ) + +#define PINMUX_BALL_R7_ETMDATA_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_EMIF_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_N2HET2_30 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R7_SHIFT ) ) +#define PINMUX_BALL_R7_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R7_SHIFT ) ) + +#define PINMUX_BALL_R8_ETMDATA_31 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_EMIF_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_N2HET2_31 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R8_SHIFT ) ) +#define PINMUX_BALL_R8_GIOA_4 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R8_SHIFT ) ) + +#define PINMUX_BALL_R9_ETMTRACECLKIN \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R9_EXTCLKIN2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R9_SHIFT ) ) +#define PINMUX_BALL_R9_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R9_SHIFT ) ) + +#define PINMUX_BALL_R10_ETMTRACECLKOUT \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R10_SHIFT ) ) +#define PINMUX_BALL_R10_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R10_SHIFT ) ) + +#define PINMUX_BALL_R11_ETMTRACECTL \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R11_SHIFT ) ) +#define PINMUX_BALL_R11_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_R11_SHIFT ) ) + +#define PINMUX_BALL_B15_FRAYTX1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B15_SHIFT ) ) +#define PINMUX_BALL_B15_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B15_SHIFT ) ) + +#define PINMUX_BALL_B8_FRAYTX2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B8_SHIFT ) ) +#define PINMUX_BALL_B8_GIOB_0 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B8_SHIFT ) ) + +#define PINMUX_BALL_B16_FRAYTXEN1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B16_SHIFT ) ) +#define PINMUX_BALL_B16_GIOB_1 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B16_SHIFT ) ) + +#define PINMUX_BALL_B9_FRAYTXEN2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B9_SHIFT ) ) +#define PINMUX_BALL_B9_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B9_SHIFT ) ) + +#define PINMUX_BALL_C1_GIOA_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_N2HET2_00 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_C1_SHIFT ) ) +#define PINMUX_BALL_C1_eQEP2I ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_C1_SHIFT ) ) + +#define PINMUX_BALL_E1_GIOA_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E1_SHIFT ) ) +#define PINMUX_BALL_E1_N2HET2_02 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E1_SHIFT ) ) + +#define PINMUX_BALL_B5_GIOA_5 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_EXTCLKIN ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B5_SHIFT ) ) +#define PINMUX_BALL_B5_eTPWM1A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B5_SHIFT ) ) + +#define PINMUX_BALL_H3_GIOA_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_N2HET2_04 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H3_SHIFT ) ) +#define PINMUX_BALL_H3_eTPWM1B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H3_SHIFT ) ) + +#define PINMUX_BALL_M1_GIOA_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_N2HET2_06 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_M1_SHIFT ) ) +#define PINMUX_BALL_M1_eTPWM2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_M1_SHIFT ) ) + +#define PINMUX_BALL_F2_GIOB_2 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F2_SHIFT ) ) +#define PINMUX_BALL_F2_DCAN4TX ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F2_SHIFT ) ) + +#define PINMUX_BALL_W10_GIOB_3 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W10_SHIFT ) ) +#define PINMUX_BALL_W10_DCAN4RX \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W10_SHIFT ) ) + +#define PINMUX_BALL_J2_GIOB_6 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J2_SHIFT ) ) +#define PINMUX_BALL_J2_nERROR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J2_SHIFT ) ) + +#define PINMUX_BALL_F1_GIOB_7 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_F1_nERROR2 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_F1_SHIFT ) ) +#define PINMUX_BALL_F1_nTZ1_2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_F1_SHIFT ) ) + +#define PINMUX_BALL_R2_MIBSPI1NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MIBSPI1SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_MII_TXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_R2_SHIFT ) ) +#define PINMUX_BALL_R2_ECAP6 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_R2_SHIFT ) ) + +#define PINMUX_BALL_F3_MIBSPI1NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_MII_COL ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_N2HET1_17 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_F3_SHIFT ) ) +#define PINMUX_BALL_F3_eQEP1S ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_F3_SHIFT ) ) + +#define PINMUX_BALL_G3_MIBSPI1NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_MDIO ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G3_SHIFT ) ) +#define PINMUX_BALL_G3_N2HET1_19 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G3_SHIFT ) ) + +#define PINMUX_BALL_J3_MIBSPI1NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_N2HET1_21 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J3_SHIFT ) ) +#define PINMUX_BALL_J3_nTZ1_3 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_J3_SHIFT ) ) + +#define PINMUX_BALL_G19_MIBSPI1NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_MII_RXD_2 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_N2HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_G19_SHIFT ) ) +#define PINMUX_BALL_G19_ECAP4 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_G19_SHIFT ) ) + +#define PINMUX_BALL_V9_MIBSPI3CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_EXT_SEL_01 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V9_SHIFT ) ) +#define PINMUX_BALL_V9_eQEP1A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V9_SHIFT ) ) + +#define PINMUX_BALL_V10_MIBSPI3NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_AD2EVT ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V10_SHIFT ) ) +#define PINMUX_BALL_V10_eQEP1I \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V10_SHIFT ) ) + +#define PINMUX_BALL_V5_MIBSPI3NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_MDCLK ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_V5_SHIFT ) ) +#define PINMUX_BALL_V5_N2HET1_25 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V5_SHIFT ) ) + +#define PINMUX_BALL_B2_MIBSPI3NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_I2C1_SDA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_N2HET1_27 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B2_SHIFT ) ) +#define PINMUX_BALL_B2_nTZ1_2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B2_SHIFT ) ) + +#define PINMUX_BALL_C3_MIBSPI3NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_I2C1_SCL ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_N2HET1_29 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_C3_SHIFT ) ) +#define PINMUX_BALL_C3_nTZ1_1 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_C3_SHIFT ) ) + +#define PINMUX_BALL_W9_MIBSPI3NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_MIBSPI3NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_N2HET1_31 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_W9_SHIFT ) ) +#define PINMUX_BALL_W9_eQEP1B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W9_SHIFT ) ) + +#define PINMUX_BALL_W8_MIBSPI3SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_EXT_SEL_00 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W8_SHIFT ) ) +#define PINMUX_BALL_W8_ECAP3 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W8_SHIFT ) ) + +#define PINMUX_BALL_V8_MIBSPI3SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_EXT_ENA ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V8_SHIFT ) ) +#define PINMUX_BALL_V8_ECAP2 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V8_SHIFT ) ) + +#define PINMUX_BALL_H19_MIBSPI5CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_DMM_DATA_04 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_MII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H19_SHIFT ) ) +#define PINMUX_BALL_H19_RMII_TXEN \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_H19_SHIFT ) ) + +#define PINMUX_BALL_E19_MIBSPI5NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_DMM_DATA_05 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E19_SHIFT ) ) +#define PINMUX_BALL_E19_eTPWM4A \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E19_SHIFT ) ) + +#define PINMUX_BALL_B6_MIBSPI5NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B6_SHIFT ) ) +#define PINMUX_BALL_B6_DMM_DATA_06 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B6_SHIFT ) ) + +#define PINMUX_BALL_W6_MIBSPI5NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W6_SHIFT ) ) +#define PINMUX_BALL_W6_DMM_DATA_02 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W6_SHIFT ) ) + +#define PINMUX_BALL_T12_MIBSPI5NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T12_SHIFT ) ) +#define PINMUX_BALL_T12_DMM_DATA_03 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T12_SHIFT ) ) + +#define PINMUX_BALL_H18_MIBSPI5NENA \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_DMM_DATA_07 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_MII_RXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_H18_SHIFT ) ) +#define PINMUX_BALL_H18_ECAP5 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_H18_SHIFT ) ) + +#define PINMUX_BALL_J19_MIBSPI5SIMO_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_DMM_DATA_08 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_MII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J19_SHIFT ) ) +#define PINMUX_BALL_J19_RMII_TXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J19_SHIFT ) ) + +#define PINMUX_BALL_E16_MIBSPI5SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_E16_DMM_DATA_09 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E16_SHIFT ) ) +#define PINMUX_BALL_E16_EXT_SEL_00 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E16_SHIFT ) ) + +#define PINMUX_BALL_H17_MIBSPI5SIMO_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_H17_DMM_DATA_10 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H17_SHIFT ) ) +#define PINMUX_BALL_H17_EXT_SEL_01 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H17_SHIFT ) ) + +#define PINMUX_BALL_G17_MIBSPI5SIMO_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_DMM_DATA_11 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_I2C2_SDA \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G17_SHIFT ) ) +#define PINMUX_BALL_G17_EXT_SEL_02 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G17_SHIFT ) ) + +#define PINMUX_BALL_J18_MIBSPI5SOMI_0 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_DMM_DATA_12 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_MII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_J18_SHIFT ) ) +#define PINMUX_BALL_J18_RMII_TXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_J18_SHIFT ) ) + +#define PINMUX_BALL_E17_MIBSPI5SOMI_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_E17_DMM_DATA_13 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E17_SHIFT ) ) +#define PINMUX_BALL_E17_EXT_SEL_03 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E17_SHIFT ) ) + +#define PINMUX_BALL_H16_MIBSPI5SOMI_2 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_H16_DMM_DATA_14 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H16_SHIFT ) ) +#define PINMUX_BALL_H16_EXT_SEL_04 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_H16_SHIFT ) ) + +#define PINMUX_BALL_G16_MIBSPI5SOMI_3 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_DMM_DATA_15 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_I2C2_SCL \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_G16_SHIFT ) ) +#define PINMUX_BALL_G16_EXT_ENA \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_G16_SHIFT ) ) + +#define PINMUX_BALL_K18_N2HET1_00 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_MIBSPI4CLK \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_K18_SHIFT ) ) +#define PINMUX_BALL_K18_eTPWM2B \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_K18_SHIFT ) ) + +#define PINMUX_BALL_V2_N2HET1_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_MIBSPI4NENA \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_N2HET2_08 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V2_SHIFT ) ) +#define PINMUX_BALL_V2_eQEP2A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V2_SHIFT ) ) + +#define PINMUX_BALL_W5_N2HET1_02 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_MIBSPI4SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W5_SHIFT ) ) +#define PINMUX_BALL_W5_eTPWM3A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W5_SHIFT ) ) + +#define PINMUX_BALL_U1_N2HET1_03 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_MIBSPI4NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_N2HET2_10 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_U1_SHIFT ) ) +#define PINMUX_BALL_U1_eQEP2B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_U1_SHIFT ) ) + +#define PINMUX_BALL_B12_N2HET1_04 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_MIBSPI4NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B12_SHIFT ) ) +#define PINMUX_BALL_B12_eTPWM4B \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B12_SHIFT ) ) + +#define PINMUX_BALL_V6_N2HET1_05 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_MIBSPI4SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_N2HET2_12 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V6_SHIFT ) ) +#define PINMUX_BALL_V6_eTPWM3B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V6_SHIFT ) ) + +#define PINMUX_BALL_W3_N2HET1_06 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_SCI3RX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_W3_SHIFT ) ) +#define PINMUX_BALL_W3_eTPWM5A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_W3_SHIFT ) ) + +#define PINMUX_BALL_T1_N2HET1_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_MIBSPI4NCS_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_N2HET2_14 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_T1_SHIFT ) ) +#define PINMUX_BALL_T1_eTPWM7B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_T1_SHIFT ) ) + +#define PINMUX_BALL_E18_N2HET1_08 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MIBSPI1SIMO_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E18_SHIFT ) ) +#define PINMUX_BALL_E18_MII_TXD_3 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_E18_SHIFT ) ) + +#define PINMUX_BALL_V7_N2HET1_09 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_MIBSPI4NCS_3 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_N2HET2_16 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_V7_SHIFT ) ) +#define PINMUX_BALL_V7_eTPWM7A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_V7_SHIFT ) ) + +#define PINMUX_BALL_D19_N2HET1_10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MIBSPI4NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_D19_SHIFT ) ) +#define PINMUX_BALL_D19_nTZ1_3 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_D19_SHIFT ) ) + +#define PINMUX_BALL_E3_N2HET1_11 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_MIBSPI3NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_N2HET2_18 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_E3_SHIFT ) ) +#define PINMUX_BALL_E3_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_E3_SHIFT ) ) + +#define PINMUX_BALL_B4_N2HET1_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MIBSPI4NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_MII_CRS ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B4_SHIFT ) ) +#define PINMUX_BALL_B4_RMII_CRS_DV \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_B4_SHIFT ) ) + +#define PINMUX_BALL_N2_N2HET1_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_SCI3TX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_N2HET2_20 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N2_SHIFT ) ) +#define PINMUX_BALL_N2_eTPWM5B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N2_SHIFT ) ) + +#define PINMUX_BALL_N1_N2HET1_15 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_MIBSPI1NCS_4 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_N2HET2_22 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_N1_SHIFT ) ) +#define PINMUX_BALL_N1_ECAP1 ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_N1_SHIFT ) ) + +#define PINMUX_BALL_A4_N2HET1_16 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCI \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_A4_SHIFT ) ) +#define PINMUX_BALL_A4_ETPWM1SYNCO \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_A4_SHIFT ) ) + +#define PINMUX_BALL_A13_N2HET1_17 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_A13_EMIF_nOE \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_A13_SHIFT ) ) +#define PINMUX_BALL_A13_SCI4RX ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A13_SHIFT ) ) + +#define PINMUX_BALL_J1_N2HET1_18 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_EMIF_RNW ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J1_SHIFT ) ) +#define PINMUX_BALL_J1_eTPWM6A ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_J1_SHIFT ) ) + +#define PINMUX_BALL_B13_N2HET1_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_B13_EMIF_nDQM_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B13_SHIFT ) ) +#define PINMUX_BALL_B13_SCI4TX ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B13_SHIFT ) ) + +#define PINMUX_BALL_P2_N2HET1_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_EMIF_nDQM_1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P2_SHIFT ) ) +#define PINMUX_BALL_P2_eTPWM6B ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_P2_SHIFT ) ) + +#define PINMUX_BALL_H4_N2HET1_21 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_H4_SHIFT ) ) +#define PINMUX_BALL_H4_EMIF_nDQM_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_H4_SHIFT ) ) + +#define PINMUX_BALL_B3_N2HET1_22 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B3_SHIFT ) ) +#define PINMUX_BALL_B3_EMIF_nDQM_3 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_B3_SHIFT ) ) + +#define PINMUX_BALL_J4_N2HET1_23 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_J4_SHIFT ) ) +#define PINMUX_BALL_J4_EMIF_BA_0 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_J4_SHIFT ) ) + +#define PINMUX_BALL_P1_N2HET1_24 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MIBSPI1NCS_5 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_MII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_P1_SHIFT ) ) +#define PINMUX_BALL_P1_RMII_RXD_0 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_P1_SHIFT ) ) + +#define PINMUX_BALL_A14_N2HET1_26 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_MII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_A14_SHIFT ) ) +#define PINMUX_BALL_A14_RMII_RXD_1 \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_A14_SHIFT ) ) + +#define PINMUX_BALL_K19_N2HET1_28 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_RMII_REFCLK \ + ( ( uint32 ) ( ( uint32 ) 0x8U << PINMUX_BALL_K19_SHIFT ) ) +#define PINMUX_BALL_K19_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_K19_SHIFT ) ) + +#define PINMUX_BALL_B11_N2HET1_30 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_MII_RX_DV \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_BALL_B11_SHIFT ) ) +#define PINMUX_BALL_B11_eQEP2S \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_B11_SHIFT ) ) + +#define PINMUX_BALL_D8_N2HET2_01 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D8_SHIFT ) ) +#define PINMUX_BALL_D8_N2HET1_NDIS \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D8_SHIFT ) ) + +#define PINMUX_BALL_D7_N2HET2_02 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D7_SHIFT ) ) +#define PINMUX_BALL_D7_N2HET2_NDIS \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_D7_SHIFT ) ) + +#define PINMUX_BALL_D3_N2HET2_12 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_MIBSPI2NENA \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D3_SHIFT ) ) +#define PINMUX_BALL_D3_MIBSPI2NCS_1 \ + ( ( uint32 ) ( ( uint32 ) 0x20U << PINMUX_BALL_D3_SHIFT ) ) + +#define PINMUX_BALL_D2_N2HET2_13 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D2_SHIFT ) ) +#define PINMUX_BALL_D2_MIBSPI2SOMI \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D2_SHIFT ) ) + +#define PINMUX_BALL_D1_N2HET2_14 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_D1_SHIFT ) ) +#define PINMUX_BALL_D1_MIBSPI2SIMO \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_D1_SHIFT ) ) + +#define PINMUX_BALL_P4_N2HET2_19 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_P4_SHIFT ) ) +#define PINMUX_BALL_P4_LIN2RX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_P4_SHIFT ) ) + +#define PINMUX_BALL_T5_N2HET2_20 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T5_SHIFT ) ) +#define PINMUX_BALL_T5_LIN2TX ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_BALL_T5_SHIFT ) ) + +#define PINMUX_BALL_T4_MII_RXCLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_T4_SHIFT ) ) +#define PINMUX_BALL_T4_MII_RX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_T4_SHIFT ) ) + +#define PINMUX_BALL_U7_MII_TX_CLK \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_U7_SHIFT ) ) +#define PINMUX_BALL_U7_MII_TX_AVCLK4 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_U7_SHIFT ) ) + +#define PINMUX_BALL_E2_N2HET2_03 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_E2_SHIFT ) ) +#define PINMUX_BALL_E2_MIBSPI2CLK \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_E2_SHIFT ) ) + +#define PINMUX_BALL_N3_N2HET2_07 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_BALL_N3_SHIFT ) ) +#define PINMUX_BALL_N3_MIBSPI2NCS_0 \ + ( ( uint32 ) ( ( uint32 ) 0x10U << PINMUX_BALL_N3_SHIFT ) ) + +#define PINMUX_GATE_EMIF_CLK_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_GATE_EMIF_CLK_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GATE_EMIF_CLK_SHIFT ) ) +#define PINMUX_EMIF_OUTPUT_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EMIF_OUTPUT_ENABLE_SHIFT ) ) +#define PINMUX_GIOA_DISABLE_HET1_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA_DISABLE_HET1_SHIFT ) ) +#define PINMUX_GIOB_DISABLE_HET2_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB_DISABLE_HET2_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_1 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ALT_ADC_TRIGGER_2 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ALT_ADC_TRIGGER_SHIFT ) ) +#define PINMUX_ETHERNET_MII ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETHERNET_SHIFT ) ) +#define PINMUX_ETHERNET_RMII ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETHERNET_SHIFT ) ) + +#define PINMUX_ETPWM1_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM1_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM1_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM2_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM2_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM3_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM3_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM4_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM4_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM5_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM5_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM6_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM6_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR12 ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR1 ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM7_EQEPERR2 ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_ETPWM7_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TIME_BASE_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_TIME_BASE_SYNC_SHIFT ) ) +#define PINMUX_ETPWM_TBCLK_SYNC_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_TBCLK_SYNC_SHIFT ) ) +#define PINMUX_TZ1_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ1_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ1_SHIFT ) ) +#define PINMUX_TZ2_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ2_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ2_SHIFT ) ) +#define PINMUX_TZ3_ASYNC ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_SYNC ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_TZ3_FILTERED ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_TZ3_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_ASYNC \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_SYNC \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_EPWM1SYNCI_FILTERED \ + ( ( uint32 ) ( ( uint32 ) 0x4U << PINMUX_EPWM1SYNCI_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC2A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC2A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC3A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC3A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC4A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC4A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC5A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC5A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC6A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC6A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_ETPWM_SOC7A_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ETPWM_SOC7A_SHIFT ) ) +#define PINMUX_ETPWM_SOC1A_ON \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_ETPWM_SOC1A_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1A_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1A_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1B_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1B_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1I_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1I_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP1S_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP1S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2A_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2A_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2B_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2B_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2I_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2I_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_EQEP2S_FILTER_SHIFT ) ) +#define PINMUX_EQEP2S_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_EQEP2S_FILTER_SHIFT ) ) + +#define PINMUX_ECAP1_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP1_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP1_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP2_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP2_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP3_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP3_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP4_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP4_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP5_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP5_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_ECAP6_FILTER_SHIFT ) ) +#define PINMUX_ECAP6_FILTER_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_ECAP6_FILTER_SHIFT ) ) + +#define PINMUX_GIOA0_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA0_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA0_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA1_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA1_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA2_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA2_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA3_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA3_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA4_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA4_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA5_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA5_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA6_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA6_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOA7_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOA7_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB0_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB0_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB1_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB1_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB2_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB2_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB3_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB3_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB4_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB4_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB5_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB5_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB6_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB6_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_ON ( ( uint32 ) ( ( uint32 ) 0x0U << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_GIOB7_DMA_OFF ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_GIOB7_DMA_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP1_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP1_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP2_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP2_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_ON \ + ( ( uint32 ) ( ( uint32 ) 0x2U << PINMUX_TEMP3_ENABLE_SHIFT ) ) +#define PINMUX_TEMP3_ENABLE_OFF \ + ( ( uint32 ) ( ( uint32 ) 0x1U << PINMUX_TEMP3_ENABLE_SHIFT ) ) + +#define SIGNAL_AD2EVT_SHIFT 0U +#define SIGNAL_GIOA_0_SHIFT 24U +#define SIGNAL_GIOA_1_SHIFT 0U +#define SIGNAL_GIOA_2_SHIFT 8U +#define SIGNAL_GIOA_3_SHIFT 16U +#define SIGNAL_GIOA_4_SHIFT 24U +#define SIGNAL_GIOA_5_SHIFT 0U +#define SIGNAL_GIOA_6_SHIFT 8U +#define SIGNAL_GIOA_7_SHIFT 16U +#define SIGNAL_GIOB_0_SHIFT 24U +#define SIGNAL_GIOB_1_SHIFT 0U +#define SIGNAL_GIOB_2_SHIFT 8U +#define SIGNAL_GIOB_3_SHIFT 16U +#define SIGNAL_GIOB_4_SHIFT 24U +#define SIGNAL_GIOB_5_SHIFT 0U +#define SIGNAL_GIOB_6_SHIFT 8U +#define SIGNAL_GIOB_7_SHIFT 16U +#define SIGNAL_MDIO_SHIFT 24U +#define SIGNAL_MIBSPI1NCS_4_SHIFT 0U +#define SIGNAL_MIBSPI1NCS_5_SHIFT 8U +#define SIGNAL_MII_COL_SHIFT 16U +#define SIGNAL_MII_CRS_SHIFT 24U +#define SIGNAL_MII_RX_DV_SHIFT 0U +#define SIGNAL_MII_RX_ER_SHIFT 8U +#define SIGNAL_MII_RXCLK_SHIFT 16U +#define SIGNAL_MII_RXD_0_SHIFT 24U +#define SIGNAL_MII_RXD_1_SHIFT 0U +#define SIGNAL_MII_RXD_2_SHIFT 8U +#define SIGNAL_MII_RXD_3_SHIFT 16U +#define SIGNAL_MII_TX_CLK_SHIFT 24U +#define SIGNAL_N2HET1_17_SHIFT 0U +#define SIGNAL_N2HET1_19_SHIFT 8U +#define SIGNAL_N2HET1_21_SHIFT 16U +#define SIGNAL_N2HET1_23_SHIFT 24U +#define SIGNAL_N2HET1_25_SHIFT 0U +#define SIGNAL_N2HET1_27_SHIFT 8U +#define SIGNAL_N2HET1_29_SHIFT 16U +#define SIGNAL_N2HET1_31_SHIFT 24U +#define SIGNAL_N2HET2_00_SHIFT 0U +#define SIGNAL_N2HET2_01_SHIFT 8U +#define SIGNAL_N2HET2_02_SHIFT 16U +#define SIGNAL_N2HET2_03_SHIFT 24U +#define SIGNAL_N2HET2_04_SHIFT 0U +#define SIGNAL_N2HET2_05_SHIFT 8U +#define SIGNAL_N2HET2_06_SHIFT 16U +#define SIGNAL_N2HET2_07_SHIFT 24U +#define SIGNAL_N2HET2_08_SHIFT 0U +#define SIGNAL_N2HET2_09_SHIFT 8U +#define SIGNAL_N2HET2_10_SHIFT 16U +#define SIGNAL_N2HET2_11_SHIFT 24U +#define SIGNAL_N2HET2_12_SHIFT 0U +#define SIGNAL_N2HET2_13_SHIFT 8U +#define SIGNAL_N2HET2_14_SHIFT 16U +#define SIGNAL_N2HET2_15_SHIFT 24U +#define SIGNAL_N2HET2_16_SHIFT 0U +#define SIGNAL_N2HET2_18_SHIFT 8U +#define SIGNAL_N2HET2_20_SHIFT 16U +#define SIGNAL_N2HET2_22_SHIFT 24U +#define SIGNAL_nTZ1_1_SHIFT 0U +#define SIGNAL_nTZ1_2_SHIFT 8U +#define SIGNAL_nTZ1_3_SHIFT 16U + +#define SIGNAL_AD2EVT_T10 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_AD2EVT_SHIFT ) ) +#define SIGNAL_AD2EVT_V10 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_AD2EVT_SHIFT ) ) + +#define SIGNAL_GIOA_0_A5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_0_SHIFT ) ) +#define SIGNAL_GIOA_0_R5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_0_SHIFT ) ) + +#define SIGNAL_GIOA_1_C2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_1_SHIFT ) ) +#define SIGNAL_GIOA_1_R6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_1_SHIFT ) ) + +#define SIGNAL_GIOA_2_C1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_2_SHIFT ) ) +#define SIGNAL_GIOA_2_B15 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_2_SHIFT ) ) + +#define SIGNAL_GIOA_3_E1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_3_SHIFT ) ) +#define SIGNAL_GIOA_3_R7 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_3_SHIFT ) ) + +#define SIGNAL_GIOA_4_A6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_4_SHIFT ) ) +#define SIGNAL_GIOA_4_R8 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_4_SHIFT ) ) + +#define SIGNAL_GIOA_5_B5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_5_SHIFT ) ) +#define SIGNAL_GIOA_5_R9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_5_SHIFT ) ) + +#define SIGNAL_GIOA_6_H3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_6_SHIFT ) ) +#define SIGNAL_GIOA_6_R10 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_6_SHIFT ) ) + +#define SIGNAL_GIOA_7_M1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOA_7_SHIFT ) ) +#define SIGNAL_GIOA_7_R11 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOA_7_SHIFT ) ) + +#define SIGNAL_GIOB_0_M2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_0_SHIFT ) ) +#define SIGNAL_GIOB_0_B8 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_0_SHIFT ) ) + +#define SIGNAL_GIOB_1_K2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_1_SHIFT ) ) +#define SIGNAL_GIOB_1_B16 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_1_SHIFT ) ) + +#define SIGNAL_GIOB_2_F2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_2_SHIFT ) ) +#define SIGNAL_GIOB_2_B9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_2_SHIFT ) ) + +#define SIGNAL_GIOB_3_W10 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_3_SHIFT ) ) +#define SIGNAL_GIOB_3_R4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_3_SHIFT ) ) + +#define SIGNAL_GIOB_4_G1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_4_SHIFT ) ) +#define SIGNAL_GIOB_4_L17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_4_SHIFT ) ) + +#define SIGNAL_GIOB_5_G2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_5_SHIFT ) ) +#define SIGNAL_GIOB_5_M17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_5_SHIFT ) ) + +#define SIGNAL_GIOB_6_J2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_6_SHIFT ) ) +#define SIGNAL_GIOB_6_R3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_6_SHIFT ) ) + +#define SIGNAL_GIOB_7_F1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_GIOB_7_SHIFT ) ) +#define SIGNAL_GIOB_7_P3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_GIOB_7_SHIFT ) ) + +#define SIGNAL_MDIO_F4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MDIO_SHIFT ) ) +#define SIGNAL_MDIO_G3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MDIO_SHIFT ) ) + +#define SIGNAL_MIBSPI1NCS_4_U10 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MIBSPI1NCS_4_SHIFT ) ) +#define SIGNAL_MIBSPI1NCS_4_N1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MIBSPI1NCS_4_SHIFT ) ) + +#define SIGNAL_MIBSPI1NCS_5_U9 \ + ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MIBSPI1NCS_5_SHIFT ) ) +#define SIGNAL_MIBSPI1NCS_5_P1 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MIBSPI1NCS_5_SHIFT ) ) + +#define SIGNAL_MII_COL_W4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_COL_SHIFT ) ) +#define SIGNAL_MII_COL_F3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_COL_SHIFT ) ) + +#define SIGNAL_MII_CRS_V4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_CRS_SHIFT ) ) +#define SIGNAL_MII_CRS_B4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_CRS_SHIFT ) ) + +#define SIGNAL_MII_RX_DV_U6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RX_DV_SHIFT ) ) +#define SIGNAL_MII_RX_DV_B11 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RX_DV_SHIFT ) ) + +#define SIGNAL_MII_RX_ER_U5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RX_ER_SHIFT ) ) +#define SIGNAL_MII_RX_ER_N19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RX_ER_SHIFT ) ) + +#define SIGNAL_MII_RXCLK_T4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXCLK_SHIFT ) ) +#define SIGNAL_MII_RXCLK_K19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXCLK_SHIFT ) ) + +#define SIGNAL_MII_RXD_0_U4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_0_SHIFT ) ) +#define SIGNAL_MII_RXD_0_P1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_0_SHIFT ) ) + +#define SIGNAL_MII_RXD_1_T3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_1_SHIFT ) ) +#define SIGNAL_MII_RXD_1_A14 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_1_SHIFT ) ) + +#define SIGNAL_MII_RXD_2_U3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_2_SHIFT ) ) +#define SIGNAL_MII_RXD_2_G19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_2_SHIFT ) ) + +#define SIGNAL_MII_RXD_3_V3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_RXD_3_SHIFT ) ) +#define SIGNAL_MII_RXD_3_H18 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_RXD_3_SHIFT ) ) + +#define SIGNAL_MII_TX_CLK_U7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_MII_TX_CLK_SHIFT ) ) +#define SIGNAL_MII_TX_CLK_D19 \ + ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_MII_TX_CLK_SHIFT ) ) + +#define SIGNAL_N2HET1_17_A13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_17_SHIFT ) ) +#define SIGNAL_N2HET1_17_F3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_17_SHIFT ) ) + +#define SIGNAL_N2HET1_19_B13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_19_SHIFT ) ) +#define SIGNAL_N2HET1_19_G3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_19_SHIFT ) ) + +#define SIGNAL_N2HET1_21_H4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_21_SHIFT ) ) +#define SIGNAL_N2HET1_21_J3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_21_SHIFT ) ) + +#define SIGNAL_N2HET1_23_J4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_23_SHIFT ) ) +#define SIGNAL_N2HET1_23_G19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_23_SHIFT ) ) + +#define SIGNAL_N2HET1_25_M3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_25_SHIFT ) ) +#define SIGNAL_N2HET1_25_V5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_25_SHIFT ) ) + +#define SIGNAL_N2HET1_27_A9 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_27_SHIFT ) ) +#define SIGNAL_N2HET1_27_B2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_27_SHIFT ) ) + +#define SIGNAL_N2HET1_29_A3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_29_SHIFT ) ) +#define SIGNAL_N2HET1_29_C3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_29_SHIFT ) ) + +#define SIGNAL_N2HET1_31_J17 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET1_31_SHIFT ) ) +#define SIGNAL_N2HET1_31_W9 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET1_31_SHIFT ) ) + +#define SIGNAL_N2HET2_00_D6 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_00_SHIFT ) ) +#define SIGNAL_N2HET2_00_C1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_00_SHIFT ) ) + +#define SIGNAL_N2HET2_01_D8 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_01_SHIFT ) ) +#define SIGNAL_N2HET2_01_D4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_01_SHIFT ) ) + +#define SIGNAL_N2HET2_02_D7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_02_SHIFT ) ) +#define SIGNAL_N2HET2_02_E1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_02_SHIFT ) ) + +#define SIGNAL_N2HET2_03_E2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_03_SHIFT ) ) +#define SIGNAL_N2HET2_03_D5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_03_SHIFT ) ) + +#define SIGNAL_N2HET2_04_D13 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_04_SHIFT ) ) +#define SIGNAL_N2HET2_04_H3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_04_SHIFT ) ) + +#define SIGNAL_N2HET2_05_D12 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_05_SHIFT ) ) +#define SIGNAL_N2HET2_05_D16 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_05_SHIFT ) ) + +#define SIGNAL_N2HET2_06_D11 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_06_SHIFT ) ) +#define SIGNAL_N2HET2_06_M1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_06_SHIFT ) ) + +#define SIGNAL_N2HET2_07_N3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_07_SHIFT ) ) +#define SIGNAL_N2HET2_07_N17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_07_SHIFT ) ) + +#define SIGNAL_N2HET2_08_K16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_08_SHIFT ) ) +#define SIGNAL_N2HET2_08_V2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_08_SHIFT ) ) + +#define SIGNAL_N2HET2_09_L16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_09_SHIFT ) ) +#define SIGNAL_N2HET2_09_K17 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_09_SHIFT ) ) + +#define SIGNAL_N2HET2_10_M16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_10_SHIFT ) ) +#define SIGNAL_N2HET2_10_U1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_10_SHIFT ) ) + +#define SIGNAL_N2HET2_11_N16 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_11_SHIFT ) ) +#define SIGNAL_N2HET2_11_C4 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_11_SHIFT ) ) + +#define SIGNAL_N2HET2_12_D3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_12_SHIFT ) ) +#define SIGNAL_N2HET2_12_V6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_12_SHIFT ) ) + +#define SIGNAL_N2HET2_13_D2 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_13_SHIFT ) ) +#define SIGNAL_N2HET2_13_C5 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_13_SHIFT ) ) + +#define SIGNAL_N2HET2_14_D1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_14_SHIFT ) ) +#define SIGNAL_N2HET2_14_T1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_14_SHIFT ) ) + +#define SIGNAL_N2HET2_15_K4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_15_SHIFT ) ) +#define SIGNAL_N2HET2_15_C6 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_15_SHIFT ) ) + +#define SIGNAL_N2HET2_16_L4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_16_SHIFT ) ) +#define SIGNAL_N2HET2_16_V7 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_16_SHIFT ) ) + +#define SIGNAL_N2HET2_18_N4 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_18_SHIFT ) ) +#define SIGNAL_N2HET2_18_E3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_18_SHIFT ) ) + +#define SIGNAL_N2HET2_20_T5 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_20_SHIFT ) ) +#define SIGNAL_N2HET2_20_N2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_20_SHIFT ) ) + +#define SIGNAL_N2HET2_22_T7 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_N2HET2_22_SHIFT ) ) +#define SIGNAL_N2HET2_22_N1 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_N2HET2_22_SHIFT ) ) + +#define SIGNAL_nTZ1_1_N19 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_1_SHIFT ) ) +#define SIGNAL_nTZ1_1_C3 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_1_SHIFT ) ) + +#define SIGNAL_nTZ1_2_F1 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_2_SHIFT ) ) +#define SIGNAL_nTZ1_2_B2 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_2_SHIFT ) ) + +#define SIGNAL_nTZ1_3_J3 ( ( uint32 ) ( ( uint32 ) 0x1U << SIGNAL_nTZ1_3_SHIFT ) ) +#define SIGNAL_nTZ1_3_D19 ( ( uint32 ) ( ( uint32 ) 0x2U << SIGNAL_nTZ1_3_SHIFT ) ) + +/** @fn void muxInit(void) + * @brief Initializes the PINMUX Driver + * + * This function initializes the PINMUX module and configures the selected + * pinmux settings as per the user selection in the GUI + */ +void muxInit( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h new file mode 100644 index 00000000000..bedac83e298 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/pom.h @@ -0,0 +1,339 @@ +/** @file pom.h + * @brief POM Driver Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __POM_H__ +#define __POM_H__ + +#include "reg_pom.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pom_region_size + * @brief Alias names for pom region size + * This enumeration is used to provide alias names for POM region size: + */ +enum pom_region_size +{ + SIZE_32BYTES = 0U, + SIZE_64BYTES = 1U, + SIZE_128BYTES = 2U, + SIZE_256BYTES = 3U, + SIZE_512BYTES = 4U, + SIZE_1KB = 5U, + SIZE_2KB = 6U, + SIZE_4KB = 7U, + SIZE_8KB = 8U, + SIZE_16KB = 9U, + SIZE_32KB = 10U, + SIZE_64KB = 11U, + SIZE_128KB = 12U, + SIZE_256KB = 13U +}; + +/** @def INTERNAL_RAM + * @brief Alias name for Internal RAM + */ +#define INTERNAL_RAM 0x08000000U + +/** @def SDRAM + * @brief Alias name for SD RAM + */ +#define SDRAM 0x80000000U + +/** @def ASYNC_MEMORY + * @brief Alias name for Async RAM + */ +#define ASYNC_MEMORY 0x60000000U + +typedef uint32 REGION_t; + +/** @struct REGION_CONFIG_ST + * @brief POM region configuration + */ +typedef struct +{ + uint32 Prog_Reg_Sta_Addr; + uint32 Ovly_Reg_Sta_Addr; + uint32 Reg_Size; +} REGION_CONFIG_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Configuration registers */ +typedef struct pom_config_reg +{ + uint32 CONFIG_POMGLBCTRL; + uint32 CONFIG_POMPROGSTART0; + uint32 CONFIG_POMOVLSTART0; + uint32 CONFIG_POMREGSIZE0; + uint32 CONFIG_POMPROGSTART1; + uint32 CONFIG_POMOVLSTART1; + uint32 CONFIG_POMREGSIZE1; + uint32 CONFIG_POMPROGSTART2; + uint32 CONFIG_POMOVLSTART2; + uint32 CONFIG_POMREGSIZE2; + uint32 CONFIG_POMPROGSTART3; + uint32 CONFIG_POMOVLSTART3; + uint32 CONFIG_POMREGSIZE3; + uint32 CONFIG_POMPROGSTART4; + uint32 CONFIG_POMOVLSTART4; + uint32 CONFIG_POMREGSIZE4; + uint32 CONFIG_POMPROGSTART5; + uint32 CONFIG_POMOVLSTART5; + uint32 CONFIG_POMREGSIZE5; + uint32 CONFIG_POMPROGSTART6; + uint32 CONFIG_POMOVLSTART6; + uint32 CONFIG_POMREGSIZE6; + uint32 CONFIG_POMPROGSTART7; + uint32 CONFIG_POMOVLSTART7; + uint32 CONFIG_POMREGSIZE7; + uint32 CONFIG_POMPROGSTART8; + uint32 CONFIG_POMOVLSTART8; + uint32 CONFIG_POMREGSIZE8; + uint32 CONFIG_POMPROGSTART9; + uint32 CONFIG_POMOVLSTART9; + uint32 CONFIG_POMREGSIZE9; + uint32 CONFIG_POMPROGSTART10; + uint32 CONFIG_POMOVLSTART10; + uint32 CONFIG_POMREGSIZE10; + uint32 CONFIG_POMPROGSTART11; + uint32 CONFIG_POMOVLSTART11; + uint32 CONFIG_POMREGSIZE11; + uint32 CONFIG_POMPROGSTART12; + uint32 CONFIG_POMOVLSTART12; + uint32 CONFIG_POMREGSIZE12; + uint32 CONFIG_POMPROGSTART13; + uint32 CONFIG_POMOVLSTART13; + uint32 CONFIG_POMREGSIZE13; + uint32 CONFIG_POMPROGSTART14; + uint32 CONFIG_POMOVLSTART14; + uint32 CONFIG_POMREGSIZE14; + uint32 CONFIG_POMPROGSTART15; + uint32 CONFIG_POMOVLSTART15; + uint32 CONFIG_POMREGSIZE15; + uint32 CONFIG_POMPROGSTART16; + uint32 CONFIG_POMOVLSTART16; + uint32 CONFIG_POMREGSIZE16; + uint32 CONFIG_POMPROGSTART17; + uint32 CONFIG_POMOVLSTART17; + uint32 CONFIG_POMREGSIZE17; + uint32 CONFIG_POMPROGSTART18; + uint32 CONFIG_POMOVLSTART18; + uint32 CONFIG_POMREGSIZE18; + uint32 CONFIG_POMPROGSTART19; + uint32 CONFIG_POMOVLSTART19; + uint32 CONFIG_POMREGSIZE19; + uint32 CONFIG_POMPROGSTART20; + uint32 CONFIG_POMOVLSTART20; + uint32 CONFIG_POMREGSIZE20; + uint32 CONFIG_POMPROGSTART21; + uint32 CONFIG_POMOVLSTART21; + uint32 CONFIG_POMREGSIZE21; + uint32 CONFIG_POMPROGSTART22; + uint32 CONFIG_POMOVLSTART22; + uint32 CONFIG_POMREGSIZE22; + uint32 CONFIG_POMPROGSTART23; + uint32 CONFIG_POMOVLSTART23; + uint32 CONFIG_POMREGSIZE23; + uint32 CONFIG_POMPROGSTART24; + uint32 CONFIG_POMOVLSTART24; + uint32 CONFIG_POMREGSIZE24; + uint32 CONFIG_POMPROGSTART25; + uint32 CONFIG_POMOVLSTART25; + uint32 CONFIG_POMREGSIZE25; + uint32 CONFIG_POMPROGSTART26; + uint32 CONFIG_POMOVLSTART26; + uint32 CONFIG_POMREGSIZE26; + uint32 CONFIG_POMPROGSTART27; + uint32 CONFIG_POMOVLSTART27; + uint32 CONFIG_POMREGSIZE27; + uint32 CONFIG_POMPROGSTART28; + uint32 CONFIG_POMOVLSTART28; + uint32 CONFIG_POMREGSIZE28; + uint32 CONFIG_POMPROGSTART29; + uint32 CONFIG_POMOVLSTART29; + uint32 CONFIG_POMREGSIZE29; + uint32 CONFIG_POMPROGSTART30; + uint32 CONFIG_POMOVLSTART30; + uint32 CONFIG_POMREGSIZE30; + uint32 CONFIG_POMPROGSTART31; + uint32 CONFIG_POMOVLSTART31; + uint32 CONFIG_POMREGSIZE31; +} pom_config_reg_t; + +/* Configuration registers initial value for POM*/ +#define POM_POMGLBCTRL_CONFIGVALUE ( ( uint32 ) INTERNAL_RAM | 0x00000005U ) +#define POM_POMPROGSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU ) +#define POM_POMOVLSTART0_CONFIGVALUE ( 0x00000000U & 0x003FFFFFU ) +/*SAFETYMCUSW 79 S MR:19.4 "Values come from GUI drop down option" */ +#define POM_POMREGSIZE0_CONFIGVALUE ( ( uint32 ) SIZE_64BYTES ) +#define POM_POMPROGSTART1_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART1_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE1_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART2_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART2_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE2_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART3_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART3_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE3_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART4_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART4_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE4_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART5_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART5_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE5_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART6_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART6_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE6_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART7_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART7_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE7_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART8_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART8_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE8_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART9_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART9_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE9_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART10_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART10_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE10_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART11_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART11_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE11_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART12_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART12_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE12_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART13_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART13_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE13_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART14_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART14_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE14_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART15_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART15_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE15_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART16_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART16_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE16_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART17_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART17_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE17_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART18_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART18_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE18_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART19_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART19_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE19_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART20_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART20_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE20_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART21_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART21_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE21_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART22_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART22_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE22_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART23_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART23_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE23_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART24_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART24_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE24_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART25_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART25_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE25_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART26_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART26_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE26_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART27_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART27_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE27_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART28_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART28_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE28_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART29_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART29_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE29_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART30_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART30_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE30_CONFIGVALUE 0x00000000U +#define POM_POMPROGSTART31_CONFIGVALUE 0x00000000U +#define POM_POMOVLSTART31_CONFIGVALUE 0x00000000U +#define POM_POMREGSIZE31_CONFIGVALUE 0x00000000U + +/** + * @defgroup POM POM + * @brief Parameter Overlay Module. + * + * The POM provides a mechanism to redirect accesses to non-volatile memory into a + * volatile memory internal or external to the device. The data requested by the CPU will + * be fetched from the overlay memory instead of the main non-volatile memory. + * + * Related Files + * - reg_pom.h + * - pom.h + * - pom.c + * @addtogroup POM + * @{ + */ + +/* POM Interface Functions */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ); +void POM_Reset( void ); +void POM_Init( void ); +void POM_Enable( void ); +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* __POM_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h new file mode 100644 index 00000000000..1e8f755d94b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_adc.h @@ -0,0 +1,252 @@ +/** @file reg_adc.h + * @brief ADC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ADC_H__ +#define __REG_ADC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Adc Register Frame Definition */ +/** @struct adcBase + * @brief ADC Register Frame Definition + * + * This type is used to access the ADC Registers. + */ +/** @typedef adcBASE_t + * @brief ADC Register Frame Type Definition + * + * This type is used to access the ADC Registers. + */ +typedef volatile struct adcBase +{ + uint32 RSTCR; /**< 0x0000: Reset control register */ + uint32 OPMODECR; /**< 0x0004: Operating mode control register */ + uint32 CLOCKCR; /**< 0x0008: Clock control register */ + uint32 CALCR; /**< 0x000C: Calibration control register */ + uint32 GxMODECR[ 3U ]; /**< 0x0010,0x0014,0x0018: Group 0-2 mode control register */ + uint32 EVSRC; /**< 0x001C: Group 0 trigger source control register */ + uint32 G1SRC; /**< 0x0020: Group 1 trigger source control register */ + uint32 G2SRC; /**< 0x0024: Group 2 trigger source control register */ + uint32 GxINTENA[ 3U ]; /**< 0x0028,0x002C,0x0030: Group 0-2 interrupt enable register + */ + uint32 GxINTFLG[ 3U ]; /**< 0x0034,0x0038,0x003C: Group 0-2 interrupt flag register */ + uint32 GxINTCR[ 3U ]; /**< 0x0040-0x0048: Group 0-2 interrupt threshold register */ + uint32 EVDMACR; /**< 0x004C: Group 0 DMA control register */ + uint32 G1DMACR; /**< 0x0050: Group 1 DMA control register */ + uint32 G2DMACR; /**< 0x0054: Group 2 DMA control register */ + uint32 BNDCR; /**< 0x0058: Buffer boundary control register */ + uint32 BNDEND; /**< 0x005C: Buffer boundary end register */ + uint32 EVSAMP; /**< 0x0060: Group 0 sample window register */ + uint32 G1SAMP; /**< 0x0064: Group 1 sample window register */ + uint32 G2SAMP; /**< 0x0068: Group 2 sample window register */ + uint32 EVSR; /**< 0x006C: Group 0 status register */ + uint32 G1SR; /**< 0x0070: Group 1 status register */ + uint32 G2SR; /**< 0x0074: Group 2 status register */ + uint32 GxSEL[ 3U ]; /**< 0x0078-0x007C: Group 0-2 channel select register */ + uint32 CALR; /**< 0x0084: Calibration register */ + uint32 SMSTATE; /**< 0x0088: State machine state register */ + uint32 LASTCONV; /**< 0x008C: Last conversion register */ + struct + { + uint32 BUF0; /**< 0x0090,0x00B0,0x00D0: Group 0-2 result buffer 1 register */ + uint32 BUF1; /**< 0x0094,0x00B4,0x00D4: Group 0-2 result buffer 1 register */ + uint32 BUF2; /**< 0x0098,0x00B8,0x00D8: Group 0-2 result buffer 2 register */ + uint32 BUF3; /**< 0x009C,0x00BC,0x00DC: Group 0-2 result buffer 3 register */ + uint32 BUF4; /**< 0x00A0,0x00C0,0x00E0: Group 0-2 result buffer 4 register */ + uint32 BUF5; /**< 0x00A4,0x00C4,0x00E4: Group 0-2 result buffer 5 register */ + uint32 BUF6; /**< 0x00A8,0x00C8,0x00E8: Group 0-2 result buffer 6 register */ + uint32 BUF7; /**< 0x00AC,0x00CC,0x00EC: Group 0-2 result buffer 7 register */ + } GxBUF[ 3U ]; + uint32 EVEMUBUFFER; /**< 0x00F0: Group 0 emulation result buffer */ + uint32 G1EMUBUFFER; /**< 0x00F4: Group 1 emulation result buffer */ + uint32 G2EMUBUFFER; /**< 0x00F8: Group 2 emulation result buffer */ + uint32 EVTDIR; /**< 0x00FC: Event pin direction register */ + uint32 EVTOUT; /**< 0x0100: Event pin digital output register */ + uint32 EVTIN; /**< 0x0104: Event pin digital input register */ + uint32 EVTSET; /**< 0x0108: Event pin set register */ + uint32 EVTCLR; /**< 0x010C: Event pin clear register */ + uint32 EVTPDR; /**< 0x0110: Event pin open drain register */ + uint32 EVTDIS; /**< 0x0114: Event pin pull disable register */ + uint32 EVTPSEL; /**< 0x0118: Event pin pull select register */ + uint32 EVSAMPDISEN; /**< 0x011C: Group 0 sample discharge register */ + uint32 G1SAMPDISEN; /**< 0x0120: Group 1 sample discharge register */ + uint32 G2SAMPDISEN; /**< 0x0124: Group 2 sample discharge register */ + uint32 MAGINTCR1; /**< 0x0128: Magnitude interrupt control register 1 */ + uint32 MAGINT1MASK; /**< 0x012C: Magnitude interrupt mask register 1 */ + uint32 MAGINTCR2; /**< 0x0130: Magnitude interrupt control register 2 */ + uint32 MAGINT2MASK; /**< 0x0134: Magnitude interrupt mask register 2 */ + uint32 MAGINTCR3; /**< 0x0138: Magnitude interrupt control register 3 */ + uint32 MAGINT3MASK; /**< 0x013C: Magnitude interrupt mask register 3 */ + uint32 rsvd1; /**< 0x0140: Reserved */ + uint32 rsvd2; /**< 0x0144: Reserved */ + uint32 rsvd3; /**< 0x0148: Reserved */ + uint32 rsvd4; /**< 0x014C: Reserved */ + uint32 rsvd5; /**< 0x0150: Reserved */ + uint32 rsvd6; /**< 0x0154: Reserved */ + uint32 MAGTHRINTENASET; /**< 0x0158: Magnitude interrupt set register */ + uint32 MAGTHRINTENACLR; /**< 0x015C: Magnitude interrupt clear register */ + uint32 MAGTHRINTFLG; /**< 0x0160: Magnitude interrupt flag register */ + uint32 MAGTHRINTOFFSET; /**< 0x0164: Magnitude interrupt offset register */ + uint32 GxFIFORESETCR[ 3U ]; /**< 0x0168,0x016C,0x0170: Group 0-2 fifo reset register + */ + uint32 EVRAMADDR; /**< 0x0174: Group 0 RAM pointer register */ + uint32 G1RAMADDR; /**< 0x0178: Group 1 RAM pointer register */ + uint32 G2RAMADDR; /**< 0x017C: Group 2 RAM pointer register */ + uint32 PARCR; /**< 0x0180: Parity control register */ + uint32 PARADDR; /**< 0x0184: Parity error address register */ + uint32 PWRUPDLYCTRL; /**< 0x0188: Power-Up delay control register */ + uint32 rsvd7; /**< 0x018C: Reserved */ + uint32 ADEVCHNSELMODECTRL; /**< 0x0190: Event Group Channel Selection Mode Control + Register */ + uint32 ADG1CHNSELMODECTRL; /**< 0x0194: Group1 Channel Selection Mode Control Register + */ + uint32 ADG2CHNSELMODECTRL; /**< 0x0198: Group2 Channel Selection Mode Control Register + */ + uint32 ADEVCURRCOUNT; /**< 0x019C: Event Group Current Count Register */ + uint32 ADEVMAXCOUNT; /**< 0x01A0: Event Group Max Count Register */ + uint32 ADG1CURRCOUNT; /**< 0x01A4: Group1 Current Count Register */ + uint32 ADG1MAXCOUNT; /**< 0x01A8: Group1 Max Count Register */ + uint32 ADG2CURRCOUNT; /**< 0x01AC: Group2 Current Count Register */ + uint32 ADG2MAXCOUNT; /**< 0x01B0: Group2 Max Count Register */ +} adcBASE_t; + +/** @struct adcLUTEntry + * @brief ADC Look-Up Table Entry + * + * This type is used to access ADC Look-Up Table Entry + */ +/** @typedef adcLUTEntry_t + * @brief ADC Look-Up Table Entry + * + * This type is used to access the Look-Up Table Entry. + */ +typedef struct adcLUTEntry +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 EV_INT_CHN_MUX_SEL; + uint8 EV_EXT_CHN_MUX_SEL; + uint16 rsvd; +#else + uint16 rsvd; + uint8 EV_EXT_CHN_MUX_SEL; + uint8 EV_INT_CHN_MUX_SEL; +#endif +} adcLUTEntry_t; + +/** @struct adcLUT + * @brief ADC Look-Up Table + * + * This type is used to access ADC Look-Up Table + */ +/** @typedef adcLUT_t + * @brief ADC Look-Up Table + * + * This type is used to access the ADC Look-Up Table. + */ +typedef volatile struct adcLUT +{ + adcLUTEntry_t eventGroup[ 32 ]; + adcLUTEntry_t Group1[ 32 ]; + adcLUTEntry_t Group2[ 32 ]; +} adcLUT_t; + +/** @def adcREG1 + * @brief ADC1 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC1 registers. + */ +#define adcREG1 ( ( adcBASE_t * ) 0xFFF7C000U ) + +/** @def adcREG2 + * @brief ADC2 Register Frame Pointer + * + * This pointer is used by the ADC driver to access the ADC2 registers. + */ +#define adcREG2 ( ( adcBASE_t * ) 0xFFF7C200U ) + +/** @def adcRAM1 + * @brief ADC1 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 RAM. + */ +#define adcRAM1 ( *( volatile uint32 * ) 0xFF3E0000U ) + +/** @def adcRAM2 + * @brief ADC2 RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 RAM. + */ +#define adcRAM2 ( *( volatile uint32 * ) 0xFF3A0000U ) + +/** @def adcPARRAM1 + * @brief ADC1 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC1 Parity RAM. + */ +#define adcPARRAM1 ( *( volatile uint32 * ) ( 0xFF3E0000U + 0x1000U ) ) + +/** @def adcPARRAM2 + * @brief ADC2 Parity RAM Pointer + * + * This pointer is used by the ADC driver to access the ADC2 Parity RAM. + */ +#define adcPARRAM2 ( *( volatile uint32 * ) ( 0xFF3A0000U + 0x1000U ) ) + +/** @def adcLUT1 + * @brief ADC1 Look-Up Table + * + * This pointer is used by the ADC driver to access the ADC1 Look-Up Table. + */ +#define adcLUT1 ( ( adcLUT_t * ) ( 0xFF3E0000U + 0x2000U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h new file mode 100644 index 00000000000..2bb705c66cb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_can.h @@ -0,0 +1,230 @@ +/** @file reg_can.h + * @brief CAN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CAN_H__ +#define __REG_CAN_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Can Register Frame Definition */ +/** @struct canBase + * @brief CAN Register Frame Definition + * + * This type is used to access the CAN Registers. + */ +/** @typedef canBASE_t + * @brief CAN Register Frame Type Definition + * + * This type is used to access the CAN Registers. + */ +typedef volatile struct canBase +{ + uint32 CTL; /**< 0x0000: Control Register */ + uint32 ES; /**< 0x0004: Error and Status Register */ + uint32 EERC; /**< 0x0008: Error Counter Register */ + uint32 BTR; /**< 0x000C: Bit Timing Register */ + uint32 INT; /**< 0x0010: Interrupt Register */ + uint32 TEST; /**< 0x0014: Test Register */ + uint32 rsvd1; /**< 0x0018: Reserved */ + uint32 PERR; /**< 0x001C: Parity/SECDED Error Code Register */ + uint32 rsvd11; /**< 0x0020: Reserved */ + uint32 ECCDIAG; /**< 0x0024: ECC Diagnostic Register */ + uint32 ECCDIAG_STAT; /**< 0x0028: ECC Diagnostic Status Register */ + uint32 ECC_CS; /**< 0x002C: ECC Control and Status Register */ + uint32 ECC_SERR; /**< 0x0030: ECC Single Bit Error code register */ + uint32 rsvd2[ 19 ]; /**< 0x002C - 0x7C: Reserved */ + uint32 ABOTR; /**< 0x0080: Auto Bus On Time Register */ + uint32 TXRQX; /**< 0x0084: Transmission Request X Register */ + uint32 TXRQx[ 4U ]; /**< 0x0088-0x0094: Transmission Request Registers */ + uint32 NWDATX; /**< 0x0098: New Data X Register */ + uint32 NWDATx[ 4U ]; /**< 0x009C-0x00A8: New Data Registers */ + uint32 INTPNDX; /**< 0x00AC: Interrupt Pending X Register */ + uint32 INTPNDx[ 4U ]; /**< 0x00B0-0x00BC: Interrupt Pending Registers */ + uint32 MSGVALX; /**< 0x00C0: Message Valid X Register */ + uint32 MSGVALx[ 4U ]; /**< 0x00C4-0x00D0: Message Valid Registers */ + uint32 rsvd3; /**< 0x00D4: Reserved */ + uint32 INTMUXx[ 4U ]; /**< 0x00D8-0x00E4: Interrupt Multiplexer Registers */ + uint32 rsvd4[ 6 ]; /**< 0x00E8: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ +#else + uint8 rsvd9; /**< 0x0100: IF1 Command Register, Reserved */ + uint8 IF1CMD; /**< 0x0100: IF1 Command Register, Command */ + uint8 IF1STAT; /**< 0x0100: IF1 Command Register, Status */ + uint8 IF1NO; /**< 0x0100: IF1 Command Register, Msg Number */ +#endif + uint32 IF1MSK; /**< 0x0104: IF1 Mask Register */ + uint32 IF1ARB; /**< 0x0108: IF1 Arbitration Register */ + uint32 IF1MCTL; /**< 0x010C: IF1 Message Control Register */ + uint8 IF1DATx[ 8U ]; /**< 0x0110-0x0114: IF1 Data A and B Registers */ + uint32 rsvd5[ 2 ]; /**< 0x0118: Reserved */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg No */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ +#else + uint8 rsvd10; /**< 0x0120: IF2 Command Register, Reserved */ + uint8 IF2CMD; /**< 0x0120: IF2 Command Register, Command */ + uint8 IF2STAT; /**< 0x0120: IF2 Command Register, Status */ + uint8 IF2NO; /**< 0x0120: IF2 Command Register, Msg Number */ +#endif + uint32 IF2MSK; /**< 0x0124: IF2 Mask Register */ + uint32 IF2ARB; /**< 0x0128: IF2 Arbitration Register */ + uint32 IF2MCTL; /**< 0x012C: IF2 Message Control Register */ + uint8 IF2DATx[ 8U ]; /**< 0x0130-0x0134: IF2 Data A and B Registers */ + uint32 rsvd6[ 2 ]; /**< 0x0138: Reserved */ + uint32 IF3OBS; /**< 0x0140: IF3 Observation Register */ + uint32 IF3MSK; /**< 0x0144: IF3 Mask Register */ + uint32 IF3ARB; /**< 0x0148: IF3 Arbitration Register */ + uint32 IF3MCTL; /**< 0x014C: IF3 Message Control Register */ + uint8 IF3DATx[ 8U ]; /**< 0x0150-0x0154: IF3 Data A and B Registers */ + uint32 rsvd7[ 2 ]; /**< 0x0158: Reserved */ + uint32 IF3UEy[ 4U ]; /**< 0x0160-0x016C: IF3 Update Enable Registers */ + uint32 rsvd8[ 28 ]; /**< 0x0170: Reserved */ + uint32 TIOC; /**< 0x01E0: TX IO Control Register */ + uint32 RIOC; /**< 0x01E4: RX IO Control Register */ +} canBASE_t; + +/** @def canREG1 + * @brief CAN1 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN1 registers. + */ +#define canREG1 ( ( canBASE_t * ) 0xFFF7DC00U ) + +/** @def canREG2 + * @brief CAN2 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN2 registers. + */ +#define canREG2 ( ( canBASE_t * ) 0xFFF7DE00U ) + +/** @def canREG3 + * @brief CAN3 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN3 registers. + */ +#define canREG3 ( ( canBASE_t * ) 0xFFF7E000U ) + +/** @def canREG4 + * @brief CAN4 Register Frame Pointer + * + * This pointer is used by the CAN driver to access the CAN4 registers. + */ +#define canREG4 ( ( canBASE_t * ) 0xFFF7E200U ) + +/** @def canRAM1 + * @brief CAN1 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 RAM. + */ +#define canRAM1 ( *( volatile uint32 * ) 0xFF1E0000U ) + +/** @def canRAM2 + * @brief CAN2 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 RAM. + */ +#define canRAM2 ( *( volatile uint32 * ) 0xFF1C0000U ) + +/** @def canRAM3 + * @brief CAN3 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 RAM. + */ +#define canRAM3 ( *( volatile uint32 * ) 0xFF1A0000U ) + +/** @def canRAM4 + * @brief CAN4 Mailbox RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN4 RAM. + */ +#define canRAM4 ( *( volatile uint32 * ) 0xFF180000U ) + +/** @def canPARRAM1 + * @brief CAN1 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN1 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM1 ( *( volatile uint32 * ) ( 0xFF1E0000U + 0x10U ) ) + +/** @def canPARRAM2 + * @brief CAN2 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN2 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM2 ( *( volatile uint32 * ) ( 0xFF1C0000U + 0x10U ) ) + +/** @def canPARRAM3 + * @brief CAN3 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN3 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM3 ( *( volatile uint32 * ) ( 0xFF1A0000U + 0x10U ) ) + +/** @def canPARRAM4 + * @brief CAN4 Mailbox Parity RAM Pointer + * + * This pointer is used by the CAN driver to access the CAN4 Parity RAM + * for testing RAM parity error detect logic. + */ +#define canPARRAM4 ( *( volatile uint32 * ) ( 0xFF180000U + 0x10U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h new file mode 100644 index 00000000000..6a7b66a4ab5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ccmr5.h @@ -0,0 +1,84 @@ +/** @file reg_ccmr5.h + * @brief CCMR5 Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CCMR5_H__ +#define __REG_CCMR5_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ +/** @struct ccmr5Base + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ +/** @typedef ccmr5BASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct ccmr5Base +{ + uint32 CCMSR1; /* 0x00 Status Register 1 */ + uint32 CCMKEYR1; /* 0x04 Key Register 1 */ + uint32 CCMSR2; /* 0x08 Status Register 2 */ + uint32 CCMKEYR2; /* 0x0C Key Register 2 */ + uint32 CCMSR3; /* 0x10 Status Register 3 */ + uint32 CCMKEYR3; /* 0x14 Key Register 3 */ + uint32 CCMPOLCNTRL; /* 0x18 Polarity Control Register */ + uint32 CCMSR4; /* 0x1C Status Register 4 */ + uint32 CCMKEYR4; /* 0x20 Key Register 4 */ + uint32 CCMPDSTAT0; /* 0x24 Power Domain Status Register 0 */ +} ccmr5BASE_t; + +#define ccmr5REG ( ( ccmr5BASE_t * ) 0xFFFFF600U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h new file mode 100644 index 00000000000..fe70e50d066 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_crc.h @@ -0,0 +1,132 @@ +/** @file reg_crc.h + * @brief CRC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_CRC_H__ +#define __REG_CRC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Crc Register Frame Definition */ +/** @struct crcBase + * @brief CRC Register Frame Definition + * + * This type is used to access the CRC Registers. + */ +/** @typedef crcBASE_t + * @brief CRC Register Frame Type Definition + * + * This type is used to access the CRC Registers. + */ +typedef volatile struct crcBase +{ + uint32 CTRL0; /**< 0x0000: Global Control Register 0 >**/ + uint32 rvd1; /**< 0x0004: reserved >**/ + uint32 CTRL1; /**< 0x0008: Global Control Register 1 >**/ + uint32 rvd2; /**< 0x000C: reserved >**/ + uint32 CTRL2; /**< 0x0010: Global Control Register 2 >**/ + uint32 rvd3; /**< 0x0014: reserved >**/ + uint32 INTS; /**< 0x0018: Interrupt Enable Set Register >**/ + uint32 rvd4; /**< 0x001C: reserved >**/ + uint32 INTR; /**< 0x0020: Interrupt Enable Reset Register >**/ + uint32 rvd5; /**< 0x0024: reserved >**/ + uint32 STATUS; /**< 0x0028: Interrupt Status Register >**/ + uint32 rvd6; /**< 0x002C: reserved >**/ + uint32 INT_OFFSET_REG; /**< 0x0030: Interrupt Offset >**/ + uint32 rvd7; /**< 0x0034: reserved >**/ + uint32 BUSY; /**< 0x0038: CRC Busy Register >**/ + uint32 rvd8; /**< 0x003C: reserved >**/ + uint32 PCOUNT_REG1; /**< 0x0040: Pattern Counter Preload Register1 >**/ + uint32 SCOUNT_REG1; /**< 0x0044: Sector Counter Preload Register1 >**/ + uint32 CURSEC_REG1; /**< 0x0048: Current Sector Register 1 >**/ + uint32 WDTOPLD1; /**< 0x004C: Channel 1 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD1; /**< 0x0050: Channel 1 Block Complete Timeout Preload Register B >**/ + uint32 rvd9[ 3 ]; /**< 0x0054: reserved >**/ + uint32 PSA_SIGREGL1; /**< 0x0060: Channel 1 PSA signature low register >**/ + uint32 PSA_SIGREGH1; /**< 0x0064: Channel 1 PSA signature high register >**/ + uint32 REGL1; /**< 0x0068: Channel 1 CRC value low register >**/ + uint32 REGH1; /**< 0x006C: Channel 1 CRC value high register >**/ + uint32 PSA_SECSIGREGL1; /**< 0x0070: Channel 1 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH1; /**< 0x0074: Channel 1 PSA sector signature high register >**/ + uint32 RAW_DATAREGL1; /**< 0x0078: Channel 1 Raw Data Low Register >**/ + uint32 RAW_DATAREGH1; /**< 0x007C: Channel 1 Raw Data High Register >**/ + uint32 PCOUNT_REG2; /**< 0x0080: CRC Pattern Counter Preload Register2 >**/ + uint32 SCOUNT_REG2; /**< 0x0084: Sector Counter Preload Register2 >**/ + uint32 CURSEC_REG2; /**< 0x0088: Current Sector Register 2>**/ + uint32 WDTOPLD2; /**< 0x008C: Channel 2 Watchdog Timeout Preload Register A >**/ + uint32 BCTOPLD2; /**< 0x0090: Channel 2 Block Complete Timeout Preload Register B >**/ + uint32 rvd10[ 3 ]; /**< 0x0094: reserved >**/ + uint32 PSA_SIGREGL2; /**< 0x00A0: Channel 2 PSA signature low register >**/ + uint32 PSA_SIGREGH2; /**< 0x00A4: Channel 2 PSA signature high register >**/ + uint32 REGL2; /**< 0x00A8: Channel 2 CRC value low register >**/ + uint32 REGH2; /**< 0x00AC: Channel 2 CRC value high register >**/ + uint32 PSA_SECSIGREGL2; /**< 0x00B0: Channel 2 PSA sector signature low register >**/ + uint32 PSA_SECSIGREGH2; /**< 0x00B4: Channel 2 PSA sector signature high register >**/ + uint32 RAW_DATAREGL2; /**< 0x00B8: Channel 2 Raw Data Low Register >**/ + uint32 RAW_DATAREGH2; /**< 0x00BC: Channel 2 Raw Data High Register >**/ +} crcBASE_t; + +/** @def crcREG1 + * @brief CRC1 Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC1 registers. + */ +#define crcREG1 ( ( crcBASE_t * ) 0xFE000000U ) + +/** @def crcREG2 + * @brief CRC2 Register Frame Pointer + * + * This pointer is used by the CRC driver to access the CRC2 registers. + */ +#define crcREG2 ( ( crcBASE_t * ) 0xFB000000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h new file mode 100644 index 00000000000..f60eefcd29b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dcc.h @@ -0,0 +1,99 @@ +/** @file reg_dcc.h + * @brief DCC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DCC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DCC_H__ +#define __REG_DCC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dcc Register Frame Definition */ +/** @struct dccBase + * @brief DCC Base Register Definition + * + * This structure is used to access the DCC module registers. + */ +/** @typedef dccBASE_t + * @brief DCC Register Frame Type Definition + * + * This type is used to access the DCC Registers. + */ +typedef volatile struct dccBase +{ + uint32 GCTRL; /**< 0x0000: DCC Control Register */ + uint32 REV; /**< 0x0004: DCC Revision Id Register */ + uint32 CNT0SEED; /**< 0x0008: DCC Counter0 Seed Register */ + uint32 VALID0SEED; /**< 0x000C: DCC Valid0 Seed Register */ + uint32 CNT1SEED; /**< 0x0010: DCC Counter1 Seed Register */ + uint32 STAT; /**< 0x0014: DCC Status Register */ + uint32 CNT0; /**< 0x0018: DCC Counter0 Value Register */ + uint32 VALID0; /**< 0x001C: DCC Valid0 Value Register */ + uint32 CNT1; /**< 0x0020: DCC Counter1 Value Register */ + uint32 CNT1CLKSRC; /**< 0x0024: DCC Counter1 Clock Source Selection Register */ + uint32 CNT0CLKSRC; /**< 0x0028: DCC Counter0 Clock Source Selection Register */ +} dccBASE_t; + +/** @def dccREG1 + * @brief DCC1 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG1 ( ( dccBASE_t * ) 0xFFFFEC00U ) + +/** @def dccREG2 + * @brief DCC2 Register Frame Pointer + * + * This pointer is used by the DCC driver to access the dcc2 module registers. + */ +#define dccREG2 ( ( dccBASE_t * ) 0xFFFFF400U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h new file mode 100644 index 00000000000..f0aa785319e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dma.h @@ -0,0 +1,242 @@ +/** @file reg_dma.h + * @brief DMA Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMA_H__ +#define __REG_DMA_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* DMA Register Frame Definition */ +/** @struct dmaBase + * @brief DMA Register Frame Definition + * + * This type is used to access the DMA Registers. + */ +/** @struct dmaBASE_t + * @brief DMA Register Definition + * + * This structure is used to access the DMA module egisters. + */ +typedef volatile struct dmaBase +{ + uint32 GCTRL; /**< 0x0000: Global Control Register */ + uint32 PEND; /**< 0x0004: Channel Pending Register */ + uint32 FBREG; /**< 0x0008: Fall Back Register */ + uint32 DMASTAT; /**< 0x000C: Status Register */ + uint32 rsvd1; /**< 0x0010: Reserved */ + uint32 HWCHENAS; /**< 0x0014: HW Channel Enable Set */ + uint32 rsvd2; /**< 0x0018: Reserved */ + uint32 HWCHENAR; /**< 0x001C: HW Channel Enable Reset */ + uint32 rsvd3; /**< 0x0020: Reserved */ + uint32 SWCHENAS; /**< 0x0024: SW Channel Enable Set */ + uint32 rsvd4; /**< 0x0028: Reserved */ + uint32 SWCHENAR; /**< 0x002C: SW Channel Enable Reset */ + uint32 rsvd5; /**< 0x0030: Reserved */ + uint32 CHPRIOS; /**< 0x0034: Channel Priority Set */ + uint32 rsvd6; /**< 0x0038: Reserved */ + uint32 CHPRIOR; /**< 0x003C: Channel Priority Reset */ + uint32 rsvd7; /**< 0x0040: Reserved */ + uint32 GCHIENAS; /**< 0x0044: Global Channel Interrupt Enable Set */ + uint32 rsvd8; /**< 0x0048: Reserved */ + uint32 GCHIENAR; /**< 0x004C: Global Channel Interrupt Enable Reset */ + uint32 rsvd9; /**< 0x0050: Reserved */ + uint32 DREQASI[ 8U ]; /**< 0x0054 - 0x70: DMA Request Assignment Register */ + uint32 rsvd10[ 8U ]; /**< 0x0074 - 0x90: Reserved */ + uint32 PAR[ 4U ]; /**< 0x0094 - 0xA0: Port Assignment Register */ + uint32 rsvd11[ 4U ]; /**< 0x00A4 - 0xB0: Reserved */ + uint32 FTCMAP; /**< 0x00B4: FTC Interrupt Mapping Register */ + uint32 rsvd12; /**< 0x00B8: Reserved */ + uint32 LFSMAP; /**< 0x00BC: LFS Interrupt Mapping Register */ + uint32 rsvd13; /**< 0x00C0: Reserved */ + uint32 HBCMAP; /**< 0x00C4: HBC Interrupt Mapping Register */ + uint32 rsvd14; /**< 0x00C8: Reserved */ + uint32 BTCMAP; /**< 0x00CC: BTC Interrupt Mapping Register */ + uint32 rsvd15; /**< 0x00D0: Reserved */ + uint32 BERMAP; /**< 0x00D4: BER Interrupt Mapping Register */ + uint32 rsvd16; /**< 0x00D8: Reserved */ + uint32 FTCINTENAS; /**< 0x00DC: FTC Interrupt Enable Set */ + uint32 rsvd17; /**< 0x00E0: Reserved */ + uint32 FTCINTENAR; /**< 0x00E4: FTC Interrupt Enable Reset */ + uint32 rsvd18; /**< 0x00E8: Reserved */ + uint32 LFSINTENAS; /**< 0x00EC: LFS Interrupt Enable Set */ + uint32 rsvd19; /**< 0x00F0: Reserved */ + uint32 LFSINTENAR; /**< 0x00F4: LFS Interrupt Enable Reset */ + uint32 rsvd20; /**< 0x00F8: Reserved */ + uint32 HBCINTENAS; /**< 0x00FC: HBC Interrupt Enable Set */ + uint32 rsvd21; /**< 0x0100: Reserved */ + uint32 HBCINTENAR; /**< 0x0104: HBC Interrupt Enable Reset */ + uint32 rsvd22; /**< 0x0108: Reserved */ + uint32 BTCINTENAS; /**< 0x010C: BTC Interrupt Enable Set */ + uint32 rsvd23; /**< 0x0110: Reserved */ + uint32 BTCINTENAR; /**< 0x0114: BTC Interrupt Enable Reset */ + uint32 rsvd24; /**< 0x0118: Reserved */ + uint32 GINTFLAG; /**< 0x011C: Global Interrupt Flag Register */ + uint32 rsvd25; /**< 0x0120: Reserved */ + uint32 FTCFLAG; /**< 0x0124: FTC Interrupt Flag Register */ + uint32 rsvd26; /**< 0x0128: Reserved */ + uint32 LFSFLAG; /**< 0x012C: LFS Interrupt Flag Register */ + uint32 rsvd27; /**< 0x0130: Reserved */ + uint32 HBCFLAG; /**< 0x0134: HBC Interrupt Flag Register */ + uint32 rsvd28; /**< 0x0138: Reserved */ + uint32 BTCFLAG; /**< 0x013C: BTC Interrupt Flag Register */ + uint32 rsvd29; /**< 0x0140: Reserved */ + uint32 BERFLAG; /**< 0x0144: BER Interrupt Flag Register */ + uint32 rsvd30; /**< 0x0148: Reserved */ + uint32 FTCAOFFSET; /**< 0x014C: FTCA Interrupt Channel Offset Register */ + uint32 LFSAOFFSET; /**< 0x0150: LFSA Interrupt Channel Offset Register */ + uint32 HBCAOFFSET; /**< 0x0154: HBCA Interrupt Channel Offset Register */ + uint32 BTCAOFFSET; /**< 0x0158: BTCA Interrupt Channel Offset Register */ + uint32 BERAOFFSET; /**< 0x015C: BERA Interrupt Channel Offset Register */ + uint32 FTCBOFFSET; /**< 0x0160: FTCB Interrupt Channel Offset Register */ + uint32 LFSBOFFSET; /**< 0x0164: LFSB Interrupt Channel Offset Register */ + uint32 HBCBOFFSET; /**< 0x0168: HBCB Interrupt Channel Offset Register */ + uint32 BTCBOFFSET; /**< 0x016C: BTCB Interrupt Channel Offset Register */ + uint32 BERBOFFSET; /**< 0x0170: BERB Interrupt Channel Offset Register */ + uint32 rsvd31; /**< 0x0174: Reserved */ + uint32 PTCRL; /**< 0x0178: Port Control Register */ + uint32 RTCTRL; /**< 0x017C: RAM Test Control Register */ + uint32 DCTRL; /**< 0x0180: Debug Control */ + uint32 WPR; /**< 0x0184: Watch Point Register */ + uint32 WMR; /**< 0x0188: Watch Mask Register */ + uint32 FAACSADDR; /**< 0x018C: */ + uint32 FAACDADDR; /**< 0x0190: */ + uint32 FAACTC; /**< 0x0194: */ + uint32 FBACSADDR; /**< 0x0198: Port B Active Channel Source Address Register */ + uint32 FBACDADDR; /**< 0x019C: Port B Active Channel Destination Address Register */ + uint32 FBACTC; /**< 0x01A0: Port B Active Channel Transfer Count Register */ + uint32 rsvd32; /**< 0x01A4: Reserved */ + uint32 DMAPCR; /**< 0x01A8: Parity Control Register */ + uint32 DMAPAR; /**< 0x01AC: DMA Parity Error Address Register */ + uint32 DMAMPCTRL1; /**< 0x01B0: DMA Memory Protection Control Register */ + uint32 DMAMPST1; /**< 0x01B4: DMA Memory Protection Status Register */ + + struct + { + uint32 STARTADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + uint32 ENDADD; /**< 0x01B8, 0x01C0, 0x01C8, 0x1D0: DMA Memory Protection Region + Start Address Register */ + } DMAMPR_L[ 4U ]; + + uint32 DMAMPCTRL2; /**< 0x01D8: Memory Protection Control Register */ + uint32 DMAPST2; /**< 0x01DC: Memory Protection Status Register */ + + struct + { + uint32 STARTADD; /**< 0x01E0, 0x01E8, 0x01F0, 0x01F8: DMA Memory Protection + Region Start Address Register */ + uint32 ENDADD; /**< 0x01E4, 0x01EC, 0x01F4, 0x01FC: DMA Memory Protection Region + Start Address Register */ + } DMAMPR_H[ 4U ]; + + uint32 rsvd33[ 10U ]; /**< 0x0200 - 0x224: Reserved */ + uint32 DMASECCCTRL; /**< 0x0228: DMA Single bit ECC Control RegisteR */ + uint32 rsvd34; /**< 0x022C: Reserved */ + uint32 DMAECCSBE; /**< 0x0230: DMA ECC Single bit Error Address Register */ + uint32 rsvd35[ 3U ]; /**< 0x0234 - 0x023C: Reserved */ + uint32 FIFOASTATREG; /**< 0x0240: FIFO A Status Register */ + uint32 FIFOBSTATREG; /**< 0x0244: FIFO B Status Register */ + uint32 rsvd37[ 58U ]; /**< 0x0248 - 0x032C: Reserved */ + uint32 DMAREQPS1; /**< 0x0330: DMA Request Polarity Select Register 1 */ + uint32 DMAREQPS0; /**< 0x0334: DMA Request Polarity Select Register 0 */ + uint32 rsvd38[ 32 ]; /**< 0x0338 - 0x033C: Reserved */ + uint32 TERECTRL; /**< 0x0340: TER Event Control Register */ + uint32 TERFLAG; /**< 0x0344: TER Event Flag Register */ + uint32 TERROFFSET; /**< 0x0348: TER Event Channel Offset Register */ +} dmaBASE_t; + +typedef volatile struct +{ + struct /* 0x000-0x400 */ + { + uint32 ISADDR; + uint32 IDADDR; + uint32 ITCOUNT; + uint32 rsvd1; + uint32 CHCTRL; + uint32 EIOFF; + uint32 FIOFF; + uint32 rsvd2; + } PCP[ 32U ]; + + struct /* 0x400-0x800 */ + { + uint32 res[ 256U ]; + } RESERVED; + + struct /* 0x800-0xA00 */ + { + uint32 CSADDR; + uint32 CDADDR; + uint32 CTCOUNT; + uint32 rsvd3; + } WCP[ 32U ]; + +} dmaRAMBASE_t; + +#define dmaRAMREG ( ( dmaRAMBASE_t * ) 0xFFF80000U ) + +/** @def dmaREG + * @brief DMA1 Register Frame Pointer + * + * This pointer is used by the DMA driver to access the DMA module registers. + */ +#define dmaREG ( ( dmaBASE_t * ) 0xFFFFF000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif /* REG_DMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h new file mode 100644 index 00000000000..b53fab6355d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_dmm.h @@ -0,0 +1,127 @@ +/** @file reg_dmm.h + * @brief DMM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DMM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_DMM_H__ +#define __REG_DMM_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Dmm Register Frame Definition */ +/** @struct dmmBase + * @brief DMM Base Register Definition + * + * This structure is used to access the DMM module registers. + */ +/** @typedef dmmBASE_t + * @brief DMM Register Frame Type Definition + * + * This type is used to access the DMM Registers. + */ + +typedef volatile struct dmmBase +{ + uint32 GLBCTRL; /**< 0x0000: Global control register 0 */ + uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */ + uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */ + uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */ + uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */ + uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */ + uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */ + uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */ + uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */ + uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */ + uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */ + uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */ + uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */ + uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */ + uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */ + uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */ + uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */ + uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */ + uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */ + uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */ + uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */ + uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */ + uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */ + uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */ + uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */ + uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */ + uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */ + uint32 PC0; /**< 0x006C: DMM Pin Control 0 */ + uint32 PC1; /**< 0x0070: DMM Pin Control 1 */ + uint32 PC2; /**< 0x0074: DMM Pin Control 2 */ + uint32 PC3; /**< 0x0078: DMM Pin Control 3 */ + uint32 PC4; /**< 0x007C: DMM Pin Control 4 */ + uint32 PC5; /**< 0x0080: DMM Pin Control 5 */ + uint32 PC6; /**< 0x0084: DMM Pin Control 6 */ + uint32 PC7; /**< 0x0088: DMM Pin Control 7 */ + uint32 PC8; /**< 0x008C: DMM Pin Control 8 */ +} dmmBASE_t; + +/** @def dmmREG + * @brief DMM Register Frame Pointer + * + * This pointer is used by the DMM driver to access the DMM module registers. + */ +#define dmmREG ( ( dmmBASE_t * ) 0xFFFFF700U ) + +/** @def dmmPORT + * @brief DMM Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of DMM + * (use the GIO drivers to access the port pins). + */ +#define dmmPORT ( ( gioPORT_t * ) 0xFFFFF770U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h new file mode 100644 index 00000000000..962bc197e55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_ecap.h @@ -0,0 +1,155 @@ +/** @file reg_ecap.h + * @brief ECAP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ECAP_H__ +#define __REG_ECAP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Ecap Register Frame Definition */ +/** @struct ecapBASE + * @brief ECAP Register Frame Definition + * + * This type is used to access the ECAP Registers. + */ +/** @typedef ecapBASE_t + * @brief ECAP Register Frame Type Definition + * + * This type is used to access the ECAP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ + +} ecapBASE_t; + +#else + +typedef volatile struct ecapBASE +{ + uint32 TSCTR; /**< 0x0000 Time stamp counter Register*/ + uint32 CTRPHS; /**< 0x0004 Counter phase Register*/ + uint32 CAP1; /**< 0x0008 Capture 1 Register*/ + uint32 CAP2; /**< 0x000C Capture 2 Register*/ + uint32 CAP3; /**< 0x0010 Capture 3 Register*/ + uint32 CAP4; /**< 0x0014 Capture 4 Register*/ + uint16 rsvd1[ 8U ]; /**< 0x0018 Reserved*/ + uint16 ECCTL2; /**< 0x002A Capture Control Reg 2 Register*/ + uint16 ECCTL1; /**< 0x0028 Capture Control Reg 1 Register*/ + uint16 ECFLG; /**< 0x002E Interrupt flags Register*/ + uint16 ECEINT; /**< 0x002C Interrupt enable Register*/ + uint16 ECFRC; /**< 0x0032 Interrupt force Register*/ + uint16 ECCLR; /**< 0x0030 Interrupt clear Register*/ + uint16 rsvd2[ 6U ]; /**< 0x0034 Reserved*/ + +} ecapBASE_t; + +#endif +/** @def ecapREG1 + * @brief ECAP1 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP1 registers. + */ +#define ecapREG1 ( ( ecapBASE_t * ) 0xFCF79300U ) + +/** @def ecapREG2 + * @brief ECAP2 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP2 registers. + */ +#define ecapREG2 ( ( ecapBASE_t * ) 0xFCF79400U ) + +/** @def ecapREG3 + * @brief ECAP3 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP3 registers. + */ +#define ecapREG3 ( ( ecapBASE_t * ) 0xFCF79500U ) + +/** @def ecapREG4 + * @brief ECAP4 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP4 registers. + */ +#define ecapREG4 ( ( ecapBASE_t * ) 0xFCF79600U ) + +/** @def ecapREG5 + * @brief ECAP5 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP5 registers. + */ +#define ecapREG5 ( ( ecapBASE_t * ) 0xFCF79700U ) + +/** @def ecapREG6 + * @brief ECAP6 Register Frame Pointer + * + * This pointer is used by the ECAP driver to access the ECAP6 registers. + */ +#define ecapREG6 ( ( ecapBASE_t * ) 0xFCF79800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h new file mode 100644 index 00000000000..f00eb93b75c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_efc.h @@ -0,0 +1,94 @@ +/** @file reg_efc.h + * @brief EFC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EFC_H__ +#define __REG_EFC_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Efc Register Frame Definition */ +/** @struct efcBase + * @brief Efc Register Frame Definition + * + * This type is used to access the Efc Registers. + */ +/** @typedef efcBASE_t + * @brief Efc Register Frame Type Definition + * + * This type is used to access the Efc Registers. + */ +typedef volatile struct efcBase +{ + uint32 rsvd1; /* 0x00 RESERVED */ + uint32 rsvd2; /* 0x04 RESERVED */ + uint32 rsvd3; /* 0x08 RESERVED */ + uint32 rsvd4; /* 0x0C RESERVED */ + uint32 rsvd5; /* 0x10 RESERVED */ + uint32 rsvd6; /* 0x14 RESERVED */ + uint32 rsvd7; /* 0x18 RESERVED */ + uint32 BOUND; /* 0x1C RESERVED */ + uint32 rsvd8; /* 0x20 RESERVED */ + uint32 rsvd9; /* 0x24 RESERVED */ + uint32 rsvd10; /* 0x28 RESERVED */ + uint32 PINS; /* 0x2C RESERVED */ + uint32 rsvd11; /* 0x30 RESERVED */ + uint32 rsvd12; /* 0x34 RESERVED */ + uint32 rsvd13; /* 0x38 RESERVED */ + uint32 ERR_STAT; /* 0x3C RESERVED */ + uint32 rsvd14; /* 0x40 RESERVED */ + uint32 rsvd15; /* 0x44 RESERVED */ + uint32 ST_CY; /* 0x48 RESERVED */ + uint32 ST_SIG; /* 0x4C RESERVED */ +} efcBASE_t; + +#define efcREG ( ( efcBASE_t * ) 0xFFF8C000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h new file mode 100644 index 00000000000..513ff89e67b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_emif.h @@ -0,0 +1,97 @@ +/** @file reg_emif.h + * @brief EMIF Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EMIF driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EMIF_H__ +#define __REG_EMIF_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Emif Register Frame Definition */ +/** @struct emifBASE_t + * @brief emifBASE Register Definition + * + * This structure is used to access the EMIF module registers. + */ +typedef volatile struct emifBase +{ + uint32 MIDR; /**< 0x0000 Module ID Register */ + uint32 AWCC; /**< 0x0004 Asynchronous wait cycle register*/ + uint32 SDCR; /**< 0x0008 SDRAM configuration register */ + uint32 SDRCR; /**< 0x000C Set Interrupt Enable Register */ + uint32 CE2CFG; /**< 0x0010 Asynchronous 1 Configuration Register */ + uint32 CE3CFG; /**< 0x0014 Asynchronous 2 Configuration Register */ + uint32 CE4CFG; /**< 0x0018 Asynchronous 3 Configuration Register */ + uint32 CE5CFG; /**< 0x001C Asynchronous 4 Configuration Register */ + uint32 SDTIMR; /**< 0x0020 SDRAM Timing Register */ + uint32 dummy1[ 6 ]; /** reserved **/ + uint32 SDSRETR; /**< 0x003c SDRAM Self Refresh Exit Timing Register */ + uint32 INTRAW; /**< 0x0040 0x0020 Interrupt Vector Offset*/ + uint32 INTMSK; /**< 0x0044 EMIF Interrupt Mask Register */ + uint32 INTMSKSET; /**< 48 EMIF Interrupt Mask Set Register */ + uint32 INTMSKCLR; /**< 0x004c EMIF Interrupt Mask Register */ + uint32 dummy2[ 6 ]; /** reserved **/ + uint32 PMCR; /**< 0x0068 Page Mode Control Register*/ + +} emifBASE_t; + +#define emifREG ( ( emifBASE_t * ) 0xFCFFE800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h new file mode 100644 index 00000000000..6c2612b51a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_epc.h @@ -0,0 +1,97 @@ +/** @file reg_epc.h + * @brief EPC Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the EPC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EPC_H__ +#define __REG_EPC_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* EPC Register Frame Definition */ +/** @struct epcBase + * @brief EPC Base Register Definition + * + * This structure is used to access the EPC module registers. + */ +/** @typedef epcBASE_t + * @brief EPC Register Frame Type Definition + * + * This type is used to access the EPC Registers. + */ +typedef volatile struct epcBase +{ + uint32 EPCREVID; /**< 0x0000: EPC REVID Register */ + uint32 EPCCNTRL; /**< 0x0004: EPC Control Register */ + uint32 UERRSTAT; /**< 0x0008: Uncorrectable Error Status Register */ + uint32 EPCERRSTAT; /**< 0x000C: EPC Error Status Register */ + uint32 FIFOFULLSTAT; /**< 0x0010: FIFO Full Status Register */ + uint32 OVRFLWSTAT; /**< 0x0014: IP Interface FIFO Overflow Status Register */ + uint32 CAMAVAILSTAT; /**< 0x0018: CAM Index Available Status Register */ + uint32 rsvd1; /**< 0x001C: Reserved */ + uint32 UERRADDR[ 2 ]; /**< 0x0020 - 0x0024: Uncorrectable Error Address Registers */ + uint32 rsvd2[ 30 ]; /**< 0x0028 - 0x009C: Reserved */ + uint32 CAM_CONTENT[ 32 ]; /**< 0x00A0 - 0x011C: CAM Content Update Registers */ + uint32 rsvd3[ 56 ]; /**< 0x0120 - 0x01FC: Reserved */ + uint32 CAM_INDEX[ 8 ]; /**< 0x0200 - 0x021C: CAM Index Register 0 to 7 */ +} epcBASE_t; + +#define epcREG1 ( ( epcBASE_t * ) 0xFFFF0C00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h new file mode 100644 index 00000000000..26c50fe56f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_eqep.h @@ -0,0 +1,148 @@ +/** @file reg_eqep.h + * @brief EQEP Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_EQEP_H__ +#define __REG_EQEP_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Eqep Register Frame Definition */ +/** @struct eqepBASE + * @brief EQEP Register Frame Definition + * + * This type is used to access the EQEP Registers. + */ +/** @typedef eqepBASE_t + * @brief EQEP Register Frame Type Definition + * + * This type is used to access the EQEP Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ +} eqepBASE_t; + +#else + +typedef volatile struct eqepBASE +{ + uint32 QPOSCNT; /*< 0x0000 eQEP Position Counter*/ + uint32 QPOSINIT; /*< 0x0004 eQEP Initialization Position Count*/ + uint32 QPOSMAX; /*< 0x0008 eQEP Maximum Position Count*/ + uint32 QPOSCMP; /*< 0x000C eQEP Position Compare*/ + uint32 QPOSILAT; /*< 0x0010 eQEP Index Position Latch*/ + uint32 QPOSSLAT; /*< 0x0014 eQEP Strobe Position Latch*/ + uint32 QPOSLAT; /*< 0x0018 eQEP Position Latch*/ + uint32 QUTMR; /*< 0x001C eQEP Unit Timer*/ + uint32 QUPRD; /*< 0x0020 eQEP Unit Period*/ + uint16 QWDPRD; /*< 0x0026 eQEP Watchdog Period*/ + uint16 QWDTMR; /*< 0x0024 eQEP Watchdog Timer*/ + uint16 QEPCTL; /*< 0x002A eQEP Control*/ + uint16 QDECCTL; /*< 0x0028 eQEP Decoder Control*/ + uint16 QPOSCTL; /*< 0x002E eQEP Position Compare Control*/ + uint16 QCAPCTL; /*< 0x002C eQEP Capture Control*/ + uint16 QFLG; /*< 0x0032 eQEP Interrupt Flag Register*/ + uint16 QEINT; /*< 0x0030 eQEP Interrupt Enable Register*/ + uint16 QFRC; /*< 0x0036 eQEP Interrupt Force Register*/ + uint16 QCLR; /*< 0x0034 eQEP Interrupt Clear Register*/ + uint16 QCTMR; /*< 0x003A eQEP Capture Timer*/ + uint16 QEPSTS; /*< 0x0038 eQEP Status Register*/ + uint16 QCTMRLAT; /*< 0x003E eQEP Capture Timer Latch*/ + uint16 QCPRD; /*< 0x003C eQEP Capture Period*/ + uint16 rsvd_1; /*< 0x0042 Reserved*/ + uint16 QCPRDLAT; /*< 0x0040 eQEP Capture Period Latch*/ +} eqepBASE_t; + +#endif + +/** @def eqepREG1 + * @brief eQEP1 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP1 registers. + */ +#define eqepREG1 ( ( eqepBASE_t * ) 0xFCF79900U ) + +/** @def eqepREG2 + * @brief eQEP2 Register Frame Pointer + * + * This pointer is used by the eQEP driver to access the eQEP2 registers. + */ +#define eqepREG2 ( ( eqepBASE_t * ) 0xFCF79A00U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h new file mode 100644 index 00000000000..d5bef12ecd2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_esm.h @@ -0,0 +1,110 @@ +/** @file reg_esm.h + * @brief ESM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ESM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ESM_H__ +#define __REG_ESM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Esm Register Frame Definition */ +/** @struct esmBase + * @brief Esm Register Frame Definition + * + * This type is used to access the Esm Registers. + */ +/** @typedef esmBASE_t + * @brief Esm Register Frame Type Definition + * + * This type is used to access the Esm Registers. + */ +typedef volatile struct esmBase +{ + uint32 EEPAPR1; /* 0x0000 */ + uint32 DEPAPR1; /* 0x0004 */ + uint32 IESR1; /* 0x0008 */ + uint32 IECR1; /* 0x000C */ + uint32 ILSR1; /* 0x0010 */ + uint32 ILCR1; /* 0x0014 */ + uint32 SR1[ 3U ]; /* 0x0018, 0x001C, 0x0020 */ + uint32 EPSR; /* 0x0024 */ + uint32 IOFFHR; /* 0x0028 */ + uint32 IOFFLR; /* 0x002C */ + uint32 LTCR; /* 0x0030 */ + uint32 LTCPR; /* 0x0034 */ + uint32 EKR; /* 0x0038 */ + uint32 SSR2; /* 0x003C */ + uint32 IEPSR4; /* 0x0040 */ + uint32 IEPCR4; /* 0x0044 */ + uint32 IESR4; /* 0x0048 */ + uint32 IECR4; /* 0x004C */ + uint32 ILSR4; /* 0x0050 */ + uint32 ILCR4; /* 0x0054 */ + uint32 SR4[ 3U ]; /* 0x0058, 0x005C, 0x0060 */ + uint32 rsvd1[ 7U ]; /* 0x0064 - 0x007C */ + uint32 IEPSR7; /* 0x0080 */ + uint32 IEPCR7; /* 0x0084 */ + uint32 IESR7; /* 0x0088 */ + uint32 IECR7; /* 0x008C */ + uint32 ILSR7; /* 0x0090 */ + uint32 ILCR7; /* 0x0094 */ + uint32 SR7[ 3U ]; /* 0x0098, 0x009C, 0x00A0 */ +} esmBASE_t; + +/** @def esmREG + * @brief Esm Register Frame Pointer + * + * This pointer is used by the Esm driver to access the Esm registers. + */ +#define esmREG ( ( esmBASE_t * ) 0xFFFFF500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h new file mode 100644 index 00000000000..07d6382ab29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_etpwm.h @@ -0,0 +1,219 @@ +/** @file reg_etpwm.h + * @brief ETPWM Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_ETPWM_H__ +#define __REG_ETPWM_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* ETPWM Register Frame Definition */ +/** @struct etpwmBASE + * @brief ETPWM Register Frame Definition + * + * This type is used to access the ETPWM Registers. + */ +/** @typedef etpwmBASE_t + * @brief ETPWM Register Frame Type Definition + * + * This type is used to access the ETPWM Registers. + */ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + +typedef volatile struct etpwmBASE +{ + uint16 TBCTL; /**< 0x0000 Time-Base Control Register*/ + uint16 TBSTS; /**< 0x0002 Time-Base Status Register*/ + uint16 rsvd1; /**< 0x0004 Reserved*/ + uint16 TBPHS; /**< 0x0006 Time-Base Phase Register*/ + uint16 TBCTR; /**< 0x0008 Time-Base Counter Register*/ + uint16 TBPRD; /**< 0x000A Time-Base Period Register*/ + uint16 rsvd2; /**< 0x000C Reserved*/ + uint16 CMPCTL; /**< 0x000E Counter-Compare Control Register*/ + uint16 rsvd3; /**< 0x0010 Reserved*/ + uint16 CMPA; /**< 0x0012 Counter-Compare A Register*/ + uint16 CMPB; /**< 0x0014 Counter-Compare B Register*/ + uint16 AQCTLA; /**< 0x0016 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 AQCTLB; /**< 0x0018 Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 AQSFRC; /**< 0x001A Action-Qualifier Software Force Register*/ + uint16 AQCSFRC; /**< 0x001C Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBCTL; /**< 0x001E Dead-Band Generator Control Register*/ + uint16 DBRED; /**< 0x0020 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 DBFED; /**< 0x0022 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 TZSEL; /**< 0x0024 Trip-Zone Select Register*/ + uint16 TZDCSEL; /**< 0x0026 Trip Zone Digital Compare Select Register*/ + uint16 TZCTL; /**< 0x0028 Trip-Zone Control Register*/ + uint16 TZEINT; /**< 0x002A Trip-Zone Enable Interrupt Register*/ + uint16 TZFLG; /**< 0x002C Trip-Zone Flag Register*/ + uint16 TZCLR; /**< 0x002E Trip-Zone Clear Register*/ + uint16 TZFRC; /**< 0x0030 Trip-Zone Force Register*/ + uint16 ETSEL; /**< 0x0032 Event-Trigger Selection Register*/ + uint16 ETPS; /**< 0x0034 Event-Trigger Pre-Scale Register*/ + uint16 ETFLG; /**< 0x0036 Event-Trigger Flag Register*/ + uint16 ETCLR; /**< 0x0038 Event-Trigger Clear Register*/ + uint16 ETFRC; /**< 0x003A Event-Trigger Force Register*/ + uint16 PCCTL; /**< 0x003C PWM-Chopper Control Register*/ + uint16 rsvd4; /**< 0x003E Reserved*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCTRIPSEL; /**< 0x0060 Digital Compare Trip Select Register*/ + uint16 DCACTL; /**< 0x0062 Digital Compare A Control Register*/ + uint16 DCBCTL; /**< 0x0064 Digital Compare B Control Register*/ + uint16 DCFCTL; /**< 0x0066 Digital Compare Filter Control Register*/ + uint16 DCCAPCTL; /**< 0x0068 Digital Compare Capture Control Register*/ + uint16 DCFOFFSET; /**< 0x006A Digital Compare Filter Offset Register*/ + uint16 DCFOFFSETCNT; /**< 0x006C Digital Compare Filter Offset Counter Register*/ + uint16 DCFWINDOW; /**< 0x006E Digital Compare Filter Window Register*/ + uint16 DCFWINDOWCNT; /**< 0x0070 Digital Compare Filter Window Counter Register*/ + uint16 DCCAP; /**< 0x0072 Digital Compare Counter Capture Register*/ +} etpwmBASE_t; + +#else + +typedef volatile struct etpwmBASE +{ + uint16 TBSTS; /**< 0x0000 Time-Base Status Register*/ + uint16 TBCTL; /**< 0x0002 Time-Base Control Register*/ + uint16 TBPHS; /**< 0x0004 Time-Base Phase Register*/ + uint16 rsvd1; /**< 0x0006 Reserved*/ + uint16 TBPRD; /**< 0x0008 Time-Base Period Register*/ + uint16 TBCTR; /**< 0x000A Time-Base Counter Register*/ + uint16 CMPCTL; /**< 0x000C Counter-Compare Control Register*/ + uint16 rsvd2; /**< 0x000E Reserved*/ + uint16 CMPA; /**< 0x0010 Counter-Compare A Register*/ + uint16 rsvd3; /**< 0x0012 Reserved*/ + uint16 AQCTLA; /**< 0x0014 Action-Qualifier Control Register for Output A (ETPWMxA)*/ + uint16 CMPB; /**< 0x0016 Counter-Compare B Register*/ + uint16 AQSFRC; /**< 0x0018 Action-Qualifier Software Force Register*/ + uint16 AQCTLB; /**< 0x001A Action-Qualifier Control Register for Output B (ETPWMxB)*/ + uint16 DBCTL; /**< 0x001C Dead-Band Generator Control Register*/ + uint16 AQCSFRC; /**< 0x001E Action-Qualifier Continuous S/W Force Register Set*/ + uint16 DBFED; /**< 0x0020 Dead-Band Generator Falling Edge Delay Count Register*/ + uint16 DBRED; /**< 0x0022 Dead-Band Generator Rising Edge Delay Count Register*/ + uint16 TZDCSEL; /**< 0x0024 Trip Zone Digital Compare Select Register*/ + uint16 TZSEL; /**< 0x0026 Trip-Zone Select Register*/ + uint16 TZEINT; /**< 0x0028 Trip-Zone Enable Interrupt Register*/ + uint16 TZCTL; /**< 0x002A Trip-Zone Control Register*/ + uint16 TZCLR; /**< 0x002C Trip-Zone Clear Register*/ + uint16 TZFLG; /**< 0x002E Trip-Zone Flag Register*/ + uint16 ETSEL; /**< 0x0030 Event-Trigger Selection Register*/ + uint16 TZFRC; /**< 0x0032 Trip-Zone Force Register*/ + uint16 ETFLG; /**< 0x0034 Event-Trigger Flag Register*/ + uint16 ETPS; /**< 0x0036 Event-Trigger Pre-Scale Register*/ + uint16 ETFRC; /**< 0x0038 Event-Trigger Force Register*/ + uint16 ETCLR; /**< 0x003A Event-Trigger Clear Register*/ + uint16 rsvd4; /**< 0x003C Reserved*/ + uint16 PCCTL; /**< 0x003E PWM-Chopper Control Register*/ + uint16 rsvd5[ 16U ]; /**< 0x0040 Reserved*/ + uint16 DCACTL; /**< 0x0060 Digital Compare A Control Register*/ + uint16 DCTRIPSEL; /**< 0x0062 Digital Compare Trip Select Register*/ + uint16 DCFCTL; /**< 0x0064 Digital Compare Filter Control Register*/ + uint16 DCBCTL; /**< 0x0066 Digital Compare B Control Register*/ + uint16 DCFOFFSET; /**< 0x0068 Digital Compare Filter Offset Register*/ + uint16 DCCAPCTL; /**< 0x006A Digital Compare Capture Control Register*/ + uint16 DCFWINDOW; /**< 0x006C Digital Compare Filter Window Register*/ + uint16 DCFOFFSETCNT; /**< 0x006E Digital Compare Filter Offset Counter Register*/ + uint16 DCCAP; /**< 0x0070 Digital Compare Counter Capture Register*/ + uint16 DCFWINDOWCNT; /**< 0x0072 Digital Compare Filter Window Counter Register*/ +} etpwmBASE_t; + +#endif + +/** @def etpwmREG1 + * @brief ETPWM1 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM1 registers. + */ +#define etpwmREG1 ( ( etpwmBASE_t * ) 0xFCF78C00U ) + +/** @def etpwmREG2 + * @brief ETPWM2 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM2 registers. + */ +#define etpwmREG2 ( ( etpwmBASE_t * ) 0xFCF78D00U ) + +/** @def etpwmREG3 + * @brief ETPWM3 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM3 registers. + */ +#define etpwmREG3 ( ( etpwmBASE_t * ) 0xFCF78E00U ) + +/** @def etpwmREG4 + * @brief ETPWM4 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM4 registers. + */ +#define etpwmREG4 ( ( etpwmBASE_t * ) 0xFCF78F00U ) + +/** @def etpwmREG5 + * @brief ETPWM5 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM5 registers. + */ +#define etpwmREG5 ( ( etpwmBASE_t * ) 0xFCF79000U ) + +/** @def etpwmREG6 + * @brief ETPWM6 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM6 registers. + */ +#define etpwmREG6 ( ( etpwmBASE_t * ) 0xFCF79100U ) + +/** @def etpwmREG7 + * @brief ETPWM7 Register Frame Pointer + * + * This pointer is used by the ETPWM driver to access the ETPWM7 registers. + */ +#define etpwmREG7 ( ( etpwmBASE_t * ) 0xFCF79200U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h new file mode 100644 index 00000000000..262d45c66d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_flash.h @@ -0,0 +1,135 @@ +/** @file reg_flash.h + * @brief Flash Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_FLASH_H__ +#define __REG_FLASH_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Flash Register Frame Definition */ +/** @struct flashWBase + * @brief Flash Wrapper Register Frame Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +/** @typedef flashWBASE_t + * @brief Flash Wrapper Register Frame Type Definition + * + * This type is used to access the Flash Wrapper Registers. + */ +typedef volatile struct flashWBase +{ + uint32 FRDCNTL; /* 0x0000 */ + uint32 rsvd1; /* 0x0004 */ + uint32 EE_FEDACCTRL1; /* 0x0008 */ + uint32 rsvd2; /* 0x000C */ + uint32 rsvd3; /* 0x0010 */ + uint32 FEDAC_PASTATUS; /* 0x0014 */ + uint32 FEDAC_PBSTATUS; /* 0x0018 */ + uint32 FEDAC_GBLSTATUS; /* 0x001C */ + uint32 rsvd4; /* 0x0020 */ + uint32 FEDACSDIS; /* 0x0024 */ + uint32 FPRIM_ADD_TAG; /* 0x0028 */ + uint32 FDUP_ADD_TAG; /* 0x002C */ + uint32 FBPROT; /* 0x0030 */ + uint32 FBSE; /* 0x0034 */ + uint32 FBBUSY; /* 0x0038 */ + uint32 FBAC; /* 0x003C */ + uint32 FBPWRMODE; /* 0x0040 */ + uint32 FBPRDY; /* 0x0044 */ + uint32 FPAC1; /* 0x0048 */ + uint32 rsvd5; /* 0x004C */ + uint32 FMAC; /* 0x0050 */ + uint32 FMSTAT; /* 0x0054 */ + uint32 FEMU_DMSW; /* 0x0058 */ + uint32 FEMU_DLSW; /* 0x005C */ + uint32 FEMU_ECC; /* 0x0060 */ + uint32 FLOCK; /* 0x0064 */ + uint32 rsvd6; /* 0x0068 */ + uint32 FDIAGCTRL; /* 0x006C */ + uint32 rsvd7; /* 0x0070 */ + uint32 FRAW_ADDR; /* 0x0074 */ + uint32 rsvd8; /* 0x0078 */ + uint32 FPAR_OVR; /* 0x007C */ + uint32 rsvd9[ 13U ]; /* 0x0080 - 0x00B0 */ + uint32 RCR_VALID; /* 0x00B4 */ + uint32 ACC_THRESHOLD; /* 0x00B8 */ + uint32 rsvd10; /* 0x00BC */ + uint32 FEDACSDIS2; /* 0x00C0 */ + uint32 rsvd11; /* 0x00C4 */ + uint32 rsvd12; /* 0x00C8 */ + uint32 rsvd13; /* 0x00CC */ + uint32 RCR_VALUE0; /* 0x00D0 */ + uint32 RCR_VALUE1; /* 0x00D4 */ + uint32 rsvd14[ 108U ]; /* 0x00D8 - 0x00284 */ + uint32 FSM_WR_ENA; /* 0x0288 */ + uint32 rsvd15[ 11U ]; /* 0x028C - 0x002B4 */ + uint32 EEPROM_CONFIG; /* 0x02B8 */ + uint32 rsvd16; /* 0x02BC */ + uint32 FSM_SECTOR1; /* 0x02C0 */ + uint32 FSM_SECTOR2; /* 0x02C4 */ + uint32 rsvd17[ 78U ]; /* 0x02A8 */ + uint32 FCFG_BANK; /* 0x02B8 */ + +} flashWBASE_t; + +/** @def flashWREG + * @brief Flash Wrapper Register Frame Pointer + * + * This pointer is used by the system driver to access the flash wrapper registers. + */ +#define flashWREG ( ( flashWBASE_t * ) ( 0xFFF87000U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h new file mode 100644 index 00000000000..694b0f4665a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_gio.h @@ -0,0 +1,128 @@ +/** @file reg_gio.h + * @brief GIO Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the GIO driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_GIO_H__ +#define __REG_GIO_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Gio Register Frame Definition */ +/** @struct gioBase + * @brief GIO Base Register Definition + * + * This structure is used to access the GIO module registers. + */ +/** @typedef gioBASE_t + * @brief GIO Register Frame Type Definition + * + * This type is used to access the GIO Registers. + */ +typedef volatile struct gioBase +{ + uint32 GCR0; /**< 0x0000: Global Control Register */ + uint32 rsvd; /**< 0x0004: Reserved*/ + uint32 INTDET; /**< 0x0008: Interrupt Detect Register*/ + uint32 POL; /**< 0x000C: Interrupt Polarity Register */ + uint32 ENASET; /**< 0x0010: Interrupt Enable Set Register */ + uint32 ENACLR; /**< 0x0014: Interrupt Enable Clear Register */ + uint32 LVLSET; /**< 0x0018: Interrupt Priority Set Register */ + uint32 LVLCLR; /**< 0x001C: Interrupt Priority Clear Register */ + uint32 FLG; /**< 0x0020: Interrupt Flag Register */ + uint32 OFF1; /**< 0x0024: Interrupt Offset A Register */ + uint32 OFF2; /**< 0x0028: Interrupt Offset B Register */ + uint32 EMU1; /**< 0x002C: Emulation 1 Register */ + uint32 EMU2; /**< 0x0030: Emulation 2 Register */ +} gioBASE_t; + +/** @struct gioPort + * @brief GIO Port Register Definition + */ +/** @typedef gioPORT_t + * @brief GIO Port Register Type Definition + * + * This type is used to access the GIO Port Registers. + */ +typedef volatile struct gioPort +{ + uint32 DIR; /**< 0x0000: Data Direction Register */ + uint32 DIN; /**< 0x0004: Data Input Register */ + uint32 DOUT; /**< 0x0008: Data Output Register */ + uint32 DSET; /**< 0x000C: Data Output Set Register */ + uint32 DCLR; /**< 0x0010: Data Output Clear Register */ + uint32 PDR; /**< 0x0014: Open Drain Register */ + uint32 PULDIS; /**< 0x0018: Pullup Disable Register */ + uint32 PSL; /**< 0x001C: Pull Up/Down Selection Register */ +} gioPORT_t; + +/** @def gioREG + * @brief GIO Register Frame Pointer + * + * This pointer is used by the GIO driver to access the gio module registers. + */ +#define gioREG ( ( gioBASE_t * ) 0xFFF7BC00U ) + +/** @def gioPORTA + * @brief GIO Port (A) Register Pointer + * + * Pointer used by the GIO driver to access PORTA + */ +#define gioPORTA ( ( gioPORT_t * ) 0xFFF7BC34U ) + +/** @def gioPORTB + * @brief GIO Port (B) Register Pointer + * + * Pointer used by the GIO driver to access PORTB + */ +#define gioPORTB ( ( gioPORT_t * ) 0xFFF7BC54U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h new file mode 100644 index 00000000000..c5de03309e5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_het.h @@ -0,0 +1,187 @@ +/** @file reg_het.h + * @brief HET Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HET driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HET_H__ +#define __REG_HET_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Het Register Frame Definition */ +/** @struct hetBase + * @brief HET Base Register Definition + * + * This structure is used to access the HET module registers. + */ +/** @typedef hetBASE_t + * @brief HET Register Frame Type Definition + * + * This type is used to access the HET Registers. + */ + +typedef volatile struct hetBase +{ + uint32 GCR; /**< 0x0000: Global control register */ + uint32 PFR; /**< 0x0004: Prescale factor register */ + uint32 ADDR; /**< 0x0008: Current address register */ + uint32 OFF1; /**< 0x000C: Interrupt offset register 1 */ + uint32 OFF2; /**< 0x0010: Interrupt offset register 2 */ + uint32 INTENAS; /**< 0x0014: Interrupt enable set register */ + uint32 INTENAC; /**< 0x0018: Interrupt enable clear register */ + uint32 EXC1; /**< 0x001C: Exception control register 1 */ + uint32 EXC2; /**< 0x0020: Exception control register 2 */ + uint32 PRY; /**< 0x0024: Interrupt priority register */ + uint32 FLG; /**< 0x0028: Interrupt flag register */ + uint32 AND; /**< 0x002C: AND share control register */ + uint32 rsvd1; /**< 0x0030: Reserved */ + uint32 HRSH; /**< 0x0034: High resolution share register */ + uint32 XOR; /**< 0x0038: XOR share register */ + uint32 REQENS; /**< 0x003C: Request enable set register */ + uint32 REQENC; /**< 0x0040: Request enable clear register */ + uint32 REQDS; /**< 0x0044: Request destination select register */ + uint32 rsvd2; /**< 0x0048: Reserved */ + uint32 DIR; /**< 0x004C: Direction register */ + uint32 DIN; /**< 0x0050: Data input register */ + uint32 DOUT; /**< 0x0054: Data output register */ + uint32 DSET; /**< 0x0058: Data output set register */ + uint32 DCLR; /**< 0x005C: Data output clear register */ + uint32 PDR; /**< 0x0060: Open drain register */ + uint32 PULDIS; /**< 0x0064: Pull disable register */ + uint32 PSL; /**< 0x0068: Pull select register */ + uint32 rsvd3; /**< 0x006C: Reserved */ + uint32 rsvd4; /**< 0x0070: Reserved */ + uint32 PCR; /**< 0x0074: Parity control register */ + uint32 PAR; /**< 0x0078: Parity address register */ + uint32 PPR; /**< 0x007C: Parity pin select register */ + uint32 SFPRLD; /**< 0x0080: Suppression filter preload register */ + uint32 SFENA; /**< 0x0084: Suppression filter enable register */ + uint32 rsvd5; /**< 0x0088: Reserved */ + uint32 LBPSEL; /**< 0x008C: Loop back pair select register */ + uint32 LBPDIR; /**< 0x0090: Loop back pair direction register */ + uint32 PINDIS; /**< 0x0094: Pin disable register */ +} hetBASE_t; + +/** @struct hetInstructionBase + * @brief HET Instruction Definition + * + * This structure is used to access the HET RAM. + */ +/** @typedef hetINSTRUCTION_t + * @brief HET Instruction Type Definition + * + * This type is used to access a HET Instruction. + */ +typedef volatile struct hetInstructionBase +{ + uint32 Program; + uint32 Control; + uint32 Data; + uint32 rsvd1; +} hetINSTRUCTION_t; + +/** @struct hetRamBase + * @brief HET RAM Definition + * + * This structure is used to access the HET RAM. + */ +/** @typedef hetRAMBASE_t + * @brief HET RAM Type Definition + * + * This type is used to access the HET RAM. + */ +typedef volatile struct het1RamBase +{ + hetINSTRUCTION_t Instruction[ 160U ]; +} hetRAMBASE_t; + +/** @def hetREG1 + * @brief HET Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG1 ( ( hetBASE_t * ) 0xFFF7B800U ) + +/** @def hetPORT1 + * @brief HET GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET1 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT1 ( ( gioPORT_t * ) 0xFFF7B84CU ) + +/** @def hetREG2 + * @brief HET2 Register Frame Pointer + * + * This pointer is used by the HET driver to access the het module registers. + */ +#define hetREG2 ( ( hetBASE_t * ) 0xFFF7B900U ) + +/** @def hetPORT2 + * @brief HET2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of HET2 + * (use the GIO drivers to access the port pins). + */ +#define hetPORT2 ( ( gioPORT_t * ) 0xFFF7B94CU ) + +#define hetRAM1 ( ( hetRAMBASE_t * ) 0xFF460000U ) + +#define hetRAM2 ( ( hetRAMBASE_t * ) 0xFF440000U ) + +#define NHET1RAMPARLOC ( *( volatile uint32 * ) 0xFF462000U ) +#define NHET1RAMLOC ( *( volatile uint32 * ) 0xFF460000U ) + +#define NHET2RAMPARLOC ( *( volatile uint32 * ) 0xFF442000U ) +#define NHET2RAMLOC ( *( volatile uint32 * ) 0xFF440000U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h new file mode 100644 index 00000000000..d5760454f50 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_htu.h @@ -0,0 +1,130 @@ +/** @file reg_htu.h + * @brief HTU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the HTU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_HTU_H__ +#define __REG_HTU_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* htu Register Frame Definition */ +/** @struct htuBase + * @brief HTU Base Register Definition + * + * This structure is used to access the HTU module registers. + */ +/** @typedef htuBASE_t + * @brief HTU Register Frame Type Definition + * + * This type is used to access the HTU Registers. + */ +typedef volatile struct htuBase +{ + uint32 GC; /** 0x00 */ + uint32 CPENA; /** 0x04 */ + uint32 BUSY0; /** 0x08 */ + uint32 BUSY1; /** 0x0C */ + uint32 BUSY2; /** 0x10 */ + uint32 BUSY3; /** 0x14 */ + uint32 ACPE; /** 0x18 */ + uint32 rsvd1; /** 0x1C */ + uint32 RLBECTRL; /** 0x20 */ + uint32 BFINTS; /** 0x24 */ + uint32 BFINTC; /** 0x28 */ + uint32 INTMAP; /** 0x2C */ + uint32 rsvd2; /** 0x30 */ + uint32 INTOFF0; /** 0x34 */ + uint32 INTOFF1; /** 0x38 */ + uint32 BIM; /** 0x3C */ + uint32 RLOSTFL; /** 0x40 */ + uint32 BFINTFL; /** 0x44 */ + uint32 BERINTFL; /** 0x48 */ + uint32 MP1S; /** 0x4C */ + uint32 MP1E; /** 0x50 */ + uint32 DCTRL; /** 0x54 */ + uint32 WPR; /** 0x58 */ + uint32 WMR; /** 0x5C */ + uint32 ID; /** 0x60 */ + uint32 PCR; /** 0x64 */ + uint32 PAR; /** 0x68 */ + uint32 rsvd3; /** 0x6C */ + uint32 MPCS; /** 0x70 */ + uint32 MP0S; /** 0x74 */ + uint32 MP0E; /** 0x78 */ +} htuBASE_t; + +typedef volatile struct htudcp +{ + uint32 IFADDRA; + uint32 IFADDRB; + uint32 IHADDRCT; + uint32 ITCOUNT; +} htudcp_t; + +typedef volatile struct htucdcp +{ + uint32 CFADDRA; + uint32 CFADDRB; + uint32 CFCOUNT; + uint32 rsvd4; +} htucdcp_t; + +#define htuREG1 ( ( htuBASE_t * ) 0xFFF7A400U ) +#define htuREG2 ( ( htuBASE_t * ) 0xFFF7A500U ) + +#define htuDCP1 ( ( htudcp_t * ) 0xFF4E0000U ) +#define htuDCP2 ( ( htudcp_t * ) 0xFF4C0000U ) + +#define htuCDCP1 ( ( htucdcp_t * ) 0xFF4E0100U ) +#define htuCDCP2 ( ( htucdcp_t * ) 0xFF4C0100U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h new file mode 100644 index 00000000000..57331088e93 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_i2c.h @@ -0,0 +1,136 @@ +/** @file reg_i2c.h + * @brief I2C Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the I2C driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_I2C_H__ +#define __REG_I2C_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* I2c Register Frame Definition */ +/** @struct i2cBase + * @brief I2C Base Register Definition + * + * This structure is used to access the I2C module registers. + */ +/** @typedef i2cBASE_t + * @brief I2C Register Frame Type Definition + * + * This type is used to access the I2C Registers. + */ +typedef volatile struct i2cBase +{ + uint32 OAR; /**< 0x0000 I2C Own Address register */ + uint32 IMR; /**< 0x0004 I2C Interrupt Mask/Status register */ + uint32 STR; /**< 0x0008 I2C Interrupt Status register */ + uint32 CKL; /**< 0x000C I2C Clock Divider Low register */ + uint32 CKH; /**< 0x0010 I2C Clock Divider High register */ + uint32 CNT; /**< 0x0014 I2C Data Count register */ + uint32 DRR; /**< 0x0018: I2C Data Receive register, */ + uint32 SAR; /**< 0x001C I2C Slave Address register */ + uint32 DXR; /**< 0x0020: I2C Data Transmit register, */ + uint32 MDR; /**< 0x0024 I2C Mode register */ + uint32 IVR; /**< 0x0028 I2C Interrupt Vector register */ + uint32 EMDR; /**< 0x002C I2C Extended Mode register */ + uint32 PSC; /**< 0x0030 I2C Prescaler register */ + uint32 PID11; /**< 0x0034 I2C Peripheral ID register 1 */ + uint32 PID12; /**< 0x0038 I2C Peripheral ID register 2 */ + uint32 DMACR; /**< 0x003C I2C DMA Control Register */ + uint32 rsvd7; /**< 0x0040 Reserved */ + uint32 rsvd8; /**< 0x0044 Reserved */ + uint32 PFNC; /**< 0x0048 Pin Function Register */ + uint32 DIR; /**< 0x004C Pin Direction Register */ + uint32 DIN; /**< 0x0050 Pin Data In Register */ + uint32 DOUT; /**< 0x0054 Pin Data Out Register */ + uint32 SET; /**< 0x0058 Pin Data Set Register */ + uint32 CLR; /**< 0x005C Pin Data Clr Register */ + uint32 PDR; /**< 0x0060 Pin Open Drain Output Enable Register */ + uint32 PDIS; /**< 0x0064 Pin Pullup/Pulldown Disable Register */ + uint32 PSEL; /**< 0x0068 Pin Pullup/Pulldown Selection Register */ + uint32 PSRS; /**< 0x006C Pin Slew Rate Select Register */ +} i2cBASE_t; + +/** @def i2cREG1 + * @brief I2C Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C module registers. + */ +#define i2cREG1 ( ( i2cBASE_t * ) 0xFFF7D400U ) + +/** @def i2cREG2 + * @brief I2C2 Register Frame Pointer + * + * This pointer is used by the I2C driver to access the I2C2 module registers. + */ +#define i2cREG2 ( ( i2cBASE_t * ) 0xFFF7D500U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @def i2cPORT1 + * @brief I2C1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C1 + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT1 ( ( gioPORT_t * ) 0xFFF7D44CU ) + +/** @def i2cPORT2 + * @brief I2C2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of I2C2 + * (use the GIO drivers to access the port pins). + */ +#define i2cPORT2 ( ( gioPORT_t * ) 0xFFF7D54CU ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h new file mode 100644 index 00000000000..61966cc2d03 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_l2ramw.h @@ -0,0 +1,93 @@ +/** @file reg_l2ramw.h + * @brief L2RAMW Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_L2RAMW_H__ +#define __REG_L2RAMW_H__ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* L2ram Register Frame Definition */ +/** @struct l2ramwBase + * @brief L2RAMW Wrapper Register Frame Definition + * + * This type is used to access the L2RAMW Wrapper Registers. + */ +/** @typedef l2ramwBASE_t + * @brief L2RAMW Wrapper Register Frame Type Definition + * + * This type is used to access the L2RAMW Wrapper Registers. + */ + +typedef volatile struct l2ramwBase +{ + uint32 RAMCTRL; /* 0x0000 */ + uint32 rsvd1[ 3 ]; /* 0x0004 */ + uint32 RAMERRSTATUS; /* 0x0010 */ + uint32 rsvd2[ 4 ]; /* 0x0014 */ + uint32 DIAGDATAVECTOR_H; /* 0x0024 */ + uint32 DIAGDATAVECTOR_L; /* 0x0028 */ + uint32 DIAG_ECC; /* 0x002C */ + uint32 RAMTEST; /* 0x0030 */ + uint32 rsvd3; /* 0x0034 */ + uint32 RAMADDRDECVECT; /* 0x0038 */ + uint32 MEMINITDOMAIN; /* 0x003C */ + uint32 rsvd4; /* 0x0040 */ + uint32 BANKDOMAINMAP0; /* 0x0044 */ + uint32 BANKDOMAINMAP1; /* 0x0048 */ +} l2ramwBASE_t; + +#define l2ramwREG ( ( l2ramwBASE_t * ) ( 0xFFFFF900U ) ) + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h new file mode 100644 index 00000000000..31681e21ef8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_lin.h @@ -0,0 +1,138 @@ +/** @file reg_lin.h + * @brief LIN Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the LIN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_LIN_H__ +#define __REG_LIN_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Lin Register Frame Definition */ +/** @struct linBase + * @brief LIN Base Register Definition + * + * This structure is used to access the LIN module registers. + */ +/** @typedef linBASE_t + * @brief LIN Register Frame Type Definition + * + * This type is used to access the LIN Registers. + */ + +typedef volatile struct linBase +{ + uint32 GCR0; /**< 0x0000: Global control register 0 */ + uint32 GCR1; /**< 0x0004: Global control register 1 */ + uint32 GCR2; /**< 0x0008: Global control register 2 */ + uint32 SETINT; /**< 0x000C: Set interrupt enable register */ + uint32 CLEARINT; /**< 0x0010: Clear interrupt enable register */ + uint32 SETINTLVL; /**< 0x0014: Set interrupt level register */ + uint32 CLEARINTLVL; /**< 0x0018: Set interrupt level register */ + uint32 FLR; /**< 0x001C: interrupt flag register */ + uint32 INTVECT0; /**< 0x0020: interrupt vector Offset 0 */ + uint32 INTVECT1; /**< 0x0024: interrupt vector Offset 1 */ + uint32 FORMAT; /**< 0x0028: Format Control Register */ + uint32 BRS; /**< 0x002C: Baud rate selection register */ + uint32 ED; /**< 0x0030: Emulation register */ + uint32 RD; /**< 0x0034: Receive data register */ + uint32 TD; /**< 0x0038: Transmit data register */ + uint32 PIO0; /**< 0x003C: Pin function register */ + uint32 PIO1; /**< 0x0040: Pin direction register */ + uint32 PIO2; /**< 0x0044: Pin data in register */ + uint32 PIO3; /**< 0x0048: Pin data out register */ + uint32 PIO4; /**< 0x004C: Pin data set register */ + uint32 PIO5; /**< 0x0050: Pin data clr register */ + uint32 PIO6; /**< 0x0054: Pin open drain output enable register */ + uint32 PIO7; /**< 0x0058: Pin pullup/pulldown disable register */ + uint32 PIO8; /**< 0x005C: Pin pullup/pulldown selection register */ + uint32 COMP; /**< 0x0060: Compare register */ + uint8 RDx[ 8U ]; /**< 0x0064-0x0068: RX buffer register */ + uint32 MASK; /**< 0x006C: Mask register */ + uint32 ID; /**< 0x0070: Identification Register */ + uint8 TDx[ 8U ]; /**< 0x0074-0x0078: TX buffer register */ + uint32 MBRSR; /**< 0x007C: Maximum baud rate selection register */ + uint32 rsvd1[ 4U ]; /**< 0x0080 - 0x8C: Reserved */ + uint32 IODFTCTRL; /**< 0x0090: IODFT loopback register */ +} linBASE_t; + +/** @def linREG1 + * @brief LIN1 Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin1 module registers. + */ +#define linREG1 ( ( linBASE_t * ) 0xFFF7E400U ) + +/** @def linPORT1 + * @brief LIN1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN1 + * (use the GIO drivers to access the port pins). + */ +#define linPORT1 ( ( gioPORT_t * ) 0xFFF7E440U ) + +/** @def linREG2 + * @brief LIN2 Register Frame Pointer + * + * This pointer is used by the LIN driver to access the lin2 module registers. + */ +#define linREG2 ( ( linBASE_t * ) 0xFFF7E600U ) + +/** @def linPORT2 + * @brief LIN2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of LIN2 + * (use the GIO drivers to access the port pins). + */ +#define linPORT2 ( ( gioPORT_t * ) 0xFFF7E640U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h new file mode 100644 index 00000000000..bb175ba4d0c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_mibspi.h @@ -0,0 +1,311 @@ +/** @file reg_mibspi.h + * @brief MIBSPI Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the MIBSPI driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_MIBSPI_H__ +#define __REG_MIBSPI_H__ + +#include "sys_common.h" +#include "reg_gio.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Mibspi Register Frame Definition */ +/** @struct mibspiBase + * @brief MIBSPI Register Definition + * + * This structure is used to access the MIBSPI module registers. + */ +/** @typedef mibspiBASE_t + * @brief MIBSPI Register Frame Type Definition + * + * This type is used to access the MIBSPI Registers. + */ +typedef volatile struct mibspiBase +{ + uint32 GCR0; /**< 0x0000: Global Control 0 */ + uint32 GCR1; /**< 0x0004: Global Control 1 */ + uint32 INT0; /**< 0x0008: Interrupt Register */ + uint32 LVL; /**< 0x000C: Interrupt Level */ + uint32 FLG; /**< 0x0010: Interrupt flags */ + uint32 PC0; /**< 0x0014: Function Pin Enable */ + uint32 PC1; /**< 0x0018: Pin Direction */ + uint32 PC2; /**< 0x001C: Pin Input Latch */ + uint32 PC3; /**< 0x0020: Pin Output Latch */ + uint32 PC4; /**< 0x0024: Output Pin Set */ + uint32 PC5; /**< 0x0028: Output Pin Clr */ + uint32 PC6; /**< 0x002C: Open Drain Output Enable */ + uint32 PC7; /**< 0x0030: Pullup/Pulldown Disable */ + uint32 PC8; /**< 0x0034: Pullup/Pulldown Selection */ + uint32 DAT0; /**< 0x0038: Transmit Data */ + uint32 DAT1; /**< 0x003C: Transmit Data with Format and Chip Select */ + uint32 BUF; /**< 0x0040: Receive Buffer */ + uint32 EMU; /**< 0x0044: Emulation Receive Buffer */ + uint32 DELAY; /**< 0x0048: Delays */ + uint32 DEF; /**< 0x004C: Default Chip Select */ + uint32 FMT0; /**< 0x0050: Data Format 0 */ + uint32 FMT1; /**< 0x0054: Data Format 1 */ + uint32 FMT2; /**< 0x0058: Data Format 2 */ + uint32 FMT3; /**< 0x005C: Data Format 3 */ + uint32 INTVECT0; /**< 0x0060: Interrupt Vector 0 */ + uint32 INTVECT1; /**< 0x0064: Interrupt Vector 1 */ + uint32 rsvd3; /**< 0x0068: Slew Rate Select */ + uint32 PMCTRL; /**< 0x006C: Parallel Mode Control */ + uint32 MIBSPIE; /**< 0x0070: Multi-buffer Mode Enable */ + uint32 TGITENST; /**< 0x0074: TG Interrupt Enable Set */ + uint32 TGITENCR; /**< 0x0078: TG Interrupt Enable Clear */ + uint32 TGITLVST; /**< 0x007C: Transfer Group Interrupt Level Set */ + uint32 TGITLVCR; /**< 0x0080: Transfer Group Interrupt Level Clear */ + uint32 TGINTFLG; /**< 0x0084: Transfer Group Interrupt Flag */ + uint32 rsvd1[ 2U ]; /**< 0x0088: Reserved */ + uint32 TICKCNT; /**< 0x0090: Tick Counter */ + uint32 LTGPEND; /**< 0x0090: Last TG End Pointer */ + uint32 TGCTRL[ 16U ]; /**< 0x0098 - 0x00D4: Transfer Group Control */ + uint32 DMACTRL[ 8U ]; /**< 0x00D8 - 0x00F4: DMA Control */ + uint32 DMACOUNT[ 8U ]; /**< 0x00F8 - 0x0114: DMA Count */ + uint32 DMACNTLEN; /**< 0x0118 - 0x0114: DMA Control length */ + uint32 rsvd2; /**< 0x011C: Reserved */ + uint32 PAR_ECC_CTRL; /**< 0x0120: Multi-buffer RAM Uncorrectable Parity Error Control + */ + uint32 UERRSTAT; /**< 0x0124: Multi-buffer RAM Uncorrectable Parity Error Status */ + uint32 UERRADDRRX; /**< 0x0128: RXRAM Uncorrectable Parity Error Address */ + uint32 UERRADDRTX; /**< 0x012C: TXRAM Uncorrectable Parity Error Address */ + uint32 RXOVRN_BUF_ADDR; /**< 0x0130: RXRAM Overrun Buffer Address */ + uint32 IOLPKTSTCR; /**< 0x0134: IO loopback */ + uint32 EXT_PRESCALE1; /**< 0x0138: SPI Extended Prescale Register 1*/ + uint32 EXT_PRESCALE2; /**< 0x013C: SPI Extended Prescale Register 2*/ + uint32 ECCDIAG_CTRL; /**< 0x0140: ECC Diagnostic Control register*/ + uint32 ECCDIAG_STAT; /**< 0x0144: ECC Diagnostic Status register*/ + uint32 SBERRADDR1; /**< 0x0148: */ + uint8 rsvd4[ 6 ]; /**< 0x014C-0x152: Single Bit Error Address Register - RXRAM*/ + uint32 SBERRADDR0; /**< 0x0152: Single Bit Error Address Register - TXRAM*/ + +} mibspiBASE_t; + +/** @def mibspiREG1 + * @brief MIBSPI1 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG1 ( ( mibspiBASE_t * ) 0xFFF7F400U ) + +/** @def mibspiPORT1 + * @brief MIBSPI1 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI1 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT1 ( ( gioPORT_t * ) 0xFFF7F418U ) + +/** @def mibspiREG2 + * @brief MIBSPI2 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG2 ( ( mibspiBASE_t * ) 0xFFF7F600U ) + +/** @def mibspiPORT2 + * @brief MIBSPI2 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI2 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT2 ( ( gioPORT_t * ) 0xFFF7F618U ) + +/** @def mibspiREG3 + * @brief MIBSPI3 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG3 ( ( mibspiBASE_t * ) 0xFFF7F800U ) + +/** @def mibspiPORT3 + * @brief MIBSPI3 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI3 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT3 ( ( gioPORT_t * ) 0xFFF7F818U ) + +/** @def mibspiREG4 + * @brief MIBSPI4 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG4 ( ( mibspiBASE_t * ) 0xFFF7FA00U ) + +/** @def mibspiPORT4 + * @brief MIBSPI4 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI4 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT4 ( ( gioPORT_t * ) 0xFFF7FA18U ) + +/** @def mibspiREG5 + * @brief MIBSPI5 Register Frame Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi module registers. + */ +#define mibspiREG5 ( ( mibspiBASE_t * ) 0xFFF7FC00U ) + +/** @def mibspiPORT5 + * @brief MIBSPI5 GIO Port Register Pointer + * + * Pointer used by the GIO driver to access I/O PORT of MIBSPI5 + * (use the GIO drivers to access the port pins). + */ +#define mibspiPORT5 ( ( gioPORT_t * ) 0xFFF7FC18U ) + +/** @struct mibspiRamBase + * @brief MIBSPI Buffer RAM Definition + * + * This structure is used to access the MIBSPI buffer memory. + */ +/** @typedef mibspiRAM_t + * @brief MIBSPI RAM Type Definition + * + * This type is used to access the MIBSPI RAM. + */ +typedef volatile struct mibspiRamBase +{ + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< tx buffer data */ + uint16 control; /**< tx buffer control */ +#else + uint16 control; /**< tx buffer control */ + uint16 data; /**< tx buffer data */ +#endif + } tx[ 128 ]; + struct + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + uint16 data; /**< rx buffer data */ + uint16 flags; /**< rx buffer flags */ +#else + uint16 flags; /**< rx buffer flags */ + uint16 data; /**< rx buffer data */ +#endif + } rx[ 128 ]; +} mibspiRAM_t; + +/** @def mibspiRAM1 + * @brief MIBSPI1 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM1 ( ( mibspiRAM_t * ) 0xFF0E0000U ) + +/** @def mibspiRAM2 + * @brief MIBSPI2 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM2 ( ( mibspiRAM_t * ) 0xFF080000U ) + +/** @def mibspiRAM3 + * @brief MIBSPI3 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM3 ( ( mibspiRAM_t * ) 0xFF0C0000U ) + +/** @def mibspiRAM4 + * @brief MIBSPI4 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM4 ( ( mibspiRAM_t * ) 0xFF060000U ) + +/** @def mibspiRAM5 + * @brief MIBSPI5 Buffer RAM Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiRAM5 ( ( mibspiRAM_t * ) 0xFF0A0000U ) + +/** @def mibspiPARRAM1 + * @brief MIBSPI1 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM1 ( *( volatile uint32 * ) ( 0xFF0E0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM2 + * @brief MIBSPI2 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM2 ( *( volatile uint32 * ) ( 0xFF080000U + 0x00000400U ) ) + +/** @def mibspiPARRAM3 + * @brief MIBSPI3 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM3 ( *( volatile uint32 * ) ( 0xFF0C0000U + 0x00000400U ) ) + +/** @def mibspiPARRAM4 + * @brief MIBSPI4 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM4 ( *( volatile uint32 * ) ( 0xFF060000U + 0x00000400U ) ) + +/** @def mibspiPARRAM5 + * @brief MIBSPI5 Buffer RAM PARITY Pointer + * + * This pointer is used by the MIBSPI driver to access the mibspi buffer memory. + */ +#define mibspiPARRAM5 ( *( volatile uint32 * ) ( 0xFF0A0000U + 0x00000400U ) ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h new file mode 100644 index 00000000000..6566787f24a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_nmpu.h @@ -0,0 +1,98 @@ +/** @file reg_nmpu.h + * @brief NMPU Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_NMPU_H__ +#define __REG_NMPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* NMPU Register Frame Definition */ +/** @struct nmpuBASE_t + * @brief nmpuBASE Register Definition + * + * This structure is used to access the NMPU module registers. + */ +typedef volatile struct nmpuBase +{ + uint32 MPUREV; /**< 0x0000 MPU Revision ID Register */ + uint32 MPULOCK; /**< 0x0004 MPU Lock Register */ + uint32 MPUDIAGCTRL; /**< 0x0008 MPU Diagnostics Control Register */ + uint32 MPUDIAGADDR; /**< 0x000C MPU Diagnostic Address Register */ + uint32 MPUERRSTAT; /**< 0x0010 MPU Error Status Register */ + uint32 MPUERRADDR; /**< 0x0014 MPU Error Address Register */ + uint32 MPUIAM; /**< 0x0018 MPU Input Address Mask Register */ + uint32 rsvd1; /**< 0x001C Reserved */ + uint32 MPUCTRL1; /**< 0x0020 MPU Control Register 1 */ + uint32 MPUCTRL2; /**< 0x0024 MPU Control Register 2 */ + uint32 rsvd2; /**< 0x0028 Reserved */ + uint32 MPUTYPE; /**< 0x002C MPU Type Register */ + uint32 MPUREGBASE; /**< 0x0030 MPU Region Base Address Register */ + uint32 MPUREGSENA; /**< 0x0034 MPU Region Size and Enable Register */ + uint32 MPUREGACR; /**< 0x0038 MPU Region Access Control Register */ + uint32 MPUREGNUM; /**< 0x003C MPU Region Number Register */ +} nmpuBASE_t; + +#define nmpu_emacREG ( ( nmpuBASE_t * ) 0xFCFF1800U ) +#define nmpu_dmaREG ( ( nmpuBASE_t * ) 0xFFFF1A00U ) +#define nmpu_ps_scr_sREG ( ( nmpuBASE_t * ) 0xFFFF1800U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h new file mode 100644 index 00000000000..d60aa405008 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pbist.h @@ -0,0 +1,96 @@ +/** @file reg_pbist.h + * @brief PBIST Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PBIST_H__ +#define __REG_PBIST_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* PBIST Register Frame Definition */ +/** @struct pbistBase + * @brief PBIST Base Register Definition + * + * This structure is used to access the PBIST module registers. + */ +/** @typedef pbistBASE_t + * @brief PBIST Register Frame Type Definition + * + * This type is used to access the PBIST Registers. + */ +typedef volatile struct pbistBase +{ + uint32 RAMT; /* 0x0160: RAM Configuration Register */ + uint32 DLR; /* 0x0164: Datalogger Register */ + uint32 rsvd1[ 6U ]; /* 0x0168 */ + uint32 PACT; /* 0x0180: PBIST Activate Register */ + uint32 PBISTID; /* 0x0184: PBIST ID Register */ + uint32 OVER; /* 0x0188: Override Register */ + uint32 rsvd2; /* 0x018C */ + uint32 FSRF0; /* 0x0190: Fail Status Fail Register 0 */ + uint32 FSRF1; /* 0x0194: Fail Status Fail Register 1 */ + uint32 FSRC0; /* 0x0198: Fail Status Count Register 0 */ + uint32 FSRC1; /* 0x019C: Fail Status Count Register 1 */ + uint32 FSRA0; /* 0x01A0: Fail Status Address 0 Register */ + uint32 FSRA1; /* 0x01A4: Fail Status Address 1 Register */ + uint32 FSRDL0; /* 0x01A8: Fail Status Data Register 0 */ + uint32 rsvd3; /* 0x01AC */ + uint32 FSRDL1; /* 0x01B0: Fail Status Data Register 1 */ + uint32 rsvd4[ 3U ]; /* 0x01B4 */ + uint32 ROM; /* 0x01C0: ROM Mask Register */ + uint32 ALGO; /* 0x01C4: Algorithm Mask Register */ + uint32 RINFOL; /* 0x01C8: RAM Info Mask Lower Register */ + uint32 RINFOU; /* 0x01CC: RAM Info Mask Upper Register */ +} pbistBASE_t; + +#define pbistREG ( ( pbistBASE_t * ) 0xFFFFE560U ) + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h new file mode 100644 index 00000000000..c7454be31f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pcr.h @@ -0,0 +1,149 @@ +/** @file reg_pcr.h + * @brief PCR Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PCR_H__ +#define __REG_PCR_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Pcr Register Frame Definition */ +/** @struct pcrBase + * @brief Pcr Register Frame Definition + * + * This type is used to access the Pcr Registers. + */ +/** @typedef pcrBASE_t + * @brief PCR Register Frame Type Definition + * + * This type is used to access the PCR Registers. + */ +typedef volatile struct pcrBase +{ + uint32 PMPROTSET0; /* 0x0000 */ + uint32 PMPROTSET1; /* 0x0004 */ + uint32 rsvd1[ 2U ]; /* 0x0008 */ + uint32 PMPROTCLR0; /* 0x0010 */ + uint32 PMPROTCLR1; /* 0x0014 */ + uint32 rsvd2[ 2U ]; /* 0x0018 */ + uint32 PPROTSET0; /* 0x0020 */ + uint32 PPROTSET1; /* 0x0024 */ + uint32 PPROTSET2; /* 0x0028 */ + uint32 PPROTSET3; /* 0x002C */ + uint32 rsvd3[ 4U ]; /* 0x0030 */ + uint32 PPROTCLR0; /* 0x0040 */ + uint32 PPROTCLR1; /* 0x0044 */ + uint32 PPROTCLR2; /* 0x0048 */ + uint32 PPROTCLR3; /* 0x004C */ + uint32 rsvd4[ 4U ]; /* 0x0050 */ + uint32 PCSPWRDWNSET0; /* 0x0060 */ + uint32 PCSPWRDWNSET1; /* 0x0064 */ + uint32 rsvd5[ 2U ]; /* 0x0068 */ + uint32 PCSPWRDWNCLR0; /* 0x0070 */ + uint32 PCSPWRDWNCLR1; /* 0x0074 */ + uint32 rsvd6[ 2U ]; /* 0x0078 */ + uint32 PSPWRDWNSET0; /* 0x0080 */ + uint32 PSPWRDWNSET1; /* 0x0084 */ + uint32 PSPWRDWNSET2; /* 0x0088 */ + uint32 PSPWRDWNSET3; /* 0x008C */ + uint32 rsvd7[ 4U ]; /* 0x0090 */ + uint32 PSPWRDWNCLR0; /* 0x00A0 */ + uint32 PSPWRDWNCLR1; /* 0x00A4 */ + uint32 PSPWRDWNCLR2; /* 0x00A8 */ + uint32 PSPWRDWNCLR3; /* 0x00AC */ + uint32 rsvd8[ 4U ]; /* 0x00B0 */ + uint32 PDPWRDWNSET; /* 0x00C0 */ + uint32 PDPWRDWNCLR; /* 0x00C4 */ + uint32 rsvd9[ 78U ]; /* 0x00C8 */ + uint32 MSTIDWRENA; /* 0x0200 */ + uint32 MSTIDENA; /* 0x0204 */ + uint32 MSTIDDIAGCTRL; /* 0x0208 */ + uint32 rsvd10[ 61U ]; /* 0x020C */ + struct + { + uint32 PSxMSTID_L; + uint32 PSxMSTID_H; + } PSxMSTID[ 32 ]; /* 0x0300 */ + struct + { + uint32 PPSxMSTID_L; + uint32 PPSxMSTID_H; + } PPSxMSTID[ 8 ]; /* 0x0400 */ + struct + { + uint32 PPSExMSTID_L; + uint32 PPSExMSTID_H; + } PPSExMSTID[ 32 ]; /* 0x0440 */ + uint32 PCSxMSTID[ 32 ]; /* 0x0540 */ + uint32 PPCSxMSTID[ 8 ]; /* 0x05C0 */ +} pcrBASE_t; + +/** @def pcrREG1 + * @brief Pcr1 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr1 registers. + */ +#define pcrREG1 ( ( pcrBASE_t * ) 0xFFFF1000U ) + +/** @def pcrREG2 + * @brief Pcr2 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr2 registers. + */ +#define pcrREG2 ( ( pcrBASE_t * ) 0xFCFF1000U ) + +/** @def pcrREG3 + * @brief Pcr3 Register Frame Pointer + * + * This pointer is used by the system driver to access the Pcr3 registers. + */ +#define pcrREG3 ( ( pcrBASE_t * ) 0xFFF78000U ) +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h new file mode 100644 index 00000000000..e26018aa2ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/reg_pinmux.h @@ -0,0 +1,101 @@ +/** @file reg_pinmux.h + * @brief PINMUX Register Layer Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PINMUX driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __REG_PINMUX_H__ +#define __REG_PINMUX_H__ + +#include "sys_common.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @struct pinMuxBase + * @brief PINMUX Register Definition + * + * This structure is used to access the PINMUX module registers. + */ +/** @typedef pinMuxBASE_t + * @brief PINMUX Register Frame Type Definition + * + * This type is used to access the PINMUX Registers. + */ +typedef volatile struct pinMuxBase +{ + uint32 REVISION_REG; /**< 0x00: Revision Register */ + uint32 rsvd1[ 7 ]; /** address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [11]: + * - 0: Read + * - 1: Write + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetDataFault_( void ); + +/** @fn void _coreClearDataFault_(void) + * @brief Clear core data fault status register + */ +void _coreClearDataFault_( void ); + +/** @fn uint32 _coreGetInstructionFault_(void) + * @brief Get core instruction fault status register + * @return The function will return the instruction fault status register value: + * - bit [10,3..0]: + * - 0b00001: Alignment -> address is valid + * - 0b00000: Background -> address is valid + * - 0b01101: Permission -> address is valid + * - 0b01000: Precise External Abort -> address is valid + * - 0b10110: Imprecise External Abort -> address is + * unpredictable + * - 0b11001: Precise ECC Error -> address is valid + * - 0b11000: Imprecise ECC Error -> address is + * unpredictable + * - 0b00010: Debug -> address is unchanged + * - bit [12]: + * - 0: AXI Decode Error (DECERR) + * - 1: AXI Slave Error (SLVERR) + */ +uint32 _coreGetInstructionFault_( void ); + +/** @fn void _coreClearInstructionFault_(void) + * @brief Clear core instruction fault status register + */ +void _coreClearInstructionFault_( void ); + +/** @fn uint32 _coreGetDataFaultAddress_(void) + * @brief Get core data fault address register + * @return The function will return the data fault address: + */ +uint32 _coreGetDataFaultAddress_( void ); + +/** @fn void _coreClearDataFaultAddress_(void) + * @brief Clear core data fault address register + */ +void _coreClearDataFaultAddress_( void ); + +/** @fn uint32 _coreGetInstructionFaultAddress_(void) + * @brief Get core instruction fault address register + * @return The function will return the instruction fault address: + */ +uint32 _coreGetInstructionFaultAddress_( void ); + +/** @fn void _coreClearInstructionFaultAddress_(void) + * @brief Clear core instruction fault address register + */ +void _coreClearInstructionFaultAddress_( void ); + +/** @fn uint32 _coreGetAuxiliaryDataFault_(void) + * @brief Get core auxiliary data fault status register + * @return The function will return the auxiliary data fault status register value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryDataFault_( void ); + +/** @fn void _coreClearAuxiliaryDataFault_(void) + * @brief Clear core auxiliary data fault status register + */ +void _coreClearAuxiliaryDataFault_( void ); + +/** @fn uint32 _coreGetAuxiliaryInstructionFault_(void) + * @brief Get core auxiliary instruction fault status register + * @return The function will return the auxiliary instruction fault status register + * value: + * - bit [13..5]: + * - Index value for access giving error + * - bit [21]: + * - 0: Unrecoverable error + * - 1: Recoverable error + * - bit [23..22]: + * - 0: Side cache + * - 1: Side ATCM (Flash) + * - 2: Side BTCM (RAM) + * - 3: Reserved + * - bit [27..24]: + * - Cache way or way in which error occurred + */ +uint32 _coreGetAuxiliaryInstructionFault_( void ); + +/** @fn void _coreClearAuxiliaryInstructionFault_(void) + * @brief Clear core auxiliary instruction fault status register + */ +void _coreClearAuxiliaryInstructionFault_( void ); + +/** @fn void _disable_IRQ_interrupt_(void) + * @brief Disable IRQ Interrupt mode in CPSR register + * + * This function disables IRQ Interrupt mode in CPSR register. + */ +void _disable_IRQ_interrupt_( void ); + +/** @fn void _enable_IRQ_interrupt_(void) + * @brief Enable IRQ Interrupt mode in CPSR register + * + * This function enables IRQ Interrupt mode in CPSR register. + */ +void _enable_IRQ_interrupt_( void ); + +/** @fn void _enable_interrupt_(void) + * @brief Enable IRQ and FIQ Interrupt mode in CPSR register + * + * This function Enables IRQ and FIQ Interrupt mode in CPSR register. + * User must call this function to enable Interrupts in non-OS environments. + */ +void _enable_interrupt_( void ); + +/** @fn void _esmCcmErrorsClear_(void) + * @brief Clears ESM Error caused due to CCM Errata in RevA Silicon + * + * This function Clears ESM Error caused due to CCM Errata + * in RevA Silicon immediately after powerup. + */ +void _esmCcmErrorsClear_( void ); + +/** @fn void _memInit_(void) + * @brief Initialize RAM + */ +void _memInit_( void ); + +/** @fn void _cacheEnable_(void) + * @brief Initialize RAM + */ +void _cacheEnable_( void ); + +/** @fn void _cacheDisable_(void) + * @brief Enable Cache + */ +void _cacheDisable_( void ); + +/** @fn void _dCacheInvalidate_(void) + * @brief Invalidate DCache. + */ +void _dCacheInvalidate_( void ); + +/** @fn void _iCacheInvalidate_(void) + * @brief Invalidate ICache. + */ +void _iCacheInvalidate_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h new file mode 100644 index 00000000000..79e5348c18e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_dma.h @@ -0,0 +1,300 @@ +/** @file sys_dma.h + * @brief DMA Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef DMA_H_ +#define DMA_H_ + +#include "reg_dma.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +typedef enum dmaChannel +{ + DMA_CH0 = 0U, + DMA_CH1, + DMA_CH2, + DMA_CH3, + DMA_CH4, + DMA_CH5, + DMA_CH6, + DMA_CH7, + DMA_CH8, + DMA_CH9, + DMA_CH10, + DMA_CH11, + DMA_CH12, + DMA_CH13, + DMA_CH14, + DMA_CH15, + DMA_CH16, + DMA_CH17, + DMA_CH18, + DMA_CH19, + DMA_CH20, + DMA_CH21, + DMA_CH22, + DMA_CH23, + DMA_CH24, + DMA_CH25, + DMA_CH26, + DMA_CH27, + DMA_CH28, + DMA_CH29, + DMA_CH30, + DMA_CH31 +} dmaChannel_t; + +typedef enum dmaRequest +{ + DMA_REQ0 = 0U, + DMA_REQ1, + DMA_REQ2, + DMA_REQ3, + DMA_REQ4, + DMA_REQ5, + DMA_REQ6, + DMA_REQ7, + DMA_REQ8, + DMA_REQ9, + DMA_REQ10, + DMA_REQ11, + DMA_REQ12, + DMA_REQ13, + DMA_REQ14, + DMA_REQ15, + DMA_REQ16, + DMA_REQ17, + DMA_REQ18, + DMA_REQ19, + DMA_REQ20, + DMA_REQ21, + DMA_REQ22, + DMA_REQ23, + DMA_REQ24, + DMA_REQ25, + DMA_REQ26, + DMA_REQ27, + DMA_REQ28, + DMA_REQ29, + DMA_REQ30, + DMA_REQ31, + DMA_REQ32, + DMA_REQ33, + DMA_REQ34, + DMA_REQ35, + DMA_REQ36, + DMA_REQ37, + DMA_REQ38, + DMA_REQ39, + DMA_REQ40, + DMA_REQ41, + DMA_REQ42, + DMA_REQ43, + DMA_REQ44, + DMA_REQ45, + DMA_REQ46, + DMA_REQ47 +} dmaRequest_t; + +typedef enum dmaTriggerType +{ + DMA_HW, + DMA_SW +} dmaTriggerType_t; + +typedef enum dmaPriorityQueue +{ + LOWPRIORITY, + HIGHPRIORITY +} dmaPriorityQueue_t; + +typedef enum dmaInterrupt +{ + FTC, /**< Frame transfer complete Interrupt */ + LFS, /**< Last frame transfer started Interrupt */ + HBC, /**< First half of block complete Interrupt */ + BTC /**< Block transfer complete Interrupt */ +} dmaInterrupt_t; + +typedef enum dmaIntGroup +{ + DMA_INTA = 0U, /**< Group A Interrupt */ + DMA_INTB = 1U /**< Group B Interrupt (Reserved for Lock-step devices) */ +} dmaIntGroup_t; + +typedef enum dmaMPURegion +{ + DMA_REGION0 = 0U, + DMA_REGION1 = 1U, + DMA_REGION2 = 2U, + DMA_REGION3 = 3U, + DMA_REGION4 = 4U, + DMA_REGION5 = 5U, + DMA_REGION6 = 6U, + DMA_REGION7 = 7U +} dmaMPURegion_t; + +typedef enum dmaRegionAccess +{ + FULLACCESS = 0U, + READONLY = 1U, + WRITEONLY = 2U, + NOACCESS = 3U +} dmaRegionAccess_t; + +typedef enum dmaMPUInt +{ + INTERRUPT_DISABLE = 0U, + INTERRUPTA_ENABLE = 1U, + INTERRUPTB_ENABLE = 3U +} dmaMPUInt_t; + +enum dmaPort +{ + PORTB_READ_PORTB_WRITE = 0x3U, + PORTA_READ_PORTA_WRITE = 0x2U, + PORTA_READ_PORTB_WRITE = 0x1U, + PORTB_READ_PORTA_WRITE = 0x0U +}; + +enum dmaElementSize +{ + ACCESS_8_BIT = 0U, + ACCESS_16_BIT = 1U, + ACCESS_32_BIT = 2U, + ACCESS_64_BIT = 3U +}; + +enum dmaTransferType +{ + FRAME_TRANSFER = 0U, + BLOCK_TRANSFER = 1U +}; + +enum dmaAddressMode +{ + ADDR_FIXED = 0U, + ADDR_INC1 = 1U, + ADDR_OFFSET = 3U +}; + +enum dmaAutoInitMode +{ + AUTOINIT_OFF = 0U, + AUTOINIT_ON = 1U +}; + +typedef struct dmaCTRLPKT +{ + uint32 SADD; /* Initial source address */ + uint32 DADD; /* Initial destination address */ + uint32 CHCTRL; /* Next channel to be triggered + 1 */ + uint32 FRCNT; /* Frame count */ + uint32 ELCNT; /* Element count */ + uint32 ELDOFFSET; /* Element destination offset */ + uint32 ELSOFFSET; /* Element source offset */ + uint32 FRDOFFSET; /* Frame destination offset */ + uint32 FRSOFFSET; /* Frame source offset */ + uint32 PORTASGN; /* DMA port */ + uint32 RDSIZE; /* Read element size */ + uint32 WRSIZE; /* Write element size */ + uint32 TTYPE; /* Trigger type - frame/block */ + uint32 ADDMODERD; /* Addressing mode for source */ + uint32 ADDMODEWR; /* Addressing mode for destination */ + uint32 AUTOINIT; /* Auto-init mode */ +} g_dmaCTRL; + +void dmaEnable( void ); +void dmaDisable( void ); +void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT ); +void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type ); +void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline ); +void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority ); +void dmaEnableInterrupt( dmaChannel_t channel, + dmaInterrupt_t inttype, + dmaIntGroup_t group ); +void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype ); +void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add ); +void dmaEnableRegion( dmaMPURegion_t region, + dmaRegionAccess_t access, + dmaMPUInt_t intenable ); +void dmaDisableRegion( dmaMPURegion_t region ); +void dmaEnableECC( void ); +void dmaDisableECC( void ); + +uint32 dmaGetReq( dmaChannel_t channel ); +boolean dmaIsBusy( void ); +boolean dmaIsChannelActive( dmaChannel_t channel ); +boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype ); + +/** @fn void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel) + * @brief Interrupt callback + * @param[in] inttype Interrupt type + * - FTC + * - LFS + * - HBC + * - BTC + * @param[in] channel channel number 0..15 + * This is a callback that is provided by the application and is called apon + * an interrupt. The parameter passed to the callback is a copy of the + * interrupt flag register. + */ +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif /* DMA_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h new file mode 100644 index 00000000000..312c6265444 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_mpu.h @@ -0,0 +1,612 @@ +/** @file sys_mpu.h + * @brief System Mpu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Mpu Interface Functions + * . + * which are relevant for the memory protection unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_MPU_H__ +#define __SYS_MPU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def mpuREGION1 + * @brief Mpu region 1 + * + * Alias for Mpu region 1 + */ +#define mpuREGION1 0U + +/** @def mpuREGION2 + * @brief Mpu region 2 + * + * Alias for Mpu region 1 + */ +#define mpuREGION2 1U + +/** @def mpuREGION3 + * @brief Mpu region 3 + * + * Alias for Mpu region 3 + */ +#define mpuREGION3 2U + +/** @def mpuREGION4 + * @brief Mpu region 4 + * + * Alias for Mpu region 4 + */ +#define mpuREGION4 3U + +/** @def mpuREGION5 + * @brief Mpu region 5 + * + * Alias for Mpu region 5 + */ +#define mpuREGION5 4U + +/** @def mpuREGION6 + * @brief Mpu region 6 + * + * Alias for Mpu region 6 + */ +#define mpuREGION6 5U + +/** @def mpuREGION7 + * @brief Mpu region 7 + * + * Alias for Mpu region 7 + */ +#define mpuREGION7 6U + +/** @def mpuREGION8 + * @brief Mpu region 8 + * + * Alias for Mpu region 8 + */ +#define mpuREGION8 7U + +/** @def mpuREGION9 + * @brief Mpu region 9 + * + * Alias for Mpu region 9 + */ +#define mpuREGION9 8U + +/** @def mpuREGION10 + * @brief Mpu region 10 + * + * Alias for Mpu region 10 + */ +#define mpuREGION10 9U + +/** @def mpuREGION11 + * @brief Mpu region 11 + * + * Alias for Mpu region 11 + */ +#define mpuREGION11 10U + +/** @def mpuREGION12 + * @brief Mpu region 12 + * + * Alias for Mpu region 12 + */ +#define mpuREGION12 11U + +/** @def mpuREGION13 + * @brief Mpu region 13 + * + * Alias for Mpu region 13 + */ +#define mpuREGION13 12U + +/** @def mpuREGION14 + * @brief Mpu region 14 + * + * Alias for Mpu region 14 + */ +#define mpuREGION14 13U + +/** @def mpuREGION15 + * @brief Mpu region 15 + * + * Alias for Mpu region 15 + */ +#define mpuREGION15 14U + +/** @def mpuREGION16 + * @brief Mpu region 16 + * + * Alias for Mpu region 16 + */ +#define mpuREGION16 15U + +/** @def mpuREGION_ENABLE + * @brief Enable MPU Region + * + * Alias for MPU region enable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_ENABLE 1U + +/** @def mpuREGION_DISABLE + * @brief Disable MPU Region + * + * Alias for MPU region disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuREGION_DISABLE 0U + +/** @def mpuSUBREGION0_DISABLE + * @brief Disable MPU Sub Region0 + * + * Alias for MPU subregion0 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION0_DISABLE 0x100U + +/** @def mpuSUBREGION1_DISABLE + * @brief Disable MPU Sub Region1 + * + * Alias for MPU subregion1 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION1_DISABLE 0x200U + +/** @def mpuSUBREGION2_DISABLE + * @brief Disable MPU Sub Region2 + * + * Alias for MPU subregion2 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION2_DISABLE 0x400U + +/** @def mpuSUBREGION3_DISABLE + * @brief Disable MPU Sub Region3 + * + * Alias for MPU subregion3 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION3_DISABLE 0x800U + +/** @def mpuSUBREGION4_DISABLE + * @brief Disable MPU Sub Region4 + * + * Alias for MPU subregion4 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION4_DISABLE 0x1000U + +/** @def mpuSUBREGION5_DISABLE + * @brief Disable MPU Sub Region5 + * + * Alias for MPU subregion5 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION5_DISABLE 0x2000U + +/** @def mpuSUBREGION6_DISABLE + * @brief Disable MPU Sub Region6 + * + * Alias for MPU subregion6 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION6_DISABLE 0x4000U + +/** @def mpuSUBREGION7_DISABLE + * @brief Disable MPU Sub Region7 + * + * Alias for MPU subregion7 disable. + * + * @note This should be used as the parameter of the API _mpuSetRegionSizeRegister_ + */ +#define mpuSUBREGION7_DISABLE 0x8000U + +/** @enum mpuRegionAccessPermission + * @brief Alias names for mpu region access permissions + * + * This enumeration is used to provide alias names for the mpu region access permission: + * - MPU_PRIV_NA_USER_NA_EXEC no access in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RW_USER_NA_EXEC read/write in privileged mode, no access in user mode + * and execute + * - MPU_PRIV_RW_USER_RO_EXEC read/write in privileged mode, read only in user mode + * and execute + * - MPU_PRIV_RW_USER_RW_EXEC read/write in privileged mode, read/write in user mode + * and execute + * - MPU_PRIV_RO_USER_NA_EXEC read only in privileged mode, no access in user mode and + * execute + * - MPU_PRIV_RO_USER_RO_EXEC read only in privileged mode, read only in user mode and + * execute + * - MPU_PRIV_NA_USER_NA_NOEXEC no access in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC read/write in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC read/write in privileged mode, read only in user mode + * and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC read/write in privileged mode, read/write in user mode + * and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC read only in privileged mode, no access in user mode + * and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC read only in privileged mode, read only in user mode + * and no execution + * + */ +enum mpuRegionAccessPermission +{ + MPU_PRIV_NA_USER_NA_EXEC = 0x0000U, /**< Alias no access in privileged mode, no access + in user mode and execute */ + MPU_PRIV_RW_USER_NA_EXEC = 0x0100U, /**< Alias no read/write in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RW_USER_RO_EXEC = 0x0200U, /**< Alias no read/write in privileged mode, read + only in user mode and execute */ + MPU_PRIV_RW_USER_RW_EXEC = 0x0300U, /**< Alias no read/write in privileged mode, + read/write in user mode and execute */ + MPU_PRIV_RO_USER_NA_EXEC = 0x0500U, /**< Alias no read only in privileged mode, no + access in user mode and execute */ + MPU_PRIV_RO_USER_RO_EXEC = 0x0600U, /**< Alias no read only in privileged mode, read + only in user mode and execute */ + MPU_PRIV_NA_USER_NA_NOEXEC = 0x1000U, /**< Alias no access in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_NA_NOEXEC = 0x1100U, /**< Alias no read/write in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RW_USER_RO_NOEXEC = 0x1200U, /**< Alias no read/write in privileged mode, + read only in user mode and no execution */ + MPU_PRIV_RW_USER_RW_NOEXEC = 0x1300U, /**< Alias no read/write in privileged mode, + read/write in user mode and no execution */ + MPU_PRIV_RO_USER_NA_NOEXEC = 0x1500U, /**< Alias no read only in privileged mode, no + access in user mode and no execution */ + MPU_PRIV_RO_USER_RO_NOEXEC = 0x1600U /**< Alias no read only in privileged mode, read + only in user mode and no execution */ +}; + +/** @enum mpuRegionType + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_DEVICE_SHAREABLE Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED Memory type normal outer and inner write-through, + * no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED Memory type normal outer and inner write-through, + * no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED Memory type normal outer and inner write-back, no + * write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_SHARED Memory type normal outer and inner write-back, no + * write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED Memory type normal outer and inner non-cacheable + * and non shared + * - MPU_NORMAL_OINC_SHARED Memory type normal outer and inner non-cacheable + * and shared + * - MPU_NORMAL_OIWBWA_NONSHARED Memory type normal outer and inner write-back, + * write allocate and non shared + * - MPU_NORMAL_OIWBWA_SHARED Memory type normal outer and inner write-back, + * write allocate and shared + * - MPU_DEVICE_NONSHAREABLE Memory type device and non sharable + */ +enum mpuRegionType +{ + MPU_STRONGLYORDERED_SHAREABLE = 0x0000U, /**< Memory type strongly ordered and + sharable */ + MPU_DEVICE_SHAREABLE = 0x0001U, /**< Memory type device and sharable */ + MPU_NORMAL_OIWTNOWA_NONSHARED = 0x0002U, /**< Memory type normal outer and inner + write-through, no write allocate and non + shared */ + MPU_NORMAL_OIWBNOWA_NONSHARED = 0x0003U, /**< Memory type normal outer and inner + write-back, no write allocate and non + shared */ + MPU_NORMAL_OIWTNOWA_SHARED = 0x0006U, /**< Memory type normal outer and inner + write-through, no write allocate and shared + */ + MPU_NORMAL_OIWBNOWA_SHARED = 0x0007U, /**< Memory type normal outer and inner + write-back, no write allocate and shared */ + MPU_NORMAL_OINC_NONSHARED = 0x0008U, /**< Memory type normal outer and inner + non-cacheable and non shared */ + MPU_NORMAL_OIWBWA_NONSHARED = 0x000BU, /**< Memory type normal outer and inner + write-back, write allocate and non shared */ + MPU_NORMAL_OINC_SHARED = 0x000CU, /**< Memory type normal outer and inner + non-cacheable and shared */ + MPU_NORMAL_OIWBWA_SHARED = 0x000FU, /**< Memory type normal outer and inner + write-back, write allocate and shared */ + MPU_DEVICE_NONSHAREABLE = 0x0010U /**< Memory type device and non sharable */ +}; + +/** @enum mpuRegionSize + * @brief Alias names for mpu region type + * + * This enumeration is used to provide alias names for the mpu region type: + * - MPU_STRONGLYORDERED_SHAREABLE Memory type strongly ordered and sharable + * - MPU_32_BYTES Memory size in bytes + * - MPU_64_BYTES Memory size in bytes + * - MPU_128_BYTES Memory size in bytes + * - MPU_256_BYTES Memory size in bytes + * - MPU_512_BYTES Memory size in bytes + * - MPU_1_KB Memory size in kB + * - MPU_2_KB Memory size in kB + * - MPU_4_KB Memory size in kB + * - MPU_8_KB Memory size in kB + * - MPU_16_KB Memory size in kB + * - MPU_32_KB Memory size in kB + * - MPU_64_KB Memory size in kB + * - MPU_128_KB Memory size in kB + * - MPU_256_KB Memory size in kB + * - MPU_512_KB Memory size in kB + * - MPU_1_MB Memory size in MB + * - MPU_2_MB Memory size in MB + * - MPU_4_MB Memory size in MB + * - MPU_8_MBv Memory size in MB + * - MPU_16_MB Memory size in MB + * - MPU_32_MB Memory size in MB + * - MPU_64_MB Memory size in MB + * - MPU_128_MB Memory size in MB + * - MPU_256_MB Memory size in MB + * - MPU_512_MB Memory size in MB + * - MPU_1_GB Memory size in GB + * - MPU_2_GB Memory size in GB + * - MPU_4_GB Memory size in GB + */ +enum mpuRegionSize +{ + MPU_32_BYTES = 0x04U << 1U, /**< Memory size in bytes */ + MPU_64_BYTES = 0x05U << 1U, /**< Memory size in bytes */ + MPU_128_BYTES = 0x06U << 1U, /**< Memory size in bytes */ + MPU_256_BYTES = 0x07U << 1U, /**< Memory size in bytes */ + MPU_512_BYTES = 0x08U << 1U, /**< Memory size in bytes */ + MPU_1_KB = 0x09U << 1U, /**< Memory size in kB */ + MPU_2_KB = 0x0AU << 1U, /**< Memory size in kB */ + MPU_4_KB = 0x0BU << 1U, /**< Memory size in kB */ + MPU_8_KB = 0x0CU << 1U, /**< Memory size in kB */ + MPU_16_KB = 0x0DU << 1U, /**< Memory size in kB */ + MPU_32_KB = 0x0EU << 1U, /**< Memory size in kB */ + MPU_64_KB = 0x0FU << 1U, /**< Memory size in kB */ + MPU_128_KB = 0x10U << 1U, /**< Memory size in kB */ + MPU_256_KB = 0x11U << 1U, /**< Memory size in kB */ + MPU_512_KB = 0x12U << 1U, /**< Memory size in kB */ + MPU_1_MB = 0x13U << 1U, /**< Memory size in MB */ + MPU_2_MB = 0x14U << 1U, /**< Memory size in MB */ + MPU_4_MB = 0x15U << 1U, /**< Memory size in MB */ + MPU_8_MB = 0x16U << 1U, /**< Memory size in MB */ + MPU_16_MB = 0x17U << 1U, /**< Memory size in MB */ + MPU_32_MB = 0x18U << 1U, /**< Memory size in MB */ + MPU_64_MB = 0x19U << 1U, /**< Memory size in MB */ + MPU_128_MB = 0x1AU << 1U, /**< Memory size in MB */ + MPU_256_MB = 0x1BU << 1U, /**< Memory size in MB */ + MPU_512_MB = 0x1CU << 1U, /**< Memory size in MB */ + MPU_1_GB = 0x1DU << 1U, /**< Memory size in GB */ + MPU_2_GB = 0x1EU << 1U, /**< Memory size in GB */ + MPU_4_GB = 0x1FU << 1U /**< Memory size in GB */ +}; + +/** @fn void _mpuInit_(void) + * @brief Initialize Mpu + * + * This function initializes memory protection unit. + */ +void _mpuInit_( void ); + +/** @fn void _mpuEnable_(void) + * @brief Enable Mpu + * + * This function enables memory protection unit. + */ +void _mpuEnable_( void ); + +/** @fn void _mpuDisable_(void) + * @brief Disable Mpu + * + * This function disables memory protection unit. + */ +void _mpuDisable_( void ); + +/** @fn void _mpuEnableBackgroundRegion_(void) + * @brief Enable Mpu background region + * + * This function enables background region of the memory protection unit. + */ +void _mpuEnableBackgroundRegion_( void ); + +/** @fn void _mpuDisableBackgroundRegion_(void) + * @brief Disable Mpu background region + * + * This function disables background region of the memory protection unit. + */ +void _mpuDisableBackgroundRegion_( void ); + +/** @fn uint32 _mpuGetNumberOfRegions_(void) + * @brief Returns number of implemented Mpu regions + * @return Number of implemented mpu regions + * + * This function returns the number of implemented mpu regions. + */ +uint32 _mpuGetNumberOfRegions_( void ); + +/** @fn uint32 _mpuAreRegionsSeparate_(void) + * @brief Returns the type of the implemented mpu regions + * @return Mpu type of regions + * + * This function returns 0 when mpu regions are of type unified otherwise regions are of + * type separate. + */ +uint32 _mpuAreRegionsSeparate_( void ); + +/** @fn void _mpuSetRegion_(uint32 region) + * @brief Set mpu region number + * @param[in] region Region number: mpuREGION1..mpuREGION12 + * + * This function selects one of the implemented mpu regions. + */ +void _mpuSetRegion_( uint32 region ); + +/** @fn uint32 _mpuGetRegion_(void) + * @brief Returns the currently selected mpu region + * @return Mpu region number + * + * This function returns currently selected mpu region number. + */ +uint32 _mpuGetRegion_( void ); + +/** @fn void _mpuSetRegionBaseAddress_(uint32 address) + * @brief Set base address of currently selected mpu region + * @param[in] address Base address of the MPU region + * @note The base address must always aligned with region size + * + * This function sets the base address of currently selected mpu region. + */ +void _mpuSetRegionBaseAddress_( uint32 address ); + +/** @fn uint32 _mpuGetRegionBaseAddress_(void) + * @brief Returns base address of currently selected mpu region + * @return Current base address of selected mpu region + * + * This function returns the base address of currently selected mpu region. + */ +uint32 _mpuGetRegionBaseAddress_( void ); + +/** @fn void _mpuSetRegionTypeAndPermission_(uint32 type, uint32 permission) + * @brief Set type of currently selected mpu region + * @param[in] type Region Type + * - MPU_STRONGLYORDERED_SHAREABLE : Memory type strongly ordered and + * sharable + * - MPU_DEVICE_SHAREABLE : Memory type device and sharable + * - MPU_NORMAL_OIWTNOWA_NONSHARED : Memory type normal outer and + * inner write-through, no write allocate and non shared + * - MPU_NORMAL_OIWBNOWA_NONSHARED : Memory type normal outer and + * inner write-back, no write allocate and non shared + * - MPU_NORMAL_OIWTNOWA_SHARED : Memory type normal outer and + * inner write-through, no write allocate and shared + * - MPU_NORMAL_OIWBNOWA_SHARED : Memory type normal outer and + * inner write-back, no write allocate and shared + * - MPU_NORMAL_OINC_NONSHARED : Memory type normal outer and + * inner non-cacheable and non shared + * - MPU_NORMAL_OIWBWA_NONSHARED : Memory type normal outer and + * inner write-back, write allocate and non shared + * - MPU_NORMAL_OINC_SHARED : Memory type normal outer and + * inner non-cacheable and shared + * - MPU_NORMAL_OIWBWA_SHARED : Memory type normal outer and + * inner write-back, write allocate and shared + * - MPU_DEVICE_NONSHAREABLE : Memory type device and non + * sharable + * + * @param[in] permission Region Access permission + * - MPU_PRIV_NA_USER_NA_EXEC : Alias no access in privileged + * mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_NA_EXEC : Alias no read/write in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RW_USER_RO_EXEC : Alias no read/write in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_RW_USER_RW_EXEC : Alias no read/write in + * privileged mode, read/write in user mode and execute + * - MPU_PRIV_RO_USER_NA_EXEC : Alias no read only in + * privileged mode, no access in user mode and execute + * - MPU_PRIV_RO_USER_RO_EXEC : Alias no read only in + * privileged mode, read only in user mode and execute + * - MPU_PRIV_NA_USER_NA_NOEXEC : Alias no access in privileged + * mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_NA_NOEXEC : Alias no read/write in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RW_USER_RO_NOEXEC : Alias no read/write in + * privileged mode, read only in user mode and no execution + * - MPU_PRIV_RW_USER_RW_NOEXEC : Alias no read/write in + * privileged mode, read/write in user mode and no execution + * - MPU_PRIV_RO_USER_NA_NOEXEC : Alias no read only in + * privileged mode, no access in user mode and no execution + * - MPU_PRIV_RO_USER_RO_NOEXEC : Alias no read only in + * privileged mode, read only in user mode and no execution + * + * This function sets the type of currently selected mpu region. + */ +void _mpuSetRegionTypeAndPermission_( uint32 type, uint32 permission ); + +/** @fn uint32 _mpuGetRegionType_(void) + * @brief Returns the type of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns the type of currently selected mpu region. + */ +uint32 _mpuGetRegionType_( void ); + +/** @fn uint32 _mpuGetRegionPermission_(void) + * @brief Returns permission of currently selected mpu region + * @return Current type of selected mpu region + * + * This function returns permission of currently selected mpu region. + */ +uint32 _mpuGetRegionPermission_( void ); + +/** @fn void _mpuSetRegionSizeRegister_(uint32 value) + * @brief Set mpu region size register value + * @param[in] value Value to be written in the MPU Region Size and Enable register + * + * This function sets mpu region size register value. + * + * Sample usuage: + * _mpuSetRegion_(mpuREGION5); + * _mpuSetRegionSizeRegister_(mpuREGION_ENABLE | MPU_16_KB | mpuSUBREGION3_DISABLE | + * mpuSUBREGION4_DISABLE); + */ +void _mpuSetRegionSizeRegister_( uint32 value ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h new file mode 100644 index 00000000000..b8dc1fb4feb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pcr.h @@ -0,0 +1,331 @@ +/** @file pcr.h + * @brief PCR Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * - Interface Prototypes + * . + * which are relevant for the PCR driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef PCR_H_ +#define PCR_H_ + +#include "reg_pcr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#define QUADRANT0 1U +#define QUADRANT1 2U +#define QUADRANT2 4U +#define QUADRANT3 8U + +typedef enum +{ + PS0 = 0U, + PS1, + PS2, + PS3, + PS4, + PS5, + PS6, + PS7, + PS8, + PS9, + PS10, + PS11, + PS12, + PS13, + PS14, + PS15, + PS16, + PS17, + PS18, + PS19, + PS20, + PS21, + PS22, + PS23, + PS24, + PS25, + PS26, + PS27, + PS28, + PS29, + PS30, + PS31 +} peripheral_Frame_t; + +typedef enum +{ + PPS0 = 0U, + PPS1, + PPS2, + PPS3, + PPS4, + PPS5, + PPS6, + PPS7 +} privileged_Peripheral_Frame_t; + +typedef enum +{ + PPSE0 = 0U, + PPSE1, + PPSE2, + PPSE3, + PPSE4, + PPSE5, + PPSE6, + PPSE7, + PPSE8, + PPSE9, + PPSE10, + PPSE11, + PPSE12, + PPSE13, + PPSE14, + PPSE15, + PPSE16, + PPSE17, + PPSE18, + PPSE19, + PPSE20, + PPSE21, + PPSE22, + PPSE23, + PPSE24, + PPSE25, + PPSE26, + PPSE27, + PPSE28, + PPSE29, + PPSE30, + PPSE31 +} privileged_Peripheral_Extended_Frame_t; + +typedef enum +{ + PCS0 = 0U, + PCS1, + PCS2, + PCS3, + PCS4, + PCS5, + PCS6, + PCS7, + PCS8, + PCS9, + PCS10, + PCS11, + PCS12, + PCS13, + PCS14, + PCS15, + PCS16, + PCS17, + PCS18, + PCS19, + PCS20, + PCS21, + PCS22, + PCS23, + PCS24, + PCS25, + PCS26, + PCS27, + PCS28, + PCS29, + PCS30, + PCS31, + PCS32, + PCS33, + PCS34, + PCS35, + PCS36, + PCS37, + PCS38, + PCS39, + PCS40, + PCS41, + PCS42, + PCS43, + PCS44, + PCS45, + PCS46, + PCS47, + PCS48, + PCS49, + PCS50, + PCS51, + PCS52, + PCS53, + PCS54, + PCS55, + PCS56, + PCS57, + PCS58, + PCS59, + PCS60, + PCS61, + PCS62, + PCS63 +} peripheral_Memory_t; + +typedef enum +{ + PPCS0 = 0U, + PPCS1, + PPCS2, + PPCS3, + PPCS4, + PPCS5, + PPCS6, + PPCS7, + PPCS8, + PPCS9, + PPCS10, + PPCS11, + PPCS12, + PPCS13, + PPCS14, + PPCS15 +} privileged_Peripheral_Memory_t; + +typedef enum +{ + Master_CPU0 = 0U, + Master_CPU1 = 1U, /* Reserved for Lock-Step device */ + Master_DMA = 2U, + Master_HTU1 = 3U, + Master_HTU2 = 4U, + Master_FTU = 5U, + Master_DMM = 7U, + Master_DAP = 9U, + Master_EMAC = 10U +} master_ID_t; + +/** + * @defgroup PCR PCR + * @brief PPeripheral Central Resource Module + * + * Related files: + * - reg_pcr.h + * - sys_pcr.h + * - sys_pcr.c + * + * @addtogroup PCR + * @{ + */ + +void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Frame_Protection_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); +void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); + +void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ); +void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); +void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ); + +void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ); +void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ); +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ); + +void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ); +void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ); +void privileged_Peripheral_Memory_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ); +void privileged_Peripheral_Memory_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ); + +void pcrEnableMasterIDCheck( pcrBASE_t * pcr ); +void pcrDisableMasterIDCheck( pcrBASE_t * pcr ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#endif /* PCR_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h new file mode 100644 index 00000000000..0365d796e13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmm.h @@ -0,0 +1,119 @@ +/** @file sys_pmm.h + * @brief PMM Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMM_H__ +#define __SYS_PMM_H__ + +#include "reg_pmm.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @enum pmmLogicPDTag + * @brief PMM Logic Power Domain + * + * Used to define PMM Logic Power Domain + */ +typedef enum pmmLogicPDTag +{ + PMM_LOGICPD1 = 5U, /*-- NOT USED*/ + PMM_LOGICPD2 = 0U, + PMM_LOGICPD3 = 1U, + PMM_LOGICPD4 = 2U, + PMM_LOGICPD5 = 3U, + PMM_LOGICPD6 = 4U +} pmm_LogicPD_t; + +/** @enum pmmModeTag + * @brief PSCON operating mode + * + * Used to define the operating mode of PSCON Compare Block + */ +typedef enum pmmModeTag +{ + LockStep = 0x0U, + SelfTest = 0x6U, + ErrorForcing = 0x9U, + SelfTestErrorForcing = 0xFU +} pmm_Mode_t; + +/** + * @defgroup PMM PMM + * @brief Power Management Module + * + * The PMM provides memory-mapped registers that control the states of the supported power + * domains. The PMM includes interfaces to the Power Mode Controller (PMC) and the Power + * State Controller (PSCON). The PMC and PSCON control the power up/down sequence of each + * power domain. + * + * Related files: + * - reg_pmm.h + * - sys_pmm.h + * - sys_pmm.c + * + * @addtogroup PMM + * @{ + */ + +/* Pmm Interface Functions */ +boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ); +boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ); +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ); + +/**@}*/ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h new file mode 100644 index 00000000000..f60d1f47c55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_pmu.h @@ -0,0 +1,240 @@ +/** @file sys_pmu.h + * @brief System Pmu Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Pmu Interface Functions + * . + * which are relevant for the performance monitor unit driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_PMU_H__ +#define __SYS_PMU_H__ + +#include "sys_common.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @def pmuCOUNTER0 + * @brief pmu event counter 0 + * + * Alias for pmu event counter 0 + */ +#define pmuCOUNTER0 0x00000001U + +/** @def pmuCOUNTER1 + * @brief pmu event counter 1 + * + * Alias for pmu event counter 1 + */ +#define pmuCOUNTER1 0x00000002U + +/** @def pmuCOUNTER2 + * @brief pmu event counter 2 + * + * Alias for pmu event counter 2 + */ +#define pmuCOUNTER2 0x00000004U + +/** @def pmuCYCLE_COUNTER + * @brief pmu cycle counter + * + * Alias for pmu event counter + */ +#define pmuCYCLE_COUNTER 0x80000000U + +/** @enum pmuEvent + * @brief pmu event + * + * Alias for pmu event counter increment source + */ +enum pmuEvent +{ + PMU_INST_CACHE_MISS = 0x01U, + PMU_DATA_CACHE_MISS = 0x03U, + PMU_DATA_CACHE_ACCESS = 0x04U, + PMU_DATA_READ_ARCH_EXECUTED = 0x06U, + PMU_DATA_WRITE_ARCH_EXECUTED = 0x07U, + PMU_INST_ARCH_EXECUTED = 0x08U, + PMU_EXCEPTION_TAKEN = 0x09U, + PMU_EXCEPTION_RETURN_ARCH_EXECUTED = 0x0AU, + PMU_CHANGE_TO_CONTEXT_ID_EXECUTED = 0x0BU, + PMU_SW_CHANGE_OF_PC_ARCH_EXECUTED = 0x0CU, + PMU_BRANCH_IMM_INST_ARCH_EXECUTED = 0x0DU, + PMU_PROC_RETURN_ARCH_EXECUTED = 0x0EU, + PMU_UNALIGNED_ACCESS_ARCH_EXECUTED = 0x0FU, + PMU_BRANCH_MISSPREDICTED = 0x10U, + PMU_CYCLE_COUNT = 0x11U, + PMU_PREDICTABLE_BRANCHES = 0x12U, + PMU_INST_BUFFER_STALL = 0x40U, + PMU_DATA_DEPENDENCY_INST_STALL = 0x41U, + PMU_DATA_CACHE_WRITE_BACK = 0x42U, + PMU_EXT_MEMORY_REQUEST = 0x43U, + PMU_LSU_BUSY_STALL = 0x44U, + PMU_FORCED_DRAIN_OFSTORE_BUFFER = 0x45U, + PMU_FIQ_DISABLED_CYCLE_COUNT = 0x46U, + PMU_IRQ_DISABLED_CYCLE_COUNT = 0x47U, + PMU_ETMEXTOUT_0 = 0x48U, + PMU_ETMEXTOUT_1 = 0x49U, + PMU_INST_CACHE_TAG_ECC_ERROR = 0x4AU, + PMU_INST_CACHE_DATA_ECC_ERROR = 0x4BU, + PMU_DATA_CACHE_TAG_ECC_ERROR = 0x4CU, + PMU_DATA_CACHE_DATA_ECC_ERROR = 0x4DU, + PMU_TCM_FATAL_ECC_ERROR_PREFETCH = 0x4EU, + PMU_TCM_FATAL_ECC_ERROR_LOAD_STORE = 0x4FU, + PMU_STORE_BUFFER_MERGE = 0x50U, + PMU_LSU_STALL_STORE_BUFFER_FULL = 0x51U, + PMU_LSU_STALL_STORE_QUEUE_FULL = 0x52U, + PMU_INTEGER_DIV_EXECUTED = 0x53U, + PMU_STALL_INTEGER_DIV = 0x54U, + PMU_PLD_INST_LINE_FILL = 0x55U, + PMU_PLD_INST_NO_LINE_FILL = 0x56U, + PMU_NON_CACHEABLE_ACCESS_AXI_MASTER = 0x57U, + PMU_INST_CACHE_ACCESS = 0x58U, + PMU_DOUBLE_DATA_CACHE_ISSUE = 0x59U, + PMU_DUAL_ISSUE_CASE_A = 0x5AU, + PMU_DUAL_ISSUE_CASE_B1_B2_F2_F2D = 0x5BU, + PMU_DUAL_ISSUE_OTHER = 0x5CU, + PMU_DP_FLOAT_INST_EXCECUTED = 0x5DU, + PMU_DUAL_ISSUED_PAIR_INST_ARCH_EXECUTED = 0x5EU, + PMU_DATA_CACHE_DATA_FATAL_ECC_ERROR = 0x60U, + PMU_DATA_CACHE_TAG_FATAL_ECC_ERROR = 0x61U, + PMU_PROCESSOR_LIVE_LOCK = 0x62U, + PMU_ATCM_MULTI_BIT_ECC_ERROR = 0x64U, + PMU_B0TCM_MULTI_BIT_ECC_ERROR = 0x65U, + PMU_B1TCM_MULTI_BIT_ECC_ERROR = 0x66U, + PMU_ATCM_SINGLE_BIT_ECC_ERROR = 0x67U, + PMU_B0TCM_SINGLE_BIT_ECC_ERROR = 0x68U, + PMU_B1TCM_SINGLE_BIT_ECC_ERROR = 0x69U, + PMU_TCM_COR_ECC_ERROR_LOAD_STORE = 0x6AU, + PMU_TCM_COR_ECC_ERROR_PREFETCH = 0x6BU, + PMU_TCM_FATAL_ECC_ERROR_AXI_SLAVE = 0x6CU, + PMU_TCM_COR_ECC_ERROR_AXI_SLAVE = 0x6DU, + PMU_ALL_CORRECTABLE_EVENTS = 0x6EU, + PMU_ALL_FATAL_EVENTS = 0x6FU, + PMU_ALL_CORRECTABLE_FAULTS = 0x70U, + PMU_ALL_FATAL_FAULTS = 0x71U, + PMU_ACP_DCACHE_ACCESS_LOOKUP_INVALIDATE = 0x72U, + PMU_ACP_DCACHE_INVALIDATE = 0x73U +}; + +/** @fn void _pmuInit_(void) + * @brief Initialize Performance Monitor Unit + */ +void _pmuInit_( void ); + +/** @fn void _pmuEnableCountersGlobal_(void) + * @brief Enable and reset cycle counter and all 3 event counters + */ +void _pmuEnableCountersGlobal_( void ); + +/** @fn void _pmuDisableCountersGlobal_(void) + * @brief Disable cycle counter and all 3 event counters + */ +void _pmuDisableCountersGlobal_( void ); + +/** @fn void _pmuResetCycleCounter_(void) + * @brief Reset cycle counter + */ +void _pmuResetCycleCounter_( void ); + +/** @fn void _pmuResetEventCounters_(void) + * @brief Reset event counters 0-2 + */ +void _pmuResetEventCounters_( void ); + +/** @fn void _pmuResetCounters_(void) + * @brief Reset cycle counter and event counters 0-2 + */ +void _pmuResetCounters_( void ); + +/** @fn void _pmuStartCounters_(uint32 counters) + * @brief Starts selected counters + * @param[in] counters - Counter mask + */ +void _pmuStartCounters_( uint32 counters ); + +/** @fn void _pmuStopCounters_(uint32 counters) + * @brief Stops selected counters + * @param[in] counters - Counter mask + */ +void _pmuStopCounters_( uint32 counters ); + +/** @fn void _pmuSetCountEvent_(uint32 counter, uint32 event) + * @brief Set event counter count event + * @param[in] counter - Counter select 0..2 + * @param[in] event - Count event + */ +void _pmuSetCountEvent_( uint32 counter, uint32 event ); + +/** @fn uint32 _pmuGetCycleCount_(void) + * @brief Returns current cycle counter value + * + * @return cycle count. + */ +uint32 _pmuGetCycleCount_( void ); + +/** @fn uint32 _pmuGetEventCount_(uint32 counter) + * @brief Returns current event counter value + * @param[in] counter - Counter select 0..2 + * + * @return event counter count. + */ +uint32 _pmuGetEventCount_( uint32 counter ); + +/** @fn uint32 _pmuGetOverflow_(void) + * @brief Returns current overflow register and clear flags + * + * @return overflow flags. + */ +uint32 _pmuGetOverflow_( void ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h new file mode 100644 index 00000000000..3d989cf9acb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/sys_vim.h @@ -0,0 +1,386 @@ +/** @file sys_vim.h + * @brief Vectored Interrupt Module Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - VIM Type Definitions + * - VIM General Definitions + * . + * which are relevant for Vectored Interrupt Controller. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_VIM_H__ +#define __SYS_VIM_H__ + +#include "reg_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* VIM Type Definitions */ + +/** @typedef t_isrFuncPTR + * @brief ISR Function Pointer Type Definition + * + * This type is used to access the ISR handler. + */ +typedef void ( *t_isrFuncPTR )( void ); + +/** @enum systemInterrupt + * @brief Alias names for clock sources + * + * This enumeration is used to provide alias names for the clock sources: + * - IRQ + * - FIQ + */ +typedef enum systemInterrupt +{ + SYS_IRQ = 0U, /**< Alias for IRQ interrupt */ + SYS_FIQ = 1U /**< Alias for FIQ interrupt */ +} systemInterrupt_t; + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* VIM General Configuration */ + +#define VIM_CHANNELS 128U + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* Interrupt Handlers */ +extern void custom_dabort( void ); +extern void esmHighInterrupt( void ) __attribute__( ( weak, interrupt( "FIQ" ) ) ); +extern void phantomInterrupt( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void FreeRTOS_Tick_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void vPortYieldWithinAPI( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); +extern void FreeRTOS_IRQ_Handler( void ) __attribute__( ( weak, interrupt( "IRQ" ) ) ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +#define VIM_ECCSTAT ( *( volatile uint32 * ) 0xFFFFFDECU ) +#define VIM_ECCCTL ( *( volatile uint32 * ) 0xFFFFFDF0U ) +#define VIM_UERRADDR ( *( volatile uint32 * ) 0xFFFFFDF4U ) +#define VIM_FBVECADDR ( *( volatile uint32 * ) 0xFFFFFDF8U ) +#define VIM_SBERRADDR ( *( volatile uint32 * ) 0xFFFFFDFCU ) + +#define VIMRAMECCLOC ( *( volatile uint32 * ) 0xFFF82400U ) +#define VIMRAMLOC ( *( volatile uint32 * ) 0xFFF82000U ) + +/* Configuration registers */ +typedef struct vim_config_reg +{ + uint32 CONFIG_FIRQPR0; + uint32 CONFIG_FIRQPR1; + uint32 CONFIG_FIRQPR2; + uint32 CONFIG_FIRQPR3; + uint32 CONFIG_REQMASKSET0; + uint32 CONFIG_REQMASKSET1; + uint32 CONFIG_REQMASKSET2; + uint32 CONFIG_REQMASKSET3; + uint32 CONFIG_WAKEMASKSET0; + uint32 CONFIG_WAKEMASKSET1; + uint32 CONFIG_WAKEMASKSET2; + uint32 CONFIG_WAKEMASKSET3; + uint32 CONFIG_CAPEVT; + uint32 CONFIG_CHANCTRL[ 24U ]; +} vim_config_reg_t; + +/* Configuration registers initial value */ +#define VIM_FIRQPR0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_FIRQPR3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) \ + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ) ) + +#define VIM_REQMASKSET0_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 0U ) | ( uint32 ) ( ( uint32 ) 1U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 1U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET2_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_REQMASKSET3_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 1U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) | ( uint32 ) ( ( uint32 ) 0U << 3U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 0U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( uint32 ) 0U << 7U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) | ( uint32 ) ( ( uint32 ) 0U << 13U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) | ( uint32 ) ( ( uint32 ) 0U << 15U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) | ( uint32 ) ( ( uint32 ) 0U << 17U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) | ( uint32 ) ( ( uint32 ) 0U << 19U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) | ( uint32 ) ( ( uint32 ) 0U << 21U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 25U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) | ( uint32 ) ( ( uint32 ) 0U << 27U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 28U ) | ( uint32 ) ( ( uint32 ) 0U << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 30U ) | ( uint32 ) ( ( uint32 ) 0U << 31U ) ) + +#define VIM_WAKEMASKSET0_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET1_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET2_CONFIGVALUE 0xFFFFFFFFU +#define VIM_WAKEMASKSET3_CONFIGVALUE 0xFFFFFFFFU +#define VIM_CAPEVT_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 0U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) ) + +#define VIM_CHANCTRL0_CONFIGVALUE 0x00010203U +#define VIM_CHANCTRL1_CONFIGVALUE 0x04050607U +#define VIM_CHANCTRL2_CONFIGVALUE 0x08090A0BU +#define VIM_CHANCTRL3_CONFIGVALUE 0x0C0D0E0FU +#define VIM_CHANCTRL4_CONFIGVALUE 0x10111213U +#define VIM_CHANCTRL5_CONFIGVALUE 0x14151617U +#define VIM_CHANCTRL6_CONFIGVALUE 0x18191A1BU +#define VIM_CHANCTRL7_CONFIGVALUE 0x1C1D1E1FU +#define VIM_CHANCTRL8_CONFIGVALUE 0x20212223U +#define VIM_CHANCTRL9_CONFIGVALUE 0x24252627U +#define VIM_CHANCTRL10_CONFIGVALUE 0x28292A2BU +#define VIM_CHANCTRL11_CONFIGVALUE 0x2C2D2E2FU +#define VIM_CHANCTRL12_CONFIGVALUE 0x30313233U +#define VIM_CHANCTRL13_CONFIGVALUE 0x34353637U +#define VIM_CHANCTRL14_CONFIGVALUE 0x38393A3BU +#define VIM_CHANCTRL15_CONFIGVALUE 0x3C3D3E3FU +#define VIM_CHANCTRL16_CONFIGVALUE 0x40414243U +#define VIM_CHANCTRL17_CONFIGVALUE 0x44454647U +#define VIM_CHANCTRL18_CONFIGVALUE 0x48494A4BU +#define VIM_CHANCTRL19_CONFIGVALUE 0x4C4D4E4FU +#define VIM_CHANCTRL20_CONFIGVALUE 0x50515253U +#define VIM_CHANCTRL21_CONFIGVALUE 0x54555657U +#define VIM_CHANCTRL22_CONFIGVALUE 0x58595A5BU +#define VIM_CHANCTRL23_CONFIGVALUE 0x5C5D5E5FU + +/** + * @defgroup VIM VIM + * @brief Vectored Interrupt Manager + * + * The vectored interrupt manager (VIM) provides hardware assistance for prioritizing and + * controlling the many interrupt sources present on a device. Interrupts are caused by + * events outside of the normal flow of program execution. + * + * Related files: + * - reg_vim.h + * - sys_vim.h + * - sys_vim.c + * + * @addtogroup VIM + * @{ + */ +/*VIM Interface functions*/ +void vimInit( void ); +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ); +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ); +void vimDisableInterrupt( uint32 channel ); +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ); +/*@}*/ +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h new file mode 100644 index 00000000000..a80f461245f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/system.h @@ -0,0 +1,477 @@ +/** @file system.h + * @brief System Driver Header File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Definitions + * - Types + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef __SYS_SYSTEM_H__ +#define __SYS_SYSTEM_H__ + +#include "reg_system.h" +#include "reg_flash.h" +#include "reg_l2ramw.h" +#include "reg_ccmr5.h" +#include "sys_core.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* System General Definitions */ + +/** @enum systemClockSource + * @brief Alias names for clock sources + * + * This enumeration is used to provide alias names for the clock sources: + * - Oscillator + * - Pll1 + * - External1 + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - PLL2 + * - External2 + * - Synchronous VCLK1 + */ +enum systemClockSource +{ + SYS_OSC = 0x0U, /**< Alias for oscillator clock Source */ + SYS_PLL1 = 0x1U, /**< Alias for Pll1 clock Source */ + SYS_EXTERNAL1 = 0x3U, /**< Alias for external clock Source */ + SYS_LPO_LOW = 0x4U, /**< Alias for low power oscillator low clock Source */ + SYS_LPO_HIGH = 0x5U, /**< Alias for low power oscillator high clock Source */ + SYS_PLL2 = 0x6U, /**< Alias for Pll2 clock Source */ + SYS_EXTERNAL2 = 0x7U, /**< Alias for external 2 clock Source */ + SYS_VCLK = 0x9U, /**< Alias for synchronous VCLK1 clock Source */ + SYS_PLL2_ODCLK_8 = 0xEU, /**< Alias for PLL2_post_ODCLK/8 */ + SYS_PLL2_ODCLK_16 = 0xFU /**< Alias for PLL2_post_ODCLK/8 */ +}; + +/** @enum resetSource + * @brief Alias names for reset sources + * + * This enumeration is used to provide alias names for the reset sources: + * - Power On Reset + * - Osc Failure Reset + * - Watch Dog Reset + * - Icepick Reset + * - CPU Reset + * - Software Reset + * - External Reset + * + */ +typedef enum +{ + POWERON_RESET = 0x8000U, /**< Alias for Power On Reset */ + OSC_FAILURE_RESET = 0x4000U, /**< Alias for Osc Failure Reset */ + WATCHDOG_RESET = 0x2000U, /**< Alias for Watch Dog Reset */ + WATCHDOG2_RESET = 0x1000U, /**< Alias for Watch Dog 2 Reset */ + DEBUG_RESET = 0x0800U, /**< Alias for Debug Reset */ + INTERCONNECT_RESET = 0x0080U, /**< Alias for Interconnect Reset */ + CPU0_RESET = 0x0020U, /**< Alias for CPU 0 Reset */ + SW_RESET = 0x0010U, /**< Alias for Software Reset */ + EXT_RESET = 0x0008U, /**< Alias for External Reset */ + NO_RESET = 0x0000U /**< Alias for No Reset */ +} resetSource_t; + +#define SYS_DOZE_MODE 0x000F3F02U +#define SYS_SNOOZE_MODE 0x000F3F03U +#define SYS_SLEEP_MODE 0x000FFFFFU +#define LPO_TRIM_VALUE ( ( ( *( volatile uint32 * ) 0xF00801B4U ) & 0xFFFF0000U ) >> 16U ) +#define SYS_EXCEPTION ( *( volatile uint32 * ) 0xFFFFFFE4U ) + +#define WATCHDOG_STATUS ( *( volatile uint32 * ) 0xFFFFFC98U ) +#define DEVICE_ID_REV ( *( volatile uint32 * ) 0xFFFFFFF0U ) + +/** @def OSC_FREQ + * @brief Oscillator clock source exported from HALCoGen GUI + * + * Oscillator clock source exported from HALCoGen GUI + */ +#define OSC_FREQ 16.0F + +/** @def PLL1_FREQ + * @brief PLL 1 clock source exported from HALCoGen GUI + * + * PLL 1 clock source exported from HALCoGen GUI + */ +#define PLL1_FREQ 300.00F + +/** @def LPO_LF_FREQ + * @brief LPO Low Freq Oscillator source exported from HALCoGen GUI + * + * LPO Low Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_LF_FREQ 0.080F + +/** @def LPO_HF_FREQ + * @brief LPO High Freq Oscillator source exported from HALCoGen GUI + * + * LPO High Freq Oscillator source exported from HALCoGen GUI + */ +#define LPO_HF_FREQ 10.000F + +/** @def PLL1_FREQ + * @brief PLL 2 clock source exported from HALCoGen GUI + * + * PLL 2 clock source exported from HALCoGen GUI + */ +#define PLL2_FREQ 300.00F + +/** @def GCLK_FREQ + * @brief GCLK domain frequency exported from HALCoGen GUI + * + * GCLK domain frequency exported from HALCoGen GUI + */ +#define GCLK_FREQ 300.000F + +/** @def HCLK_FREQ + * @brief HCLK domain frequency exported from HALCoGen GUI + * + * HCLK domain frequency exported from HALCoGen GUI + */ +#define HCLK_FREQ 150.000F + +/** @def RTI_FREQ + * @brief RTI Clock frequency exported from HALCoGen GUI + * + * RTI Clock frequency exported from HALCoGen GUI + */ +#define RTI_FREQ 75.000F + +/** @def AVCLK1_FREQ + * @brief AVCLK1 Domain frequency exported from HALCoGen GUI + * + * AVCLK Domain frequency exported from HALCoGen GUI + */ +#define AVCLK1_FREQ 75.000F + +/** @def AVCLK2_FREQ + * @brief AVCLK2 Domain frequency exported from HALCoGen GUI + * + * AVCLK2 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK2_FREQ 0.000F + +/** @def AVCLK3_FREQ + * @brief AVCLK3 Domain frequency exported from HALCoGen GUI + * + * AVCLK3 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK3_FREQ 75.000F + +/** @def AVCLK4_FREQ + * @brief AVCLK4 Domain frequency exported from HALCoGen GUI + * + * AVCLK4 Domain frequency exported from HALCoGen GUI + */ +#define AVCLK4_FREQ 75.000F + +/** @def VCLK1_FREQ + * @brief VCLK1 Domain frequency exported from HALCoGen GUI + * + * VCLK1 Domain frequency exported from HALCoGen GUI + */ +#define VCLK1_FREQ 75.000F + +/** @def VCLK2_FREQ + * @brief VCLK2 Domain frequency exported from HALCoGen GUI + * + * VCLK2 Domain frequency exported from HALCoGen GUI + */ +#define VCLK2_FREQ 75.000F + +/** @def VCLK3_FREQ + * @brief VCLK3 Domain frequency exported from HALCoGen GUI + * + * VCLK3 Domain frequency exported from HALCoGen GUI + */ +#define VCLK3_FREQ 75.000F + +/** @def VCLK4_FREQ + * @brief VCLK4 Domain frequency exported from HALCoGen GUI + * + * VCLK4 Domain frequency exported from HALCoGen GUI + */ +#define VCLK4_FREQ 75.0F + +/** @def SYS_PRE1 + * @brief Alias name for RTI1CLK PRE clock source + * + * This is an alias name for the RTI1CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 "Macro filled using GUI parameter cannot be avoided" + */ +#define SYS_PRE1 ( SYS_PLL1 ) + +/** @def SYS_PRE2 + * @brief Alias name for RTI2CLK pre clock source + * + * This is an alias name for the RTI2CLK pre clock source. + * This can be either: + * - Oscillator + * - Pll + * - 32 kHz Oscillator + * - External + * - Low Power Oscillator Low + * - Low Power Oscillator High + * - Flexray Pll + */ +/*SAFETYMCUSW 79 S MR:19.4 "Macro filled using GUI parameter cannot be avoided" + */ +#define SYS_PRE2 ( SYS_PLL1 ) + +/* Configuration registers */ +typedef struct system_config_reg +{ + uint32 CONFIG_SYSPC1; + uint32 CONFIG_SYSPC2; + uint32 CONFIG_SYSPC7; + uint32 CONFIG_SYSPC8; + uint32 CONFIG_SYSPC9; + uint32 CONFIG_CSDIS; + uint32 CONFIG_CDDIS; + uint32 CONFIG_GHVSRC; + uint32 CONFIG_VCLKASRC; + uint32 CONFIG_RCLKSRC; + uint32 CONFIG_MSTGCR; + uint32 CONFIG_MINITGCR; + uint32 CONFIG_MSINENA; + uint32 CONFIG_PLLCTL1; + uint32 CONFIG_PLLCTL2; + uint32 CONFIG_SYSPC10; + uint32 CONFIG_LPOMONCTL; + uint32 CONFIG_CLKTEST; + uint32 CONFIG_DFTCTRLREG1; + uint32 CONFIG_DFTCTRLREG2; + uint32 CONFIG_GPREG1; + uint32 CONFIG_RAMGCR; + uint32 CONFIG_BMMCR1; + uint32 CONFIG_CLKCNTL; + uint32 CONFIG_ECPCNTL; + uint32 CONFIG_DEVCR1; + uint32 CONFIG_SYSECR; + uint32 CONFIG_PLLCTL3; + uint32 CONFIG_STCCLKDIV; + uint32 CONFIG_ECPCNTL1; + uint32 CONFIG_CLK2CNTRL; + uint32 CONFIG_VCLKACON1; + uint32 CONFIG_HCLKCNTL; + uint32 CONFIG_CLKSLIP; + uint32 CONFIG_EFC_CTLEN; +} system_config_reg_t; + +/* Configuration registers initial value */ +#define SYS_SYSPC1_CONFIGVALUE 0U + +#define SYS_SYSPC2_CONFIGVALUE 1U + +#define SYS_SYSPC7_CONFIGVALUE 0U + +#define SYS_SYSPC8_CONFIGVALUE 0U + +#define SYS_SYSPC9_CONFIGVALUE 1U + +#define SYS_CSDIS_CONFIGVALUE \ + ( 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U | 0x00000000U | 0x00000000U \ + | 0x00000000U | 0x4U ) + +#define SYS_CDDIS_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 4U ) | ( uint32 ) ( ( uint32 ) 1U << 5U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) ( ( uint32 ) 0U << 9U ) \ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) | ( uint32 ) ( ( uint32 ) 0U << 11U ) ) + +#define SYS_GHVSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) \ + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ) ) + +#define SYS_VCLKASRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_RCLKSRC_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) + +#define SYS_MSTGCR_CONFIGVALUE 0x00000105U + +#define SYS_MINITGCR_CONFIGVALUE 0x5U + +#define SYS_MSINENA_CONFIGVALUE 0U + +#define SYS_PLLCTL1_CONFIGVALUE_1 \ + ( ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) ) + +#define SYS_PLLCTL1_CONFIGVALUE_2 \ + ( ( ( SYS_PLLCTL1_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) + +#define SYS_PLLCTL2_CONFIGVALUE \ + ( ( uint32 ) 0x00000000U | ( uint32 ) ( ( uint32 ) 255U << 22U ) \ + | ( uint32 ) ( ( uint32 ) 7U << 12U ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U ) + +#define SYS_SYSPC10_CONFIGVALUE 0U + +#define SYS_LPOMONCTL_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | LPO_TRIM_VALUE ) +#define SYS_LPOMONCTL_CONFIGVALUE_2 \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 16U << 8U ) | 16U ) + +#define SYS_CLKTEST_CONFIGVALUE 0x000A0000U + +#define SYS_DFTCTRLREG1_CONFIGVALUE 0x00002205U + +#define SYS_DFTCTRLREG2_CONFIGVALUE 0x5U + +#define SYS_GPREG1_CONFIGVALUE 0x0005FFFFU + +#define SYS_RAMGCR_CONFIGVALUE 0x00050000U + +#define SYS_BMMCR1_CONFIGVALUE 0xAU + +#define SYS_CLKCNTL_CONFIGVALUE \ + ( 0x00000100U | ( uint32 ) ( ( uint32 ) 1U << 16U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) ) + +#define SYS_ECPCNTL_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 0U << 24U ) | ( uint32 ) ( ( uint32 ) 0U << 23U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ) ) + +#define SYS_DEVCR1_CONFIGVALUE 0xAU + +#define SYS_SYSECR_CONFIGVALUE 0x00004000U +#define SYS2_PLLCTL3_CONFIGVALUE_1 \ + ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) \ + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) \ + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) | ( uint32 ) ( 0x9500U ) ) + +#define SYS2_PLLCTL3_CONFIGVALUE_2 \ + ( ( ( SYS2_PLLCTL3_CONFIGVALUE_1 ) & 0xE0FFFFFFU ) \ + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) ) +#define SYS2_STCCLKDIV_CONFIGVALUE 0U +#define SYS2_ECPCNTL1_CONFIGVALUE 0x50000000U +#define SYS2_CLK2CNTRL_CONFIGVALUE ( 1U | 0x00000100U ) +#define SYS2_HCLKCNTL_CONFIGVALUE 1U +#define SYS2_VCLKACON1_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) 1U << 24U ) | ( uint32 ) ( ( uint32 ) 1U << 20U ) \ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) | ( uint32 ) ( ( uint32 ) 1U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ) ) +#define SYS2_CLKSLIP_CONFIGVALUE 0x5U +#define SYS2_EFC_CTLEN_CONFIGVALUE 0x5U + +#define L2FLASH_FBPWRMODE_CONFIGVALUE \ + ( ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) | ( uint32 ) ( ( uint32 ) 3U << 12U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 10U ) | ( uint32 ) ( ( uint32 ) 3U << 8U ) \ + | ( uint32 ) ( ( uint32 ) 3U << 6U ) | ( uint32 ) ( ( uint32 ) 3U << 4U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) \ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ) ) +#define L2FLASH_FRDCNTL_CONFIGVALUE ( ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U ) + +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ); + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* FlashW General Definitions */ + +/** @enum flashWPowerModes + * @brief Alias names for flash bank power modes + * + * This enumeration is used to provide alias names for the flash bank power modes: + * - sleep + * - standby + * - active + */ +enum flashWPowerModes +{ + SYS_SLEEP = 0U, /**< Alias for flash bank power mode sleep */ + SYS_STANDBY = 1U, /**< Alias for flash bank power mode standby */ + SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ +}; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +#define FSM_WR_ENA_HL ( *( volatile uint32 * ) 0xFFF87288U ) +#define EEPROM_CONFIG_HL ( *( volatile uint32 * ) 0xFFF872B8U ) +#define FSM_SECTOR1 ( *( volatile uint32 * ) 0xFFF872C0U ) +#define FSM_SECTOR2 ( *( volatile uint32 * ) 0xFFF872C4U ) +#define FCFG_BANK ( *( volatile uint32 * ) 0xFFF87400U ) + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/* System Interface Functions */ +void setupPLL( void ); +void trimLPO( void ); +void customTrimLPO( void ); +void setupFlash( void ); +void periphInit( void ); +void mapClocks( void ); +void systemInit( void ); +void systemPowerDown( uint32 mode ); +resetSource_t getResetSource( void ); + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +/**@}*/ +#ifdef __cplusplus +} +#endif /*extern "C" */ + +#endif diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h new file mode 100644 index 00000000000..d38f913546f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee.h @@ -0,0 +1,625 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * + ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.01 29Oct2012 Vishwanath Reddy 0000000000000 Changes for + implementing Error Recovery + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + segmentation changes. + * 00.01.03 14Jan2013 Vishwanath Reddy SDOCM00098510 Changes as requested + by Vector. + * 00.01.04 12Feb2012 Vishwanath Reddy SDOCM00099152 Integration issues + fix. + * 00.01.05 04Mar2013 Vishwanath Reddy SDOCM00099152 Added Deleting a + block feature, bug fixes. + * 00.01.06 11Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : + copying of unconfigured blocks. + * 00.01.07 15Mar2013 Vishwanath Reddy SDOCM00099152 Added feature : + Number of 8 bytes writes, fixed issue with copy blocks. + * 00.01.08 05Apr2013 Vishwanath Reddy SDOCM00099152 Added feature : CRC + check for unconfigured blocks, Main function modified to complete writes as fast as + possible, Added Non polling mode support. + * 00.01.09 19Apr2013 Vishwanath Reddy SDOCM00099152 Warning removal, + Added feature comparision of data during write. + * 00.01.10 11Jun2013 Vishwanath Reddy SDOCM00101845 Updated version + information. + * 00.01.11 05Jul2013 Vishwanath Reddy SDOCM00101643 Updated version + information. + * 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 Traceability tags + added. + * MISRA C fixes. + Version info corrected. + * 01.13.00 30Dec2013 Vishwanath Reddy 0000000000000 Undated version info + for SDOCM00107976 + * and SDOCM00105795. + * 01.13.01 19May2014 Vishwanath Reddy 0000000000000 Updated version info + for SDOCM00107913 + * and SDOCM00107622. + * 01.13.02 12Jun2014 Vishwanath Reddy 0000000000000 Updated version info + for SDOCM00108238 + * 01.14.00 26Mar2014 Vishwanath Reddy Update version info + for SDOCM00107161. + * 01.15.00 06Jun2014 Vishwanath Reddy Support for + Conqueror. + * 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove MISRA + warnings. + * 01.16.01 12Sep2014 Vishwanath Reddy SDOCM00112930 Prototype for + TI_Fee_SuspendResumeErase added. + * TI_Fee_EraseCommandType enum added. + * extern added for + TI_Fee_bEraseSuspended. + * 01.17.00 15Oct2014 Vishwanath Reddy SDOCM00113379 RAM Optimization + changes. + * 01.17.01 30Oct2014 Vishwanath Reddy SDOCM00113536 Support for + TMS570LS07xx,TMS570LS09xx, + * TMS570LS05xx, RM44Lx. + * 01.17.02 26Dec2014 Vishwanath Reddy SDOCM00114102 FLEE Errata Fix. + * SDOCM00114104 Change ALL 1's OK + check condition. + * Updated version info. + Added new macros. + * SDOCM00114423 Add new enum + TI_Fee_DeviceType. + * Add new variable + TI_Fee_MaxSectors and + * prototype + TI_FeeInternal_PopulateStructures. + * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version + history. + * Update ti_fee_util.c + file for the + * bugfix "If morethan + one data set is config- + * ured, then a valid + block may get invalidated if + * multiple valid blocks + are present in FEE memory. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + history. + * In + TI_FeeInternal_FeeManager, do not change the + * state to IDLE,after + completing the copy operation. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + history. + * Add a call of + TI_FeeInternal_PollFlashStatus() + * before reading data + from FEE bank in + * TI_FeeInternal_UpdateBlockOffsetArray(), + * TI_Fee_WriteAsync(),TI_Fee_WriteSync(), + * TI_Fee_ReadSync(), + TI_Fee_Read() + * 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update patch version + TI_FEE_SW_PATCH_VERSION. + * TI_FEE_FLASH_CRC_ENABLE is renamed to + * TI_FEE_FLASH_CHECKSUM_ENABLE. + * SDOCM00122429 In ti_fee_types.h, + add error when endianess + * is not defined. + * 01.19.00 08Augu2016 Vishwanath Reddy SDOCM00122592 Update patch version + TI_FEE_MINOR_VERSION. + * Code for using + partially ersed sector is now + * removed. + * Bugfix for FEE + reading from unimplemented memory + * space. + * 01.19.01 12Augu2016 Vishwanath Reddy SDOCM00122543 Update patch version + TI_FEE_MINOR_VERSION. + * Synchronous write API + modified to avoid copy of + * already copied block. + * 01.19.02 25Janu2017 Vishwanath Reddy SDOCM00122832 Update patch version + TI_FEE_MINOR_VERSION. + * Format API modified + to erase all configured VS. + * SDOCM00122833 In API + TI_Fee_ErrorRecovery, added polling for + * flash status before + calling TI_Fee_Init. + * 01.19.03 15May2017 Prathap Srinivasan SDOCM00122917 Added + TI_Fee_bIsMainFunctionCalled Global Variable. + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_H + #define TI_FEE_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "hal_stdtypes.h" + #include "fee_interface.h" + #include "ti_fee_types.h" + #include "ti_fee_cfg.h" + /********************************************************************************************************************** + * GLOBAL CONSTANT MACROS + *********************************************************************************************************************/ + /* Fee Published Information */ + #define TI_FEE_MAJOR_VERSION 3U + #define TI_FEE_MINOR_VERSION 0U + #define TI_FEE_PATCH_VERSION 2U + #define TI_FEE_SW_MAJOR_VERSION 1U + #define TI_FEE_SW_MINOR_VERSION 19U + #define TI_FEE_SW_PATCH_VERSION 4U + + #define TI_FEE_VIRTUAL_SECTOR_VERSION 1U + + /* Virtual sector states */ + #define ActiveVSHi 0x0000FFFFU + #define ActiveVSLo 0x00000000U + #define CopyVSHi 0xFFFFFFFFU + #define CopyVSLo 0x00000000U + #define EmptyVSHi 0xFFFFFFFFU + #define EmptyVSLo 0x0000FFFFU + #define InvalidVSHi 0xFFFFFFFFU + #define InvalidVSLo 0xFFFFFFFFU + #define ReadyforEraseVSHi 0x00000000U + #define ReadyforEraseVSLo 0x00000000U + + /* Data Block states*/ + #define EmptyBlockHi 0xFFFFFFFFU + #define EmptyBlockLo 0xFFFFFFFFU + #define StartProgramBlockHi 0xFFFF0000U + #define StartProgramBlockLo 0xFFFFFFFFU + #define ValidBlockHi 0x00000000U + #define ValidBlockLo 0xFFFFFFFFU + #define InvalidBlockHi 0x00000000U + #define InvalidBlockLo 0xFFFF0000U + #define CorruptBlockHi 0x00000000U + #define CorruptBlockLo 0x00000000U + + #define FEE_BANK 0U + + /* Enable/Disable FEE sectors */ + #define FEE_DISABLE_SECTORS_31_00 0x00000000U + #define FEE_DISABLE_SECTORS_63_32 0x00000000U + #define FEE_ENABLE_SECTORS_31_00 0xFFFFFFFFU + #define FEE_ENABLE_SECTORS_63_32 0xFFFFFFFFU + +/********************************************************************************************************************** + * GLOBAL DATA TYPES AND STRUCTURES + *********************************************************************************************************************/ +/* Structures used */ +/* Enum to describe the Fee Status types */ +typedef enum +{ + TI_FEE_OK = 0U, /* Function returned no error */ + TI_FEE_ERROR = 1U /* Function returned an error */ +} TI_Fee_StatusType; + +/* Enum to describe the Virtual Sector State */ +typedef enum +{ + VsState_Invalid = 1U, + VsState_Empty = 2U, + VsState_Copy = 3U, + VsState_Active = 4U, + VsState_ReadyForErase = 5U +} VirtualSectorStatesType; + +/* Enum to describe the Block State */ +typedef enum +{ + Block_StartProg = 1U, + Block_Valid = 2U, + Block_Invalid = 3U +} BlockStatesType; + +/* Enum for error trpes */ +typedef enum +{ + Error_Nil = 0U, + Error_TwoActiveVS = 1U, + Error_TwoCopyVS = 2U, + Error_SetupStateMachine = 3U, + Error_CopyButNoActiveVS = 4U, + Error_NoActiveVS = 5U, + Error_BlockInvalid = 6U, + Error_NullDataPtr = 7U, + Error_NoFreeVS = 8U, + Error_InvalidVirtualSectorParameter = 9U, + Error_ExceedSectorOnBank = 10U, + Error_EraseVS = 11U, + Error_BlockOffsetGtBlockSize = 12U, + Error_LengthParam = 13U, + Error_FeeUninit = 14U, + Error_Suspend = 15U, + Error_InvalidBlockIndex = 16U, + Error_NoErase = 17U, + Error_CurrentAddress = 18U, + Error_Exceed_No_Of_DataSets = 19U +} TI_Fee_ErrorCodeType; + +typedef enum +{ + Suspend_Erase = 0U, + Resume_Erase +} TI_Fee_EraseCommandType; + +/* Enum to describe the Device types */ +typedef enum +{ + CHAMPION = 0U, /* Function returned no error */ + ARCHER = 1U /* Function returned an error */ +} TI_Fee_DeviceType; + +typedef uint32 TI_Fee_AddressType; /* Used for defining variables to indicate number of + bytes for address offset */ +typedef uint32 TI_Fee_LengthType; /* Used for defining variables to indicate number of + bytes per read/write/erase */ +typedef TI_Fee_ErrorCodeType Fee_ErrorCodeType; + +/* Structure used when defining virtual sectors */ +/* The following error checks need to be performed: */ +/* Virtual Sector definitions are not allowed to overlap */ +/* Virtual Sector definition is at least twice the size in bytes of the total size of all + * defined blocks */ +/* We will need to define a formula to indicate if the number of write cycles indicated in + * the block definitions */ +/* is possible in the defined Virtual Sector. */ +/* Ending sector cannot be less than Starting sector */ +typedef struct +{ + uint16 FeeVirtualSectorNumber; /* Virtual Sector's Number - 0 and 0xFFFF values are + not allowed*/ + /* Minimum 1, Maximum 4 */ + uint16 FeeFlashBank; /* Flash Bank to use for virtual sector. */ + /* As we do not allow Flash EEPROM Emulation in Bank 0, + 0 is not a valid option */ + /* Defaultvalue 1, Minimum 1, Maxiumum 7 */ + Fapi_FlashSectorType FeeStartSector; /* Defines the Starting Sector inthe Bank for + this VirtualSector*/ + Fapi_FlashSectorType FeeEndSector; /* Defines the Ending Sector inthe Bank for this + Virtual Sector */ + /* Start and End sectors can be the same, which indicates only + one sector */ + /* is the entire virtual sector. */ + /* Values are based on the FLASH_SECT enum */ + /* Defaultvalue and Min is the same sector defined as the starting + sector */ + /* Max values are based onthe device definition file being used.*/ +} Fee_VirtualSectorConfigType; + +/* Structure used when defining blocks */ +typedef struct +{ + uint16 FeeBlockNumber; /* Block's Number - 0 and 0xFFFF values are not allowed */ + /* Start 1, Next: Number of Blocks + 1, Min 1, Max 0xFFFE */ + uint16 FeeBlockSize; /* Block's Size - Actual number of bits used is reduced */ + /* by number of bits used for dataset. */ + /* Default 8, Min 1, Max (2^(16-# of Dataset Bits))-1 */ + boolean FeeImmediateData; /* Indicates if the block is used for immediate data */ + /* Default: False */ + uint32 FeeNumberOfWriteCycles; /* Number of write cycles this block requires */ + /* Default: 0, but this will not be a valid number. + Force customer to select a value */ + /* Min 1, Max (2^32)-1 */ + uint8 FeeDeviceIndex; /* Device Index - This will always be 0 */ + /* Fixed value: 0 */ + uint8 FeeNumberOfDataSets; /* Number of DataSets for the Block */ + /* Default value: 1 */ + uint8 FeeEEPNumber; +} Fee_BlockConfigType; + +/* Structure used for Global variables */ +typedef struct +{ + TI_Fee_AddressType Fee_oFlashNextAddress; /* The next Flash Address to write to */ + TI_Fee_AddressType Fee_oCopyCurrentAddress; /* Indicates the Address within the Active + VS which will be copied to Copy VS */ + TI_Fee_AddressType Fee_oCopyNextAddress; /* Indicates the Address within the Copy VS + to which the data from Active VS will be + copied to */ + TI_Fee_AddressType Fee_u32nextwriteaddress; /* Indicates the next free Address within + the curent VS to which the data will be + written */ + TI_Fee_AddressType Fee_oVirtualSectorStartAddress; /* Start Address of the current + Virtual Sector */ + TI_Fee_AddressType Fee_oVirtualSectorEndAddress; /* End Address of the current Virtual + Sector */ + TI_Fee_AddressType Fee_oCopyVirtualSectorAddress; /* Start Address of the Copy Virtual + Address */ + TI_Fee_AddressType Fee_oCurrentStartAddress; /* Start Address of the Previous Block */ + TI_Fee_AddressType Fee_oCurrentBlockHeader; /* Start Address of the Block which is + being currently written*/ + TI_Fee_AddressType Fee_oWriteAddress; /* Address within the VS where data is to be + written */ + TI_Fee_AddressType Fee_oCopyWriteAddress; /* Address within the VS where data is to be + copied */ + TI_Fee_AddressType Fee_oActiveVirtualSectorAddress; /* Start Address of the Active VS + */ + TI_Fee_AddressType Fee_oBlankFailAddress; /* Address of first non-blank location */ + TI_Fee_AddressType Fee_oActiveVirtualSectorStartAddress; /* Start Address of the + active VS */ + TI_Fee_AddressType Fee_oActiveVirtualSectorEndAddress; /* End Address of the active VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorStartAddress; /* Start Address of the Copy VS + */ + TI_Fee_AddressType Fee_oCopyVirtualSectorEndAddress; /* End Address of the Copy VS */ + TI_Fee_AddressType Fee_u32nextActiveVSwriteaddress; /* Next write address in Active VS + */ + TI_Fee_AddressType Fee_u32nextCopyVSwriteaddress; /* Next write address in Copy VS */ + uint16 Fee_u16CopyBlockSize; /* Indicates the size of current block in bytes which is + been copied from Active to Copy VS */ + uint8 Fee_u8VirtualSectorStart; /* Index of the Start Sector of the VS */ + uint8 Fee_u8VirtualSectorEnd; /* Index of the End Sector of the VS */ + uint32 Fee_au32VirtualSectorStateValue[ TI_FEE_VIRTUAL_SECTOR_OVERHEAD + >> 2U ]; /* Array to store the Virtual + Sector Header and + Information record */ + uint8 Fee_au8VirtualSectorState[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Stores the + state of each + Virtual sector + */ + uint32 Fee_au32VirtualSectorEraseCount[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; /* Array + to + store + the + erase + count + of each + Virtual + Sector*/ + uint16 Fee_au16BlockOffset[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to store within + the VS */ + uint32 Fee_au32BlockHeader[ TI_FEE_BLOCK_OVERHEAD >> 2U ]; /* Array to store the Block + Header value */ + uint8 Fee_au8BlockCopyStatus[ TI_FEE_TOTAL_BLOCKS_DATASETS ]; /* Array to storeblock + copy status */ + uint8 Fee_u8InternalVirtualSectorStart; /* Indicates internal VS start index */ + uint8 Fee_u8InternalVirtualSectorEnd; /* Indicates internal VS end index */ + TI_FeeModuleStatusType Fee_ModuleState; /* Indicates the state of the FEE module */ + TI_FeeJobResultType Fee_u16JobResult; /* Stores the Job Result of the current command + */ + TI_Fee_StatusType Fee_oStatus; /* Indicates the status of FEE */ + TI_Fee_ErrorCodeType Fee_Error; /* Indicates the Error code */ + uint16 Fee_u16CopyBlockNumber; /* Block number which is currently being copied */ + uint16 Fee_u16BlockIndex; /* Index of the Current Block */ + uint16 Fee_u16BlockCopyIndex; /* Index of the Block being copied from Copy to Active + VS */ + uint16 Fee_u16DataSetIndex; /* Index of the Current DataSet */ + uint16 Fee_u16ArrayIndex; /* Index of the Current DataSet */ + uint16 Fee_u16BlockSize; /* Size of the current block in bytes */ + uint16 Fee_u16BlockSizeinBlockHeader; /* Size of the current block. Used to write into + Block Header */ + uint16 Fee_u16BlockNumberinBlockHeader; /* Number of the current block. Used to write + into Block Header */ + uint8 Fee_u8ActiveVirtualSector; /* Indicates the FeeVirtualSectorNumber for the + Active VS */ + uint8 Fee_u8CopyVirtualSector; /* Indicates the FeeVirtualSectorNumber for the Copy VS + */ + uint32 Fee_u32InternalEraseQueue; /* Indicates which VS can be erased when the FEE is + in BusyInternal State*/ + uint8 Fee_u8WriteCopyVSHeader; /* Indicates the number of bytes of the Copy VS Header + being written */ + uint8 Fee_u8WriteCount; /* Indicates the number of bytes of the Block Header being + written */ + uint8 * Fee_pu8ReadDataBuffer; /* Pointer to read data */ + uint8 * Fee_pu8ReadAddress; /* Pointer to read address */ + uint8 * Fee_pu8Data; /* Pointer to the next data to be written to the VS */ + uint8 * Fee_pu8CopyData; /* Pointer to the next data to be copied to the VS */ + uint8 * Fee_pu8DataStart; /* Pointer to the first data to be written to the VS */ + boolean Fee_bInvalidWriteBit; /* Indicates whether the block is + written/invalidated/erased for the first time */ + boolean Fee_bWriteData; /* Indicates that there is data which is pending to be written + to the Block */ + boolean Fee_bWriteBlockHeader; /* Indicates whether the Block Header has been written + or not */ + boolean bWriteFirstTime; /* Indicates if the block is being written first time */ + boolean Fee_bFindNextVirtualSector; /* Indicates if there is aneed to find next free + VS */ + boolean Fee_bWriteVSHeader; /* Indicates if block header needs to be written */ + boolean Fee_bWriteStartProgram; /* Indicates if start program block header needs to be + written */ + boolean Fee_bWritePartialBlockHeader; /* Indicates if start program block header needs + to be written */ + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) + uint16 Fee_au16UnConfiguredBlockAddress + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Indicates + number of unconfigured blocks to copy */ + uint8 Fee_au8UnConfiguredBlockCopyStatus + [ TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY ]; /* Array to store block + copy status */ + #endif +} TI_Fee_GlobalVarsType; + +/********************************************************************************************************************** + * EXTERN Declarations + *********************************************************************************************************************/ +/* Fee Global Variables */ +extern const Fee_BlockConfigType Fee_BlockConfiguration[ TI_FEE_NUMBER_OF_BLOCKS ]; + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_OFF ) +extern const Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern const Device_FlashType Device_FlashDevice; + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +extern Fee_VirtualSectorConfigType + Fee_VirtualSectorConfiguration[ TI_FEE_NUMBER_OF_VIRTUAL_SECTORS ]; +extern Device_FlashType Device_FlashDevice; +extern uint8 TI_Fee_MaxSectors; + #endif +extern TI_Fee_GlobalVarsType TI_Fee_GlobalVariables[ TI_FEE_NUMBER_OF_EEPS ]; +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord[ TI_FEE_NUMBER_OF_EEPS ]; + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +extern uint32 TI_Fee_u32FletcherChecksum; + #endif +extern uint32 TI_Fee_u32BlockEraseCount; +extern uint8 TI_Fee_u8DataSets; +extern uint8 TI_Fee_u8DeviceIndex; +extern uint32 TI_Fee_u32ActCpyVS; +extern uint8 TI_Fee_u8ErrEraseVS; + #if( TI_FEE_NUMBER_OF_UNCONFIGUREDBLOCKSTOCOPY != 0U ) +extern uint16 TI_Fee_u16NumberOfUnconfiguredBlocks[ TI_FEE_NUMBER_OF_EEPS ]; + #endif + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern boolean Fee_bDoubleBitError; +extern boolean Fee_bSingleBitError; + #endif + #if( TI_FEE_NUMBER_OF_EEPS == 2U ) +extern TI_Fee_StatusWordType_UN TI_Fee_oStatusWord_Global; + #endif +extern boolean TI_Fee_FapiInitCalled; +extern boolean TI_Fee_bEraseSuspended; +extern boolean TI_Fee_bIsMainFunctionCalled; + +/********************************************************************************************************************** + * GLOBAL FUNCTION PROTOTYPES + *********************************************************************************************************************/ +/* Interface Functions */ +extern void TI_Fee_Cancel( uint8 u8EEPIndex ); +extern Std_ReturnType TI_Fee_EraseImmediateBlock( uint16 BlockNumber ); +extern TI_FeeModuleStatusType TI_Fee_GetStatus( uint8 u8EEPIndex ); +extern void TI_Fee_GetVersionInfo( Std_VersionInfoType * VersionInfoPtr ); +extern void TI_Fee_Init( void ); +extern Std_ReturnType TI_Fee_InvalidateBlock( uint16 BlockNumber ); +extern Std_ReturnType TI_Fee_Read( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); +extern Std_ReturnType TI_Fee_WriteAsync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern void TI_Fee_MainFunction( void ); +extern TI_Fee_ErrorCodeType TI_FeeErrorCode( uint8 u8EEPIndex ); +extern void TI_Fee_ErrorRecovery( TI_Fee_ErrorCodeType ErrorCode, uint8 u8VirtualSector ); +extern TI_FeeJobResultType TI_Fee_GetJobResult( uint8 u8EEPIndex ); +extern void TI_Fee_SuspendResumeErase( TI_Fee_EraseCommandType Command ); + + #if( TI_FEE_FLASH_ERROR_CORRECTION_HANDLING == TI_Fee_Fix ) +extern void TI_Fee_ErrorHookSingleBitError( void ); +extern void TI_Fee_ErrorHookDoubleBitError( void ); + #endif + + #if( TI_FEE_DRIVER == 1U ) +extern Std_ReturnType TI_Fee_WriteSync( uint16 BlockNumber, uint8 * DataBufferPtr ); +extern Std_ReturnType TI_Fee_Shutdown( void ); +extern boolean TI_Fee_Format( uint32 u32FormatKey ); +extern Std_ReturnType TI_Fee_ReadSync( uint16 BlockNumber, + uint16 BlockOffset, + uint8 * DataBufferPtr, + uint16 Length ); + #endif + +/* TI Fee Internal Functions */ +TI_Fee_AddressType TI_FeeInternal_GetNextFlashAddress( uint8 u8EEPIndex ); +TI_Fee_AddressType TI_FeeInternal_AlignAddressForECC( TI_Fee_AddressType oAddress ); +TI_Fee_AddressType TI_FeeInternal_GetCurrentBlockAddress( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - + * TI_FeeInternal_GetVirtualSectorParameter name is required here."*/ +uint32 TI_FeeInternal_GetVirtualSectorParameter( Fapi_FlashSectorType oSector, + uint16 u16Bank, + boolean VirtualSectorInfo, + uint8 u8EEPIndex ); +uint32 TI_FeeInternal_PollFlashStatus( void ); +uint16 TI_FeeInternal_GetBlockSize( uint16 BlockIndex ); +uint16 TI_FeeInternal_GetBlockIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetDataSetIndex( uint16 BlockNumber ); +uint16 TI_FeeInternal_GetBlockNumber( uint16 BlockNumber ); +uint8 TI_FeeInternal_FindNextVirtualSector( uint8 u8EEPIndex ); +uint8 TI_FeeInternal_WriteDataF021( boolean bCopy, + uint16 u16WriteSize, + uint8 u8EEPIndex ); +boolean TI_FeeInternal_BlankCheck( uint32 u32StartAddress, + uint32 u32EndAddress, + uint16 u16Bank, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckReadParameters( uint32 u32BlockSize, + uint16 BlockOffset, + const uint8 * DataBufferPtr, + uint16 Length, + uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_CheckModuleState( uint8 u8EEPIndex ); +Std_ReturnType TI_FeeInternal_InvalidateErase( uint16 BlockNumber ); +TI_Fee_StatusType TI_FeeInternal_FeeManager( uint8 u8EEPIndex ); +void TI_FeeInternal_WriteVirtualSectorHeader( uint8 FeeVirtualSectorNumber, + VirtualSectorStatesType VsState, + uint8 u8EEPIndex ); +/*SAFETYMCUSW 61 X MR:1.4,5.1 "Reason - TI_FeeInternal_GetVirtualSectorIndex + * name is required here."*/ +void TI_FeeInternal_GetVirtualSectorIndex( Fapi_FlashSectorType oSectorStart, + Fapi_FlashSectorType oSectorEnd, + uint16 u16Bank, + boolean bOperation, + uint8 u8EEPIndex ); +void TI_FeeInternal_WritePreviousBlockHeader( boolean bWrite, uint8 u8EEPIndex ); +void TI_FeeInternal_WriteBlockHeader( boolean bWrite, + uint8 u8EEPIndex, + uint16 Fee_BlockSize_u16, + uint16 u16BlockNumber ); +void TI_FeeInternal_SetClearCopyBlockState( uint8 u8EEPIndex, boolean bSetClear ); +void TI_FeeInternal_SanityCheck( uint16 BlockSize, uint8 u8EEPIndex ); +void TI_FeeInternal_StartProgramBlock( uint8 u8EEPIndex ); +void TI_FeeInternal_UpdateBlockOffsetArray( uint8 u8EEPIndex, + boolean bActCpyVS, + uint8 u8VirtualSector ); +void TI_FeeInternal_WriteInitialize( TI_Fee_AddressType oFlashNextAddress, + uint8 * DataBufferPtr, + uint8 u8EEPIndex ); +void TI_FeeInternal_CheckForError( uint8 u8EEPIndex ); +void TI_FeeInternal_EnableRequiredFlashSector( uint32 u32VirtualSectorStartAddress ); +uint16 TI_FeeInternal_GetArrayIndex( uint16 BlockNumber, + uint16 DataSetNumber, + uint8 u8EEPIndex, + boolean bCallContext ); + #if( TI_FEE_FLASH_CHECKSUM_ENABLE == STD_ON ) +uint32 TI_FeeInternal_Fletcher16( uint8 const * pu8data, uint16 u16Length ); + #endif + #if( TI_FEE_GENERATE_DEVICEANDVIRTUALSECTORSTRUC == STD_ON ) +void TI_FeeInternal_PopulateStructures( TI_Fee_DeviceType DeviceType ); + #endif +#endif /* TI_FEE_H */ +/********************************************************************************************************************** + * END OF FILE: ti_fee.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h new file mode 100644 index 00000000000..60e8117e6c1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_cfg.h @@ -0,0 +1,55 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_cfg.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: HALCoGen + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 00.00.01 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 01.19.04 05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version + *history. + * + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h new file mode 100644 index 00000000000..7dea8d67c26 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/include/ti_fee_types.h @@ -0,0 +1,260 @@ +/********************************************************************************************************************** + * FILE DESCRIPTION + * ------------------------------------------------------------------------------------------------------------------- + * File: ti_fee_types.h + * Project: Tms570_TIFEEDriver + * Module: TIFEEDriver + * Generator: None + * + * Description: This file implements the TI FEE Api. + *--------------------------------------------------------------------------------------------------------------------- + * Author: Vishwanath Reddy + *--------------------------------------------------------------------------------------------------------------------- + * Revision History + *--------------------------------------------------------------------------------------------------------------------- + * Version Date Author Change ID Description + *--------------------------------------------------------------------------------------------------------------------- + * 03.00.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.00 31Aug2012 Vishwanath Reddy 0000000000000 Initial Version + * 00.01.02 30Nov2012 Vishwanath Reddy SDOCM00097786 Misra Fixes, Memory + *segmentation changes. 01.12.00 13Dec2013 Vishwanath Reddy SDOCM00105412 + *MISRA C fixes. + * 01.15.00 06Jun2014 Vishwanath Reddy Support for LC + *Varients. 01.16.00 15Jul2014 Vishwanath Reddy SDOCM00112141 Remove + *MISRA warnings. + * 01.18.00 12Oct2015 Vishwanath Reddy SDOCM00119455 Update version + *history. + * 01.18.01 17Nov2015 Vishwanath Reddy SDOCM00120161 Update version + *history. + * 01.18.02 05Feb2016 Vishwanath Reddy SDOCM00121158 Update version + *history. 01.18.03 30June2016 Vishwanath Reddy SDOCM00122388 Update + *version history. SDOCM00122429 Added error when endianess is not defined. 01.19.00 + *08Augu2016 Vishwanath Reddy SDOCM00122592 Update version history. 01.19.01 + *12Augu2016 Vishwanath Reddy SDOCM00122543 Update version history. 01.19.03 + *15May2017 Prathap Srinivasan SDOCM00122917 Update version history. 01.19.04 + *05Dec2017 Prathap Srinivasan HERCULES_SW-5082 Update version history. + *********************************************************************************************************************/ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#ifndef TI_FEE_TYPES_H + #define TI_FEE_TYPES_H + + /********************************************************************************************************************** + * INCLUDES + *********************************************************************************************************************/ + #include "Device_header.h" + + #ifndef TI_Fee_None + #define TI_Fee_None \ + 0x00U /*Take no action on single bit errors, (respond with corrected data), \ + */ + /*return error for uncorrectable error reads (multibit errors for ECC or parity + * failures)*/ + /*For devices with no ECC (they may have parity or not) the only valid option is none. + */ + #endif + + #ifndef TI_Fee_Fix + #define TI_Fee_Fix 0x01U /* single bit error will be fixed by reprogramming */ + /* return previous valid data for uncorrectable error reads (multi bit errors for ECC + or parity failures). */ + #endif + + #if !defined( _LITTLE_ENDIAN ) && !defined( _BIG_ENDIAN ) + #error "Target Endianess is not defined. Include F021 header files and library." + #endif + +/*SAFETYMCUSW 74 S MR:18.4 "Reason - union declaration is necessary here."*/ +typedef union +{ + uint16 Fee_u16StatusWord; + #ifdef _BIG_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + } Fee_StatusWordType_ST; + #endif + #ifdef _LITTLE_ENDIAN + struct + { + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 SingleBitError : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Initialized : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Copy : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 InvalidateBlock : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 EraseImmediate : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteAsync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 WriteSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Read : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ProgramFailed : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 ReadSync : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Erase : 1U; + /*SAFETYMCUSW 42 S MR:3.5 "Reason - Bit field declaration is necessary + * here."*/ + /*SAFETYMCUSW 73 S MR:6.4 "Reason - Bit field is declared as + * unsigned."*/ + uint16 Reserved : 5U; + } Fee_StatusWordType_ST; + #endif +} TI_Fee_StatusWordType_UN; + +typedef enum +{ + UNINIT, + IDLE, + /*SAFETYMCUSW 91 S MR:5.2,5.6,5.7 "Reason - BUSY in F021 is a member of + * structure."*/ + BUSY, + BUSY_INTERNAL +} TI_FeeModuleStatusType; + +typedef enum +{ + JOB_OK, + JOB_FAILED, + JOB_PENDING, + JOB_CANCELLED, + BLOCK_INCONSISTENT, + BLOCK_INVALID +} TI_FeeJobResultType; + +#endif /* TI_FEE_TYPES_H */ + +/********************************************************************************************************************** + * END OF FILE: ti_fee_types.h + *********************************************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c new file mode 100644 index 00000000000..c9b4ed5f955 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/adc.c @@ -0,0 +1,1052 @@ +/** @file adc.c + * @brief ADC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ADC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void adcInit(void) + * @brief Initializes ADC Driver + * + * This function initializes the ADC driver. + * + */ +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : ADC_SourceId_001 */ +/* DesignId : ADC_DesignId_001 */ +/* Requirements : CONQ_ADC_SR2 */ +void adcInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b Initialize @b ADC1: */ + + /** - Reset ADC module */ + adcREG1->RSTCR = 1U; + adcREG1->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG1->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG1->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG1->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG1->BNDEND = ( adcREG1->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup event group sample window */ + adcREG1->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 1 sample window */ + adcREG1->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG1->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG1->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC1_EVENT; + + /** - Setup group 2 sample window */ + adcREG1->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG1->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC1 EVT pin output value */ + adcREG1->EVTOUT = 0U; + + /** - ADC1 EVT pin direction */ + adcREG1->EVTDIR = 0U; + + /** - ADC1 EVT pin open drain enable */ + adcREG1->EVTPDR = 0U; + + /** - ADC1 EVT pin pullup / pulldown selection */ + adcREG1->EVTPSEL = 1U; + + /** - ADC1 EVT pin pullup / pulldown enable*/ + adcREG1->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG1->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG1->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG1->PARCR = 0x00000005U; + + /** @b Initialize @b ADC2: */ + + /** - Reset ADC module */ + adcREG2->RSTCR = 1U; + adcREG2->RSTCR = 0U; + + /** - Enable 12-BIT ADC */ + adcREG2->OPMODECR |= 0x80000000U; + + /** - Setup prescaler */ + adcREG2->CLOCKCR = 7U; + + /** - Setup memory boundaries */ + adcREG2->BNDCR = ( uint32 ) ( ( uint32 ) 8U << 16U ) | ( 8U + 8U ); + adcREG2->BNDEND = ( adcREG2->BNDEND & 0xFFFF0000U ) | ( 2U ); + + /** - Setup event group conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 0U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U; + + /** - Setup event group hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->EVSRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup event group sample window */ + adcREG2->EVSAMP = 1U; + + /** - Setup event group sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->EVSAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 1 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 1U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 1 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G1SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 1 sample window */ + adcREG2->G1SAMP = 1U; + + /** - Setup group 1 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G1SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - Setup group 2 conversion mode + * - Setup data format + * - Enable/Disable channel id in conversion result + * - Enable/Disable continuous conversion + */ + adcREG2->GxMODECR[ 2U ] = ( uint32 ) ADC_12_BIT | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup group 2 hardware trigger + * - Setup hardware trigger edge + * - Setup hardware trigger source + */ + adcREG2->G2SRC = ( uint32 ) 0x00000000U | ( uint32 ) ADC2_EVENT; + + /** - Setup group 2 sample window */ + adcREG2->G2SAMP = 1U; + + /** - Setup group 2 sample discharge + * - Setup discharge prescaler + * - Enable/Disable discharge + */ + adcREG2->G2SAMPDISEN = ( uint32 ) ( ( uint32 ) 0U << 8U ) | ( uint32 ) 0x00000000U; + + /** - ADC2 EVT pin output value */ + adcREG2->EVTOUT = 0U; + + /** - ADC2 EVT pin direction */ + adcREG2->EVTDIR = 0U; + + /** - ADC2 EVT pin open drain enable */ + adcREG2->EVTPDR = 0U; + + /** - ADC2 EVT pin pullup / pulldown selection */ + adcREG2->EVTPSEL = 1U; + + /** - ADC2 EVT pin pullup / pulldown enable*/ + adcREG2->EVTDIS = 0U; + + /** - Enable ADC module */ + adcREG2->OPMODECR |= 0x80140001U; + + /** - Wait for buffer initialization complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( adcREG2->BNDEND & 0xFFFF0000U ) >> 16U ) != 0U ) + { + } /* Wait */ + + /** - Setup parity */ + adcREG2->PARCR = 0x00000005U; + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** - s_adcSelect is used as constant table for channel selection */ +static const uint32 s_adcSelect[ 2U ][ 3U ] = { + { 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U }, + { + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U, + } +}; + +/** - s_adcFiFoSize is used as constant table for channel selection */ +static const uint32 s_adcFiFoSize[ 2U ][ 3U ] = { { 16U, 16U, 16U }, { 16U, 16U, 16U } }; + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/** @fn void adcStartConversion(adcBASE_t *adc, uint32 group) + * @brief Starts an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function starts a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_002 */ +/* DesignId : ADC_DesignId_002 */ +/* Requirements : CONQ_ADC_SR3 */ +void adcStartConversion( adcBASE_t * adc, uint32 group ) +{ + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Setup FiFo size */ + adc->GxINTCR[ group ] = s_adcFiFoSize[ index ][ group ]; + + /** - Start Conversion */ + adc->GxSEL[ group ] = s_adcSelect[ index ][ group ]; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/** @fn void adcStopConversion(adcBASE_t *adc, uint32 group) + * @brief Stops an ADC conversion + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function stops a conversion of the ADC hardware group. + * + */ +/* SourceId : ADC_SourceId_003 */ +/* DesignId : ADC_DesignId_003 */ +/* Requirements : CONQ_ADC_SR4 */ +void adcStopConversion( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Stop Conversion */ + adc->GxSEL[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/** @fn void adcResetFiFo(adcBASE_t *adc, uint32 group) + * @brief Resets FiFo read and write pointer. + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function resets the FiFo read and write pointers. + * + */ +/* SourceId : ADC_SourceId_004 */ +/* DesignId : ADC_DesignId_004 */ +/* Requirements : CONQ_ADC_SR5 */ +void adcResetFiFo( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Reset FiFo */ + adc->GxFIFORESETCR[ group ] = 1U; + + /** @note The function adcInit has to be called before this function can be used.\n + * the conversion should be stopped before calling this function. + */ + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/** @fn uint32 adcGetData(adcBASE_t *adc, uint32 group, adcData_t * data) + * @brief Gets converted a ADC values + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @param[out] data Pointer to store ADC converted data + * @return The function will return the number of converted values copied into data + * buffer: + * + * This function writes a ADC message into a ADC message box. + * + */ +/* SourceId : ADC_SourceId_005 */ +/* DesignId : ADC_DesignId_005 */ +/* Requirements : CONQ_ADC_SR6 */ +uint32 adcGetData( adcBASE_t * adc, uint32 group, adcData_t * data ) +{ + uint32 i; + uint32 buf; + uint32 mode; + uint32 index = ( adc == adcREG1 ) ? 0U : 1U; + + uint32 intcr_reg = adc->GxINTCR[ group ]; + uint32 count = ( intcr_reg >= 256U ) ? s_adcFiFoSize[ index ][ group ] + : ( s_adcFiFoSize[ index ][ group ] + - ( uint32 ) ( intcr_reg & 0xFFU ) ); + adcData_t * ptr = data; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mode = ( adc->OPMODECR & ADC_12_BIT_MODE ); + + if( mode == ADC_12_BIT_MODE ) + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0xFFFU ); + ptr->id = ( uint32 ) ( ( buf >> 16U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + else + { + /** - Get conversion data and channel/pin id */ + for( i = 0U; i < count; i++ ) + { + buf = adc->GxBUF[ group ].BUF0; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr->value = ( uint16 ) ( buf & 0x3FFU ); + ptr->id = ( uint32 ) ( ( buf >> 10U ) & 0x1FU ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + ptr++; + } + } + + adc->GxINTFLG[ group ] = 9U; + + /** @note The function adcInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return count; +} + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/** @fn uint32 adcIsFifoFull(adcBASE_t *adc, uint32 group) + * @brief Checks if FiFo buffer is full + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When FiFo buffer is not full + * - 1: When FiFo buffer is full + * - 3: When FiFo buffer overflow occurred + * + * This function checks FiFo buffer status. + * + */ +/* SourceId : ADC_SourceId_006 */ +/* DesignId : ADC_DesignId_006 */ +/* Requirements : CONQ_ADC_SR7 */ +uint32 adcIsFifoFull( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read FiFo flags */ + flags = adc->GxINTFLG[ group ] & 3U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/** @fn uint32 adcIsConversionComplete(adcBASE_t *adc, uint32 group) + * @brief Checks if Conversion is complete + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * @return The function will return: + * - 0: When is not finished + * - 8: When conversion is complete + * + * This function checks if conversion is complete. + * + */ +/* SourceId : ADC_SourceId_007 */ +/* DesignId : ADC_DesignId_007 */ +/* Requirements : CONQ_ADC_SR8 */ +uint32 adcIsConversionComplete( adcBASE_t * adc, uint32 group ) +{ + uint32 flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Read conversion flags */ + flags = adc->GxINTFLG[ group ] & 8U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return flags; +} + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/** @fn void adcCalibration(adcBASE_t *adc) + * @brief Computes offset error using Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * This function computes offset error using Calibration mode + * + */ +/* SourceId : ADC_SourceId_008 */ +/* DesignId : ADC_DesignId_010 */ +/* Requirements : CONQ_ADC_SR11 */ +void adcCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + uint32 conv_val[ 5U ] = { 0U, 0U, 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 4U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + case 2U: /* Test 1 : Bride En = 1 , HiLo =0 */ + adc->CALCR = 0x0200U; + break; + + case 3U: /* Test 1 : Bride En = 1 , HiLo =1 */ + adc->CALCR = 0x0300U; + break; + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 4U ] = conv_val[ 0U ] + conv_val[ 1U ] + conv_val[ 2U ] + conv_val[ 3U ]; + + conv_val[ 4U ] = ( conv_val[ 4U ] / 4U ); + + offset_error = conv_val[ 4U ] - 0x7FFU; + + /*Write the offset error to the Calibration register */ + /* Load 2;s complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error & 0xFFFU; + offset_error = offset_error + 1U; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + /** @note The function adcInit has to be called before using this function. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/** @fn void adcMidPointCalibration(adcBASE_t *adc) + * @brief Computes offset error using Mid Point Calibration mode + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @return This function will return offset error using Mid Point Calibration mode + * + * This function computes offset error using Mid Point Calibration mode + * + */ +/* SourceId : ADC_SourceId_009 */ +/* DesignId : ADC_DesignId_011 */ +/* Requirements : CONQ_ADC_SR12 */ +uint32 adcMidPointCalibration( adcBASE_t * adc ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + uint32 conv_val[ 3U ] = { 0U, 0U, 0U }; + uint32 loop_index = 0U; + uint32 offset_error = 0U; + uint32 backup_mode; + + /** - Backup Mode before Calibration */ + backup_mode = adc->OPMODECR; + + /** - Enable 12-BIT ADC */ + adc->OPMODECR |= 0x80000000U; + + /* Disable all channels for conversion */ + adc->GxSEL[ 0U ] = 0x00U; + adc->GxSEL[ 1U ] = 0x00U; + adc->GxSEL[ 2U ] = 0x00U; + + for( loop_index = 0U; loop_index < 2U; loop_index++ ) + { + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + switch( loop_index ) + { + case 0U: /* Test 1 : Bride En = 0 , HiLo =0 */ + adc->CALCR = 0x0U; + break; + + case 1U: /* Test 1 : Bride En = 0 , HiLo =1 */ + adc->CALCR = 0x0100U; + break; + + default: + break; + } + + /* Enable Calibration mode */ + adc->CALCR |= 0x1U; + + /* Start calibration conversion */ + adc->CALCR |= 0x00010000U; + + /* Wait for calibration conversion to complete */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( adc->CALCR & 0x00010000U ) == 0x00010000U ) + { + } /* Wait */ + + /* Read converted value */ + conv_val[ loop_index ] = adc->CALR; + } + + /* Disable Self Test and Calibration mode */ + adc->CALCR = 0x0U; + + /* Compute the Offset error correction value */ + conv_val[ 2U ] = ( conv_val[ 0U ] ) + ( conv_val[ 1U ] ); + + conv_val[ 2U ] = ( conv_val[ 2U ] / 2U ); + + offset_error = conv_val[ 2U ] - 0x7FFU; + + /* Write the offset error to the Calibration register */ + /* Load 2's complement of the computed value to ADCALR register */ + offset_error = ~offset_error; + offset_error = offset_error + 1U; + offset_error = offset_error & 0xFFFU; + + adc->CALR = offset_error; + + /** - Restore Mode after Calibration */ + adc->OPMODECR = backup_mode; + + return ( offset_error ); + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void adcEnableNotification(adcBASE_t *adc, uint32 group) + * @brief Enable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will enable the notification of a conversion. + * In single conversion mode for conversion complete and + * in continuous conversion mode when the FiFo buffer is full. + * + */ +/* SourceId : ADC_SourceId_010 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : CONQ_ADC_SR9 */ +void adcEnableNotification( adcBASE_t * adc, uint32 group ) +{ + uint32 notif = ( ( ( uint32 ) ( adc->GxMODECR[ group ] ) & 2U ) == 2U ) ? 1U : 8U; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = notif; + + /** @note The function adcInit has to be called before this function can be used.\n + * This function should be called before the conversion is started + */ + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (32) */ +/* USER CODE END */ + +/** @fn void adcDisableNotification(adcBASE_t *adc, uint32 group) + * @brief Disable notification + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * - adcREG2: ADC2 module pointer + * @param[in] group Hardware group of ADC module: + * - adcGROUP0: ADC event group + * - adcGROUP1: ADC group 1 + * - adcGROUP2: ADC group 2 + * + * This function will disable the notification of a conversion. + */ +/* SourceId : ADC_SourceId_011 */ +/* DesignId : ADC_DesignId_008 */ +/* Requirements : CONQ_ADC_SR9 */ +void adcDisableNotification( adcBASE_t * adc, uint32 group ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + adc->GxINTENA[ group ] = 0U; + + /** @note The function adcInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} + +/** @fn void adcSetEVTPin(adcBASE_t *adc, uint32 value) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @param[in] value Value to be set: 0 or 1 + * + * This function will set the ADC EVT pin if configured as an output pin. + */ +/* SourceId : ADC_SourceId_012 */ +/* DesignId : ADC_DesignId_014 */ +/* Requirements : CONQ_ADC_SR13 */ +void adcSetEVTPin( adcBASE_t * adc, uint32 value ) +{ + adc->EVTOUT = value; +} + +/** @fn uint32 adcGetEVTPin(adcBASE_t *adc) + * @brief Set ADCEVT pin + * @param[in] adc Pointer to ADC module: + * - adcREG1: ADC1 module pointer + * @return Value of the ADC EVT pin: 0 or 1 + * + * This function will return the value of ADC EVT pin. + */ +/* SourceId : ADC_SourceId_013 */ +/* DesignId : ADC_DesignId_015 */ +/* Requirements : CONQ_ADC_SR14 */ +uint32 adcGetEVTPin( adcBASE_t * adc ) +{ + return adc->EVTIN; +} + +/** @fn void adc1GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_014 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : CONQ_ADC_SR15 */ +void adc1GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC1_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC1_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC1_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC1_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC1_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC1_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC1_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC1_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC1_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC1_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC1_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC1_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC1_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC1_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC1_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC1_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC1_PARCR_CONFIGVALUE; + } + else + { + config_reg->CONFIG_OPMODECR = adcREG1->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG1->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG1->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG1->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG1->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG1->EVSRC; + config_reg->CONFIG_G1SRC = adcREG1->G1SRC; + config_reg->CONFIG_G2SRC = adcREG1->G2SRC; + config_reg->CONFIG_BNDCR = adcREG1->BNDCR; + config_reg->CONFIG_BNDEND = adcREG1->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG1->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG1->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG1->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG1->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG1->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG1->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG1->PARCR; + } +} + +/** @fn void adc2GetConfigValue(adc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ADC_SourceId_015 */ +/* DesignId : ADC_DesignId_012 */ +/* Requirements : CONQ_ADC_SR15 */ +void adc2GetConfigValue( adc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OPMODECR = ADC2_OPMODECR_CONFIGVALUE; + config_reg->CONFIG_CLOCKCR = ADC2_CLOCKCR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 0U ] = ADC2_G0MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 1U ] = ADC2_G1MODECR_CONFIGVALUE; + config_reg->CONFIG_GxMODECR[ 2U ] = ADC2_G2MODECR_CONFIGVALUE; + config_reg->CONFIG_G0SRC = ADC2_G0SRC_CONFIGVALUE; + config_reg->CONFIG_G1SRC = ADC2_G1SRC_CONFIGVALUE; + config_reg->CONFIG_G2SRC = ADC2_G2SRC_CONFIGVALUE; + config_reg->CONFIG_BNDCR = ADC2_BNDCR_CONFIGVALUE; + config_reg->CONFIG_BNDEND = ADC2_BNDEND_CONFIGVALUE; + config_reg->CONFIG_G0SAMP = ADC2_G0SAMP_CONFIGVALUE; + config_reg->CONFIG_G1SAMP = ADC2_G1SAMP_CONFIGVALUE; + config_reg->CONFIG_G2SAMP = ADC2_G2SAMP_CONFIGVALUE; + config_reg->CONFIG_G0SAMPDISEN = ADC2_G0SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G1SAMPDISEN = ADC2_G1SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_G2SAMPDISEN = ADC2_G2SAMPDISEN_CONFIGVALUE; + config_reg->CONFIG_PARCR = ADC2_PARCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_OPMODECR = adcREG2->OPMODECR; + config_reg->CONFIG_CLOCKCR = adcREG2->CLOCKCR; + config_reg->CONFIG_GxMODECR[ 0U ] = adcREG2->GxMODECR[ 0U ]; + config_reg->CONFIG_GxMODECR[ 1U ] = adcREG2->GxMODECR[ 1U ]; + config_reg->CONFIG_GxMODECR[ 2U ] = adcREG2->GxMODECR[ 2U ]; + config_reg->CONFIG_G0SRC = adcREG2->EVSRC; + config_reg->CONFIG_G1SRC = adcREG2->G1SRC; + config_reg->CONFIG_G2SRC = adcREG2->G2SRC; + config_reg->CONFIG_BNDCR = adcREG2->BNDCR; + config_reg->CONFIG_BNDEND = adcREG2->BNDEND; + config_reg->CONFIG_G0SAMP = adcREG2->EVSAMP; + config_reg->CONFIG_G1SAMP = adcREG2->G1SAMP; + config_reg->CONFIG_G2SAMP = adcREG2->G2SAMP; + config_reg->CONFIG_G0SAMPDISEN = adcREG2->EVSAMPDISEN; + config_reg->CONFIG_G1SAMPDISEN = adcREG2->G1SAMPDISEN; + config_reg->CONFIG_G2SAMPDISEN = adcREG2->G2SAMPDISEN; + config_reg->CONFIG_PARCR = adcREG2->PARCR; + } +} + +/* USER CODE BEGIN (35) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c new file mode 100644 index 00000000000..2dbf833636c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/can.c @@ -0,0 +1,1690 @@ +/** @file can.c + * @brief CAN Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CAN driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "can.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Global and Static Variables */ + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) +#else +static const uint32 s_canByteOrder[ 8U ] = { 3U, 2U, 1U, 0U, 7U, 6U, 5U, 4U }; +#endif + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/** @fn void canInit(void) + * @brief Initializes CAN Driver + * + * This function initializes the CAN driver. + * + */ +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +/* SourceId : CAN_SourceId_001 */ +/* DesignId : CAN_DesignId_001 */ +/* Requirements : CONQ_CAN_SR4 */ +void canInit( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG1->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG1->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG1->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG1->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG1->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG1->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG1->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG1->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG1->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN1 Port output values */ + canREG1->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG1->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG1->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN2: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG2->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG2->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG2->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG2->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG2->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG2->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG2->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG2->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG2->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN2 Port output values */ + canREG2->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG2->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG2->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN3: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG3->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) 0x00000005U << 10U ) | 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG3->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG3->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + canREG3->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG3->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG3->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG3->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG3->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG3->BTR = ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 12U ) + | ( uint32 ) ( ( uint32 ) ( ( 6U + 4U ) - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) ( 4U - 1U ) << 6U ) | ( uint32 ) ( uint32 ) 9U; + + /** - CAN3 Port output values */ + canREG3->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG3->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + /** - Leave configuration and initialization mode */ + canREG3->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @b Initialize @b CAN1: */ + + /** - Setup control register + * - Disable automatic wakeup on bus activity + * - Local power down mode disabled + * - Disable DMA request lines + * - Enable global Interrupt Line 0 and 1 + * - Disable debug mode + * - Release from software reset + * - Enable/Disable parity or ECC + * - Enable/Disable auto bus on timer + * - Setup message completion before entering debug state + * - Setup normal operation mode + * - Request write access to the configuration registers + * - Setup automatic retransmission of messages + * - Disable error interrupts + * - Disable status interrupts + * - Enter initialization mode + */ + canREG4->CTL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( ( uint32 ) 0x00000005U << 10U ) | ( uint32 ) 0x00020043U; + + /** - Clear all pending error flags and reset current status */ + canREG4->ES |= 0xFFFFFFFFU; + + /** - Assign interrupt level for messages */ + canREG4->INTMUXx[ 0U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + canREG4->INTMUXx[ 1U ] = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup auto bus on timer period */ + canREG4->ABOTR = ( uint32 ) 0U; + + /** - Setup IF1 for data transmission + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG4->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG4->IF1CMD = 0x87U; + + /** - Setup IF2 for reading data + * - Wait until IF1 is ready for use + * - Set IF1 control byte + */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( canREG4->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + canREG4->IF2CMD = 0x17U; + + /** - Setup bit timing + * - Setup baud rate prescaler extension + * - Setup TSeg2 + * - Setup TSeg1 + * - Setup sample jump width + * - Setup baud rate prescaler + */ + canREG4->BTR = ( ( uint32 ) 0U << 16U ) | ( ( ( uint32 ) 4U - 1U ) << 12U ) + | ( ( ( ( uint32 ) 6U + ( uint32 ) 4U ) - 1U ) << 8U ) + | ( ( ( uint32 ) 4U - 1U ) << 6U ) | ( uint32 ) 9U; + + /** - CAN4 Port output values */ + canREG4->TIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + + canREG4->RIOC = ( uint32 ) ( ( uint32 ) 1U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 1U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ); + /** - Leave configuration and initialization mode */ + canREG4->CTL &= ~( uint32 ) ( 0x00000041U ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn uint32 canTransmit(canBASE_t *node, uint32 messageBox, const uint8 * data) + * @brief Transmits a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of the TX message box wasn't successful + * - 1: When the setup of the TX message box was successful + * + * This function writes a CAN message into a CAN message box. + * + */ + +/* USER CODE BEGIN (6) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_002 */ +/* DesignId : CAN_DesignId_002 */ +/* Requirements : CONQ_CAN_SR5 */ +uint32 canTransmit( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + * - Start Transmission + */ + node->IF1CMD = 0x87U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetData(canBASE_t *node, uint32 messageBox, uint8 * const data) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return: + * - 0: When RX message box hasn't received new data + * - 1: When RX data are stored in the data buffer + * - 3: When RX data are stored in the data buffer and a message was lost + * + * This function writes a CAN message into a CAN message box. + * + */ + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_003 */ +/* DesignId : CAN_DesignId_003 */ +/* Requirements : CONQ_CAN_SR6 */ +uint32 canGetData( canBASE_t * node, uint32 messageBox, uint8 * const data ) +{ + uint32 i; + uint32 size; + uint8 * pData = data; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /** - Check if new data have been arrived: + * - no new data, return 0 + * - new data, get received message + */ + if( ( node->NWDATx[ regIndex ] & bitIndex ) == 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF2 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x17U; + + /** - Copy data into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Get number of received bytes */ + size = node->IF2MCTL & 0xFU; + if( size > 0x8U ) + { + size = 0x8U; + } + /** - Copy RX data into destination buffer */ + for( i = 0U; i < size; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + pData++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *pData = node->IF2DATx[ s_canByteOrder[ i ] ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + pData++; +#endif + } + + success = 1U; + } + /** - Check if data have been lost: + * - no data lost, return 1 + * - data lost, return 3 + */ + if( ( node->IF2MCTL & 0x4000U ) == 0x4000U ) + { + success = 3U; + } + + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return success; +} + +/** @fn uint32 canGetID(canBASE_t *node, uint32 messageBox) + * @brief Gets received a CAN message + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[out] data Pointer to store CAN RX data + * @return The function will return the ID of the message box. + * + * This function gets the identifier of a CAN message box. + * + */ +/* SourceId : CAN_SourceId_026 */ +/* DesignId : CAN_DesignId_020 */ +/* Requirements : CONQ_CAN_SR39 */ +uint32 canGetID( canBASE_t * node, uint32 messageBox ) +{ + uint32 msgBoxID = 0U; + + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0x20U; + + /** - Copy message box number into IF2 */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /* Read Message Box ID from Arbitration register. */ + msgBoxID = ( node->IF2ARB & 0x1FFFFFFFU ); + + return msgBoxID; +} + +/** @fn uint32 canUpdateID(canBASE_t *node, uint32 messageBox, uint32 msgBoxArbitVal) +* @brief Gets received a CAN message +* @param[in] node Pointer to CAN node: +* - canREG1: CAN1 node pointer +* - canREG2: CAN2 node pointer +* - canREG3: CAN3 node pointer +* - canREG4: CAN4 node pointer +* @param[in] messageBox Message box number of CAN node: +* - canMESSAGE_BOX1: CAN message box 1 +* - canMESSAGE_BOXn: CAN message box n [n: 1-64] +* - canMESSAGE_BOX64: CAN message box 64 +* @param[in] msgBoxArbitVal (32 bit value): +* Bit 31 - Not used. +* Bit 30 - 0 - The 11-bit ("standard") identifier is used for this message +object. * 1 - The 29-bit ("extended") identifier is used for this +message object. * Bit 29 - 0 - Direction = Receive +* 1 - Direction = Transmit +* Bit 28:0 - Message Identifier. +* @return + +* +* This function changes the Identifier and other arbitration parameters of a CAN Message +Box. +* +*/ +/* SourceId : CAN_SourceId_027 */ +/* DesignId : CAN_DesignId_021 */ +/* Requirements : CONQ_CAN_SR40 */ +void canUpdateID( canBASE_t * node, uint32 messageBox, uint32 msgBoxArbitVal ) +{ + /** - Wait until IF2 is ready for use */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF2 for + * - Message direction - Read + * - Data Read + * - Clears NewDat bit in the message object. + */ + node->IF2CMD = 0xA0U; + /* Copy passed value into the arbitration register. */ + node->IF2ARB &= 0x80000000U; + node->IF2ARB |= ( msgBoxArbitVal & 0x7FFFFFFFU ); + + /** - Update message box number. */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF2NO = ( uint8 ) messageBox; + + /** - Wait until data are copied into IF2 */ + while( ( node->IF2STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ +} + +/** @fn uint32 canSendRemoteFrame(canBASE_t *node, uint32 messageBox) + * @brief Transmits a CAN Remote Frame. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @param[in] data Pointer to CAN TX data + * @return The function will return: + * - 0: When the setup of Send Remote Frame from message box wasn't successful + * - 1: When the setup of Send Remote Frame from message box was successful + * + * This function triggers Remote Frame Transmission from CAN message box. + * Note : Enable RTR must be set in the Message x Configuration in the GUI( x: 1 - 64) + * + */ +/* SourceId : CAN_SourceId_028 */ +/* DesignId : CAN_DesignId_022 */ +/* Requirements : CONQ_CAN_SR23 */ +uint32 canSendRemoteFrame( canBASE_t * node, uint32 messageBox ) +{ + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Request Transmission by setting TxRqst in message box */ + node->IF1CMD = ( uint8 ) 0x84U; + + /** - Trigger Remote Frame Transmit from message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + /** @note The function canInit has to be called before this function can be used.\n + * The user is responsible to initialize the message box. + */ + return success; +} + +/** @fn uint32 canFillMessageObjectData(canBASE_t *node, uint32 messageBox, const uint8 * + * data) + * @brief Fills the Message Object with the data but does not initiate transmission. + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return: + * - 0: When the Fill up of the TX message box wasn't successful + * - 1: When the Fill up of the TX message box was successful + * + * This function fills the Message Object with the data but does not initiate + * transmission. + * + */ +/* SourceId : CAN_SourceId_029 */ +/* DesignId : CAN_DesignId_023 */ +/* Requirements : CONQ_CAN_SR24 */ +uint32 canFillMessageObjectData( canBASE_t * node, uint32 messageBox, const uint8 * data ) +{ + uint32 i; + uint32 success = 0U; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /** - Check for pending message: + * - pending message, return 0 + * - no pending message, start new transmission + */ + if( ( node->TXRQx[ regIndex ] & bitIndex ) != 0U ) + { + success = 0U; + } + else + { + /** - Wait until IF1 is ready for use */ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware + * Status check for execution sequence" */ + while( ( node->IF1STAT & 0x80U ) == 0x80U ) + { + } /* Wait */ + + /** - Configure IF1 for + * - Message direction - Write + * - Data Update + */ + node->IF1CMD = 0x83U; + + /** - Copy TX data into IF1 */ + for( i = 0U; i < 8U; i++ ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ i ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#else + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + node->IF1DATx[ s_canByteOrder[ i ] ] = *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; +#endif + } + + /** - Copy TX data into message box */ + /*SAFETYMCUSW 93 S MR: 6.1,6.2,10.1,10.2,10.3,10.4 "LDRA Tool issue" */ + node->IF1NO = ( uint8 ) messageBox; + + success = 1U; + } + + return success; +} + +/** @fn uint32 canIsTxMessagePending(canBASE_t *node, uint32 messageBox) + * @brief Gets Tx message box transmission status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the tx request flag + * + * Checks to see if the Tx message box has a pending Tx request, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ + +/* USER CODE BEGIN (12) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_004 */ +/* DesignId : CAN_DesignId_004 */ +/* Requirements : CONQ_CAN_SR7 */ +uint32 canIsTxMessagePending( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->TXRQx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canIsRxMessageArrived(canBASE_t *node, uint32 messageBox) + * @brief Gets Rx message box reception status + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the Rx message box has pending Rx data, returns + * 0 is flag not set otherwise will return the Tx request flag itself. + */ + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_005 */ +/* DesignId : CAN_DesignId_005 */ +/* Requirements : CONQ_CAN_SR8 */ +uint32 canIsRxMessageArrived( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->NWDATx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canIsMessageBoxValid(canBASE_t *node, uint32 messageBox) + * @brief Checks if message box is valid + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] messageBox Message box number of CAN node: + * - canMESSAGE_BOX1: CAN message box 1 + * - canMESSAGE_BOXn: CAN message box n [n: 1-64] + * - canMESSAGE_BOX64: CAN message box 64 + * @return The function will return the new data flag + * + * Checks to see if the message box is valid for operation, returns + * 0 is flag not set otherwise will return the validation flag itself. + */ + +/* USER CODE BEGIN (18) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_006 */ +/* DesignId : CAN_DesignId_006 */ +/* Requirements : CONQ_CAN_SR9 */ +uint32 canIsMessageBoxValid( canBASE_t * node, uint32 messageBox ) +{ + uint32 flag; + uint32 regIndex = ( messageBox - 1U ) >> 5U; + uint32 bitIndex = 1U << ( ( messageBox - 1U ) & 0x1FU ); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Read Tx request register */ + flag = node->MSGVALx[ regIndex ] & bitIndex; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return flag; +} + +/** @fn uint32 canGetLastError(canBASE_t *node) + * @brief Gets last RX/TX-Error of CAN message traffic + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @return The function will return: + * - canERROR_OK (0): When no CAN error occurred + * - canERROR_STUFF (1): When a stuff error occurred on RX message + * - canERROR_FORMAT (2): When a form/format error occurred on RX message + * - canERROR_ACKNOWLEDGE (3): When a TX message wasn't acknowledged + * - canERROR_BIT1 (4): When a TX message monitored dominant level where + * recessive is expected + * - canERROR_BIT0 (5): When a TX message monitored recessive level where + * dominant is expected + * - canERROR_CRC (6): When a RX message has wrong CRC value + * - canERROR_NO (7): When no error occurred since last call of this function + * + * This function returns the last occurred error code of an RX or TX message, + * since the last call of this function. + * + */ + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_007 */ +/* DesignId : CAN_DesignId_007 */ +/* Requirements : CONQ_CAN_SR10 */ +uint32 canGetLastError( canBASE_t * node ) +{ + uint32 errorCode; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /** - Get last error code */ + errorCode = node->ES & 7U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return errorCode; +} + +/** @fn uint32 canGetErrorLevel(canBASE_t *node) + * @brief Gets error level of a CAN node + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @return The function will return: + * - canLEVEL_ACTIVE (0x00): When RX- and TX error counters are below 96 + * - canLEVEL_WARNING (0x40): When RX- or TX error counter are between 96 and + * 127 + * - canLEVEL_PASSIVE (0x20): When RX- or TX error counter are between 128 and + * 255 + * - canLEVEL_BUS_OFF (0x80): When RX- or TX error counter are above 255 + * + * This function returns the current error level of a CAN node. + * + */ + +/* USER CODE BEGIN (24) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_008 */ +/* DesignId : CAN_DesignId_008 */ +/* Requirements : CONQ_CAN_SR11 */ +uint32 canGetErrorLevel( canBASE_t * node ) +{ + uint32 errorLevel; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + /** - Get error level */ + errorLevel = node->ES & 0xE0U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + return errorLevel; +} + +/** @fn void canEnableErrorNotification(canBASE_t *node) + * @brief Enable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will enable the notification for the reaching the error levels warning, + * passive and bus off. + */ + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_009 */ +/* DesignId : CAN_DesignId_009 */ +/* Requirements : CONQ_CAN_SR12 */ +void canEnableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + node->CTL |= 8U; + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (30) */ +/* USER CODE END */ + +/** @fn void canEnableStatusChangeNotification(canBASE_t *node) + * @brief Enable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will enable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_030 */ +/* DesignId : CAN_DesignId_024 */ +/* Requirements : CONQ_CAN_SR25 */ +void canEnableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL |= 4U; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableStatusChangeNotification(canBASE_t *node) + * @brief Disable Status Change notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable the notification for the status change RxOK, TxOK, PDA, + * WakeupPnd Interrupt. + */ +/* SourceId : CAN_SourceId_031 */ +/* DesignId : CAN_DesignId_025 */ +/* Requirements : CONQ_CAN_SR26 */ +void canDisableStatusChangeNotification( canBASE_t * node ) +{ + node->CTL &= ~( uint32 ) ( 4U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableErrorNotification(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable the notification for the reaching the error levels + * warning, passive and bus off. + */ + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +/* SourceId : CAN_SourceId_010 */ +/* DesignId : CAN_DesignId_010 */ +/* Requirements : CONQ_CAN_SR13 */ +void canDisableErrorNotification( canBASE_t * node ) +{ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + node->CTL &= ~( uint32 ) ( 8U ); + + /** @note The function canInit has to be called before this function can be used. */ + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void canEnableloopback(canBASE_t *node, canloopBackType_t Loopbacktype) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] Loopbacktype Type of Loopback: + * - Internal_Lbk: Internal Loop Back + * - External_Lbk: External Loop Back + * - Internal_Silent_Lbk: Internal Loop Back with Silent mode. + * + * This function will enable can loopback mode + */ +/* SourceId : CAN_SourceId_011 */ +/* DesignId : CAN_DesignId_011 */ +/* Requirements : CONQ_CAN_SR21 */ +void canEnableloopback( canBASE_t * node, canloopBackType_t Loopbacktype ) +{ + /* Enter Test Mode */ + node->CTL |= ( uint32 ) ( ( uint32 ) 1U << 7U ); + + /* Configure Loopback */ + node->TEST |= ( uint32 ) Loopbacktype; + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canDisableloopback(canBASE_t *node) + * @brief Disable error notification + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * + * This function will disable can loopback mode + */ +/* SourceId : CAN_SourceId_012 */ +/* DesignId : CAN_DesignId_012 */ +/* Requirements : CONQ_CAN_SR22 */ +void canDisableloopback( canBASE_t * node ) +{ + node->TEST &= ~( uint32 ) ( 0x00000118U ); + + /* Exit Test Mode */ + node->CTL &= ~( uint32 ) ( ( uint32 ) 1U << 7U ); + + /** @note The function canInit has to be called before this function can be used. */ +} + +/** @fn void canIoSetDirection(canBASE_t *node,uint32 TxDir,uint32 RxDir) + * @brief Set Port Direction + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] TxDir - TX Pin direction + * @param[in] RxDir - RX Pin direction + * + * Set the direction of CAN pins at runtime when configured as IO pins. + */ +/* SourceId : CAN_SourceId_013 */ +/* DesignId : CAN_DesignId_013 */ +/* Requirements : CONQ_CAN_SR14 */ +void canIoSetDirection( canBASE_t * node, uint32 TxDir, uint32 RxDir ) +{ + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFBU ) | ( TxDir << 2U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFBU ) | ( RxDir << 2U ) ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void canIoSetPort(canBASE_t *node, uint32 TxValue, uint32 RxValue) + * @brief Write Port Value + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * - canREG4: CAN4 node pointer + * @param[in] TxValue - TX Pin value 0 or 1 + * @param[in] RxValue - RX Pin value 0 or 1 + * + * Writes a value to TX and RX pin of a given CAN module when configured as IO pins. + */ +/* SourceId : CAN_SourceId_014 */ +/* DesignId : CAN_DesignId_014 */ +/* Requirements : CONQ_CAN_SR15 */ +void canIoSetPort( canBASE_t * node, uint32 TxValue, uint32 RxValue ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + node->TIOC = ( ( node->TIOC & 0xFFFFFFFDU ) | ( TxValue << 1U ) ); + node->RIOC = ( ( node->RIOC & 0xFFFFFFFDU ) | ( RxValue << 1U ) ); + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn uint32 canIoTxGetBit(canBASE_t *node) + * @brief Read TX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the TX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_015 */ +/* DesignId : CAN_DesignId_015 */ +/* Requirements : CONQ_CAN_SR16 */ +uint32 canIoTxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + return ( node->TIOC & 1U ); +} + +/** @fn uint32 canIoRxGetBit(canBASE_t *node) + * @brief Read RX Bit + * @param[in] node Pointer to CAN node: + * - canREG1: CAN1 node pointer + * - canREG2: CAN2 node pointer + * - canREG3: CAN3 node pointer + * + * Reads a the current value from the RX pin of the given CAN port + */ +/* SourceId : CAN_SourceId_016 */ +/* DesignId : CAN_DesignId_016 */ +/* Requirements : CONQ_CAN_SR17 */ +uint32 canIoRxGetBit( canBASE_t * node ) +{ + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + + return ( node->RIOC & 1U ); +} + +/** @fn void can1GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_017 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR27 */ +void can1GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN1_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN1_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN1_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN1_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN1_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN1_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN1_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN1_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN1_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN1_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG1->CTL; + config_reg->CONFIG_ES = canREG1->ES; + config_reg->CONFIG_BTR = canREG1->BTR; + config_reg->CONFIG_TEST = canREG1->TEST; + config_reg->CONFIG_ABOTR = canREG1->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG1->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG1->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG1->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG1->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG1->TIOC; + config_reg->CONFIG_RIOC = canREG1->RIOC; + } +} +/** @fn void can2GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_018 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR28 */ +void can2GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN2_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN2_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN2_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN2_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN2_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN2_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN2_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN2_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN2_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN2_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG2->CTL; + config_reg->CONFIG_ES = canREG2->ES; + config_reg->CONFIG_BTR = canREG2->BTR; + config_reg->CONFIG_TEST = canREG2->TEST; + config_reg->CONFIG_ABOTR = canREG2->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG2->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG2->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG2->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG2->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG2->TIOC; + config_reg->CONFIG_RIOC = canREG2->RIOC; + } +} +/** @fn void can3GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_019 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR29 */ +void can3GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN3_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN3_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN3_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN3_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN3_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN3_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN3_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN3_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN3_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN3_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG3->CTL; + config_reg->CONFIG_ES = canREG3->ES; + config_reg->CONFIG_BTR = canREG3->BTR; + config_reg->CONFIG_TEST = canREG3->TEST; + config_reg->CONFIG_ABOTR = canREG3->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG3->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG3->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG3->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG3->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG3->TIOC; + config_reg->CONFIG_RIOC = canREG3->RIOC; + } +} + +/** @fn void can4GetConfigValue(can_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CAN4 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CAN_SourceId_032 */ +/* DesignId : CAN_DesignId_017 */ +/* Requirements : CONQ_CAN_SR30 */ +void can4GetConfigValue( can_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTL = CAN4_CTL_CONFIGVALUE; + config_reg->CONFIG_ES = CAN4_ES_CONFIGVALUE; + config_reg->CONFIG_BTR = CAN4_BTR_CONFIGVALUE; + config_reg->CONFIG_TEST = CAN4_TEST_CONFIGVALUE; + config_reg->CONFIG_ABOTR = CAN4_ABOTR_CONFIGVALUE; + config_reg->CONFIG_INTMUX0 = CAN4_INTMUX0_CONFIGVALUE; + config_reg->CONFIG_INTMUX1 = CAN4_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX2 = CAN4_INTMUX2_CONFIGVALUE; + config_reg->CONFIG_INTMUX3 = CAN4_INTMUX3_CONFIGVALUE; + config_reg->CONFIG_TIOC = CAN4_TIOC_CONFIGVALUE; + config_reg->CONFIG_RIOC = CAN4_RIOC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTL = canREG4->CTL; + config_reg->CONFIG_ES = canREG4->ES; + config_reg->CONFIG_BTR = canREG4->BTR; + config_reg->CONFIG_TEST = canREG4->TEST; + config_reg->CONFIG_ABOTR = canREG4->ABOTR; + config_reg->CONFIG_INTMUX0 = canREG4->INTMUXx[ 0 ]; + config_reg->CONFIG_INTMUX1 = canREG4->INTMUXx[ 1 ]; + config_reg->CONFIG_INTMUX2 = canREG4->INTMUXx[ 2 ]; + config_reg->CONFIG_INTMUX3 = canREG4->INTMUXx[ 3 ]; + config_reg->CONFIG_TIOC = canREG4->TIOC; + config_reg->CONFIG_RIOC = canREG4->RIOC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c new file mode 100644 index 00000000000..b8ebcd958af --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/crc.c @@ -0,0 +1,652 @@ +/** @file crc.c + * @brief CRC Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the CRC driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "crc.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void crcInit(void) + * @brief Initializes the crc Driver + * + * This function initializes the crc module. + */ +/* SourceId : CRC_SourceId_001 */ +/* DesignId : CRC_DesignId_001 */ +/* Requirements : CONQ_CRC_SR2 */ +void crcInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b CRC1 */ + /** - Reset PSA*/ + crcREG1->CTRL0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ); + + /** - Pulling PSA out of reset */ + crcREG1->CTRL0 = 0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG1->CTRL2 |= ( uint32 ) 0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG1->INTS = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG1->PCOUNT_REG1 = 0x00000000U; + crcREG1->PCOUNT_REG2 = 0x00000000U; + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG1->SCOUNT_REG1 = 0x00000000U; + crcREG1->SCOUNT_REG2 = 0x00000000U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG1->WDTOPLD1 = 0x00000000U; + crcREG1->WDTOPLD2 = 0x00000000U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG1->BCTOPLD1 = 0x00000000U; + crcREG1->BCTOPLD2 = 0x00000000U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG1->REGL1 = 0x00000000U; + crcREG1->REGL2 = 0x00000000U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG1->REGH1 = 0x00000000U; + crcREG1->REGH2 = 0x00000000U; + + /** - Setup the Channel mode */ + crcREG1->CTRL2 |= ( uint32 ) ( CRC_FULL_CPU ) + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ); + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b CRC2 */ + + /** - Reset PSA*/ + crcREG2->CTRL0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ); + + /** - Pulling PSA out of reset */ + crcREG2->CTRL0 = 0x00000000U; + + /** - Setup the Data trace for channel1 */ + crcREG2->CTRL2 |= ( uint32 ) 0U << 4U; + + /** - Set interrupt enable + * - Enable/Disable timeout + * - Enable/Disable underrun interrupt + * - Enable/Disable overrun interrupt + * - Enable/Disable CRC fail interrupt + * - Enable/Disable compression interrupt + */ + crcREG2->INTS = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U; + + /** - Setup pattern count preload register for channel 1 and channel 2*/ + crcREG2->PCOUNT_REG1 = 0U; + crcREG2->PCOUNT_REG2 = 0U; + + /** - Setup sector count preload register for channel 1 and channel 2*/ + crcREG2->SCOUNT_REG1 = 0U; + crcREG2->SCOUNT_REG2 = 0U; + + /** - Setup watchdog timeout for channel 1 and channel 2*/ + crcREG2->WDTOPLD1 = 0U; + crcREG2->WDTOPLD2 = 0U; + + /** - Setup block complete timeout for channel 1 and channel 2*/ + crcREG2->BCTOPLD1 = 0U; + crcREG2->BCTOPLD2 = 0U; + + /** - Setup CRC value low for channel 1 and channel 2*/ + crcREG2->REGL1 = 0U; + crcREG2->REGL2 = 0U; + + /** - Setup CRC value high for channel 1 and channel 2*/ + crcREG2->REGH1 = 0U; + crcREG2->REGH2 = 0U; + + /** - Setup the Channel mode */ + crcREG2->CTRL2 |= ( uint32 ) ( CRC_FULL_CPU ) + | ( uint32 ) ( ( uint32 ) CRC_FULL_CPU << 8U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void crcSendPowerDown(crcBASE_t *crc) + * @brief Send crc power down + * @param[in] crc - crc module base address + * + * Send crc power down signal to enter into sleep mode + */ +/* SourceId : CRC_SourceId_002 */ +/* DesignId : CRC_DesignId_002 */ +/* Requirements : CONQ_CRC_SR3 */ +void crcSendPowerDown( crcBASE_t * crc ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + crc->CTRL1 |= 0x00000001U; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/** @fn void crcSignGen(crcBASE_t *crc,crcModConfig_t *param) + * @brief set the mode specific parameters for signature generation + * @param[in] crc - crc module base address + * @param[in] param - structure holding mode specific parameters + * Generate CRC signature + */ +/* SourceId : CRC_SourceId_003 */ +/* DesignId : CRC_DesignId_003 */ +/* Requirements : CONQ_CRC_SR4 */ +void crcSignGen( crcBASE_t * crc, crcModConfig_t * param ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + uint32 i = 0U, psaSigx; + volatile uint64 *ptr64, *psaSigx_ptr64; + ptr64 = param->src_data_pat; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 439 S MR:11.3 "Pointer Manupulation required to find offset" + */ + psaSigx = ( uint32 ) ( &crc->PSA_SIGREGL1 ) + + ( ( uint32 ) ( param->crc_channel ) * 0x40U ); + psaSigx_ptr64 = ( uint64 * ) ( psaSigx ); + + if( param->mode == CRC_AUTO ) + { + /** -do a channel reset + * -clear all interrupts by reading offset register + * -set CRC FAIL interrupt + * -set the pattern count and sector count + * -HW trigger in AUTO mode for CRC register update + * -copy from memory location to CRC register using DMA + * -copy from memory to PSA signature register using DMA + * -frame or block transfer,auto init + * -compare with crc reference + * -do a channel reset + */ + } + else if( param->mode == CRC_SEMI_CPU ) + { + /* after DMA does the transfer,CPU is invoked by CC interrupt to do signature + * verification */ + } + else if( param->mode == CRC_FULL_CPU ) + { + for( i = 0U; i < param->data_length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *psaSigx_ptr64 = *ptr64; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + ptr64++; + } + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + } + else + { + /* Empty */ + } +} + +/** @fn void crcSetConfig(crcBASE_t *crc,crcConfig_t *param) + * @brief Set crc configurations + * @param[in] crc - crc module base address + * @param[in] param - structure for channel configuration + * Set Channel parameters + */ +/* SourceId : CRC_SourceId_004 */ +/* DesignId : CRC_DesignId_004 */ +/* Requirements : CONQ_CRC_SR5 */ +void crcSetConfig( crcBASE_t * crc, crcConfig_t * param ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + switch( param->crc_channel ) + { + case 0U: + crc->CTRL2 &= 0xFFFFFFFCU; + crc->CTRL0 |= 0x00000001U; + crc->CTRL0 &= 0xFFFFFFFEU; + crc->PCOUNT_REG1 = param->pcount; + crc->SCOUNT_REG1 = param->scount; + crc->WDTOPLD1 = param->wdg_preload; + crc->BCTOPLD1 = param->block_preload; + crc->CTRL2 |= param->mode; + break; + case 1U: + crc->CTRL2 &= 0xFFFFFCFFU; + crc->CTRL0 |= 0x00000100U; + crc->CTRL0 &= 0xFFFFFEFFU; + crc->PCOUNT_REG2 = param->pcount; + crc->SCOUNT_REG2 = param->scount; + crc->WDTOPLD2 = param->wdg_preload; + crc->BCTOPLD2 = param->block_preload; + crc->CTRL2 |= ( uint32 ) ( ( uint32 ) param->mode << 8U ); + break; + default: + break; + } + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/** @fn uint64 crcGetSectorSig(crcBASE_t *crc,uint32 channel) + * @brief get genearted sector signature + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get Sector signature value of selected channel + */ +/* SourceId : CRC_SourceId_005 */ +/* DesignId : CRC_DesignId_006 */ +/* Requirements : CONQ_CRC_SR7 */ +uint64 crcGetSectorSig( crcBASE_t * crc, uint32 channel ) +{ + uint64 status = 0U; + uint32 CRC_PSA_SECSIGREGH1 = crc->PSA_SECSIGREGH1; + uint32 CRC_PSA_SECSIGREGL1 = crc->PSA_SECSIGREGL1; + uint32 CRC_PSA_SECSIGREGH2 = crc->PSA_SECSIGREGH2; + uint32 CRC_PSA_SECSIGREGL2 = crc->PSA_SECSIGREGL2; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + switch( channel ) + { + case 0U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SECSIGREGL1 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SECSIGREGH1 ) ); + break; + case 1U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SECSIGREGL2 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SECSIGREGH2 ) ); + break; + default: + break; + } + return status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetFailedSector(crcBASE_t *crc,uint32 channel) + * @brief get failed sector details + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get Failed Sector value of selected channel + */ +/* SourceId : CRC_SourceId_006 */ +/* DesignId : CRC_DesignId_007 */ +/* Requirements : CONQ_CRC_SR8 */ +uint32 crcGetFailedSector( crcBASE_t * crc, uint32 channel ) +{ + uint32 sector = 0U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + switch( channel ) + { + case 0U: + sector = crc->CURSEC_REG1; + break; + case 1U: + sector = crc->CURSEC_REG2; + break; + default: + break; + } + return sector; + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetIntrPend(crcBASE_t *crc,uint32 channel) + * @brief get highest priority interrupt pending + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * + * Get pending Interrupts of selected channel + */ +/* SourceId : CRC_SourceId_007 */ +/* DesignId : CRC_DesignId_008 */ +/* Requirements : CONQ_CRC_SR9 */ +uint32 crcGetIntrPend( crcBASE_t * crc, uint32 channel ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + return crc->INT_OFFSET_REG; + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void crcChannelReset(crcBASE_t *crc,uint32 channel) + * @brief Reset the channel configurations + * @param[in] crc - crc module base address + * @param[in] channel-crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Reset configurations of the selected channels. + */ +/* SourceId : CRC_SourceId_008 */ +/* DesignId : CRC_DesignId_009 */ +/* Requirements : CONQ_CRC_SR10 */ +void crcChannelReset( crcBASE_t * crc, uint32 channel ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( channel == 0U ) + { + crc->CTRL0 |= ( uint32 ) ( ( uint32 ) 1U << 0U ); /** Reset the CRC channel */ + crc->CTRL0 &= ~( uint32 ) ( ( uint32 ) 1U << 0U ); /** Exit the reset */ + } + else if( channel == 1U ) + { + crc->CTRL0 |= ( uint32 ) ( ( uint32 ) 1U << 8U ); /** Reset the CRC channel */ + crc->CTRL0 &= ~( uint32 ) ( ( uint32 ) 1U << 8U ); /** Exit the reset */ + } + else + { + /** Empty */ + } + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn crcEnableNotification(crcBASE_t *crc, uint32 flags) + * @brief Enable interrupts + * @param[in] crc - crc module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * CRC_CH2_TO - channel3 timeout error, + * CRC_CH2_UR - channel3 underrun error, + * CRC_CH2_OR - channel3 overrun error, + * CRC_CH2_FAIL - channel3 crc error, + * CRC_CH2_CC - channel3 compression complete interrupt , + * CRC_CH1_TO - channel4 timeout error, + * CRC_CH1_UR - channel4 underrun error, + * CRC_CH1_OR - channel4 overrun error, + * CRC_CH1_FAIL - channel4 crc error, + * CRC_CH1_CC - channel4 compression complete interrupt + * + * Enable Notifications / Interrupts + */ +/* SourceId : CRC_SourceId_009 */ +/* DesignId : CRC_DesignId_010 */ +/* Requirements : CONQ_CRC_SR11 */ +void crcEnableNotification( crcBASE_t * crc, uint32 flags ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + crc->INTS = flags; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn crcDisableNotification(crcBASE_t *crc, uint32 flags) + * @brief Disable interrupts + * @param[in] crc - crc module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * CRC_CH2_TO - channel3 timeout error, + * CRC_CH2_UR - channel3 underrun error, + * CRC_CH2_OR - channel3 overrun error, + * CRC_CH2_FAIL - channel3 crc error, + * CRC_CH2_CC - channel3 compression complete interrupt , + * CRC_CH1_TO - channel4 timeout error, + * CRC_CH1_UR - channel4 underrun error, + * CRC_CH1_OR - channel4 overrun error, + * CRC_CH1_FAIL - channel4 crc error, + * CRC_CH1_CC - channel4 compression complete interrupt + * + * Disable Notifications / Interrupts + */ +/* SourceId : CRC_SourceId_010 */ +/* DesignId : CRC_DesignId_011 */ +/* Requirements : CONQ_CRC_SR12 */ +void crcDisableNotification( crcBASE_t * crc, uint32 flags ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + crc->INTR = flags; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/** @fn uint32 crcGetPSASig(crcBASE_t *crc,uint32 channel) + * @brief get genearted PSA signature used for FULL CPU mode + * @param[in] crc - crc module base address + * @param[in] channel - crc channel + * CRC_CH1 - channel1 + * CRC_CH2 - channel2 + * CRC_CH3 - channel3 + * CRC_CH4 - channel4 + * + * Get PSA signature used for FULL CPU mode of selected channel + */ +/* SourceId : CRC_SourceId_011 */ +/* DesignId : CRC_DesignId_005 */ +/* Requirements : CONQ_CRC_SR6 */ +uint64 crcGetPSASig( crcBASE_t * crc, uint32 channel ) +{ + uint64 status = 0U; + uint32 CRC_PSA_SIGREGH1 = crc->PSA_SIGREGH1; + uint32 CRC_PSA_SIGREGL1 = crc->PSA_SIGREGL1; + uint32 CRC_PSA_SIGREGH2 = crc->PSA_SIGREGH2; + uint32 CRC_PSA_SIGREGL2 = crc->PSA_SIGREGL2; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + switch( channel ) + { + case 0U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SIGREGL1 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SIGREGH1 ) ); + break; + case 1U: + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( uint64 ) ( CRC_PSA_SIGREGL2 ) << 32U ) + | ( uint64 ) ( CRC_PSA_SIGREGH2 ) ); + break; + default: + break; + } + return status; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void crc1GetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CRC1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CRC_SourceId_012 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements : CONQ_CRC_SR15 */ +void crc1GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRL0 = CRC1_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC1_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC1_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC1_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC1_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC1_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC1_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC1_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC1_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC1_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC1_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC1_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTRL0 = crcREG1->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG1->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG1->CTRL2; + config_reg->CONFIG_INTS = crcREG1->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG1->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG1->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG1->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG1->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG1->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG1->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG1->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG1->BCTOPLD2; + } +} + +/** @fn void crc2GetConfigValue(crc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the CRC2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : CRC_SourceId_013 */ +/* DesignId : CRC_DesignId_012 */ +/* Requirements : CONQ_CRC_SR15 */ +void crc2GetConfigValue( crc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRL0 = CRC2_CTRL0_CONFIGVALUE; + config_reg->CONFIG_CTRL1 = CRC2_CTRL1_CONFIGVALUE; + config_reg->CONFIG_CTRL2 = CRC2_CTRL2_CONFIGVALUE; + config_reg->CONFIG_INTS = CRC2_INTS_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG1 = CRC2_PCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG1 = CRC2_SCOUNT_REG1_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD1 = CRC2_WDTOPLD1_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD1 = CRC2_BCTOPLD1_CONFIGVALUE; + config_reg->CONFIG_PCOUNT_REG2 = CRC2_PCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_SCOUNT_REG2 = CRC2_SCOUNT_REG2_CONFIGVALUE; + config_reg->CONFIG_WDTOPLD2 = CRC2_WDTOPLD2_CONFIGVALUE; + config_reg->CONFIG_BCTOPLD2 = CRC2_BCTOPLD2_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_CTRL0 = crcREG2->CTRL0; + config_reg->CONFIG_CTRL1 = crcREG2->CTRL1; + config_reg->CONFIG_CTRL2 = crcREG2->CTRL2; + config_reg->CONFIG_INTS = crcREG2->INTS; + config_reg->CONFIG_PCOUNT_REG1 = crcREG2->PCOUNT_REG1; + config_reg->CONFIG_SCOUNT_REG1 = crcREG2->SCOUNT_REG1; + config_reg->CONFIG_WDTOPLD1 = crcREG2->WDTOPLD1; + config_reg->CONFIG_BCTOPLD1 = crcREG2->BCTOPLD1; + config_reg->CONFIG_PCOUNT_REG2 = crcREG2->PCOUNT_REG2; + config_reg->CONFIG_SCOUNT_REG2 = crcREG2->SCOUNT_REG2; + config_reg->CONFIG_WDTOPLD2 = crcREG2->WDTOPLD2; + config_reg->CONFIG_BCTOPLD2 = crcREG2->BCTOPLD2; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S new file mode 100644 index 00000000000..03969b31d23 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dabort.S @@ -0,0 +1,164 @@ +/*-------------------------------------------------------------------------- + dabort.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +--------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + + +/*-------------------------------------------------------------------------------*/ +@ Run Memory Test + + .extern custom_dabort + .extern vHandleMemoryFault + .weak _dabort + .type _dabort, %function + +_dabort: + stmfd r13!, {r0 - r12, lr}@ push registers and link register on to stack + ldr r12, esmsr3 @ ESM Group3 status register + ldr r0, [r12] + tst r0, #0x8 @ check if bit 3 is set, this indicates uncorrectable ECC error on B0TCM + bne ramErrorFound + tst r0, #0x20 @ check if bit 5 is set, this indicates uncorrectable ECC error on B1TCM + bne ramErrorFound2 + +noRAMerror: + tst r0, #0x80 @ check if bit 7 is set, this indicates uncorrectable ECC error on ATCM + bne flashErrorFound + +/* Create a Exception Fault Stack similiar to the way it is created by the ARMvM + * architecture. The auto-pushed exception stack will contain: + * +-------+-----+----------+----------+------+ + * | R0-R3 | R12 | LR (R14) | PC (R15) | CPSR | + * +-------+-----+----------+----------+------+ + * + * <-------><----><---------><---------><-----> + * 4 1 1 1 1 +*/ +MemManage_Handler: + /* Pop the pushed values so we can re-do the stack the way we need it to be */ + LDMFD R13!, {R0 - R12, LR} + /* Abort exceptions increment the LR 0x8 after the fault-inducing instruction */ + SUB LR, #0x8 + + SRSDB SP!, #0x17 /* Save the pre-exception PC and CPSR */ + STMDB SP, { R0-R3, R12, LR }^ /* Save the user R0-R3, R12, and LR */ + SUB SP, SP, #0x18 /* Can't auto-increment SP with ^ operator */ + /* Need the SP in R0 */ + MOV R0, SP + + POP { R0-R3, R12, LR } /* Pop the original values off the stack */ + /* Return to the next instruction after the fault was generated */ + RFEIA SP! + +ramErrorFound: + ldr r1, ramctrl @ RAM control register for B0TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x08 + str r2, [r12] @ clear ESM group3 channel3 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + +ramErrorFound2: + ldr r1, ram2ctrl @ RAM control register for B1TCM TCRAMW + ldr r2, [r1] + tst r2, #0x100 @ check if bit 8 is set in RAMCTRL, this indicates ECC memory write is enabled + beq ramErrorReal + mov r2, #0x20 + str r2, [r1, #0x10] @ clear RAM error status register + + mov r2, #0x20 + str r2, [r12] @ clear ESM group3 flags channel5 flag for uncorrectable RAM ECC errors + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +ramErrorReal: + b ramErrorReal @ branch here forever as continuing operation is not recommended + +flashErrorFound: + ldr r1, flashbase + ldr r2, [r1, #0x6C] @ read FDIAGCTRL register + + mov r2, r2, lsr #16 + tst r2, #5 @ check if bits 19:16 are 5, this indicates diagnostic mode is enabled + beq flashErrorReal + mov r2, #1 + mov r2, r2, lsl #8 + + str r2, [r1, #0x1C] @ clear FEDACSTATUS error flag + + mov r2, #0x80 + str r2, [r12] @ clear ESM group3 flag for uncorrectable flash ECC error + mov r2, #5 + str r2, [r12, #0x18] @ The nERROR pin will become inactive once the LTC counter expires + + ldmfd r13!, {r0 - r12, lr} + subs pc, lr, #4 @ branch to instruction after the one that caused the abort + @ this is the case because the data abort was caused intentionally + @ and we do not want to cause the same data abort again. + + +flashErrorReal: + b flashErrorReal @ branch here forever as continuing operation is not recommended + +esmsr3: .word 0xFFFFF520 +ramctrl: .word 0xFFFFF800 +ram2ctrl: .word 0xFFFFF900 +ram1errstat: .word 0xFFFFF810 +ram2errstat: .word 0xFFFFF910 +flashbase: .word 0xFFF87000 + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c new file mode 100644 index 00000000000..4498fab0615 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/dcc.c @@ -0,0 +1,455 @@ +/** @file dcc.c + * @brief DCC Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "dcc.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : DCC_SourceId_001 */ +/* DesignId : DCC_DesignId_001 */ +/* Requirements : CONQ_DCC_SR4 */ +/** @fn void dccInit(void) + * @brief Initializes the DCC Driver + * + * This function initializes the DCC module. + */ +void dccInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b DCC1 */ + + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 39204U; + + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 792U; + + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 742500U; + + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) DCC1_CNT1_PLL1; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable / Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0xAU << 4U ) | /** Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0xAU << 12U ); /** Done Interrupt */ + + /** @b initialize @b DCC2 */ + + /** DCC2 Clock0 Counter Seed value configuration */ + dccREG2->CNT0SEED = 0U; + + /** DCC2 Clock0 Valid Counter Seed value configuration */ + dccREG2->VALID0SEED = 0U; + + /** DCC2 Clock1 Counter Seed value configuration */ + dccREG2->CNT1SEED = 0U; + + /** DCC2 Clock1 Source 1 Select */ + dccREG2->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | /** DCC Enable Key */ + ( uint32 ) DCC2_CNT1_VCLK; /** DCC2 Clock Source 1 */ + + dccREG2->CNT0CLKSRC = ( uint32 ) DCC2_CNT0_OSCIN; /** DCC2 Clock Source 0 */ + + /** DCC2 Global Control register configuration */ + dccREG2->GCTRL = ( uint32 ) 0xAU | /** Enable DCC2 */ + ( uint32 ) ( ( uint32 ) 0xAU << 4U ) | /** Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0x5U << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0xAU << 12U ); /** Done Interrupt */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_002 */ +/* DesignId : DCC_DesignId_002 */ +/* Requirements : CONQ_DCC_SR5 */ +/** @fn void dccSetCounter0Seed(dccBASE_t *dcc, uint32 cnt0seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0seed - Clock Source 0 Counter seed value + * + * This function sets the seed value for Clock source 0 counter. + * + */ +void dccSetCounter0Seed( dccBASE_t * dcc, uint32 cnt0seed ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + dcc->CNT0SEED = cnt0seed; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_003 */ +/* DesignId : DCC_DesignId_003 */ +/* Requirements : CONQ_DCC_SR6 */ +/** @fn void dccSetTolerance(dccBASE_t *dcc, uint32 valid0seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] valid0seed - Clock Source 0 Counter tolerance value + * + * This function sets the seed value for Clock source 0 tolerance or + * valid counter. + * + */ +void dccSetTolerance( dccBASE_t * dcc, uint32 valid0seed ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + dcc->VALID0SEED = valid0seed; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_004 */ +/* DesignId : DCC_DesignId_004 */ +/* Requirements : CONQ_DCC_SR7 */ +/** @fn void dccSetCounter1Seed(dccBASE_t *dcc, uint32 cnt1seed) + * @brief Set dcc Clock source 1 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt1seed - Clock Source 1 Counter seed value + * + * This function sets the seed value for Clock source 1 counter. + * + */ +void dccSetCounter1Seed( dccBASE_t * dcc, uint32 cnt1seed ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + dcc->CNT1SEED = cnt1seed; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_005 */ +/* DesignId : DCC_DesignId_005 */ +/* Requirements : CONQ_DCC_SR8 */ +/** @fn void dccSetSeed(dccBASE_t *dcc, uint32 cnt0seed, uint32 valid0seed, uint32 + * cnt1seed) + * @brief Set dcc Clock source 0 counter seed value + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0seed - Clock Source 0 Counter seed value. + * @param[in] valid0seed - Clock Source 0 Counter tolerance value. + * @param[in] cnt1seed - Clock Source 1 Counter seed value. + * + * This function sets the seed value for clock source 0, clock source 1 + * and tolerance counter. + * + */ +void dccSetSeed( dccBASE_t * dcc, uint32 cnt0seed, uint32 valid0seed, uint32 cnt1seed ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + dcc->CNT0SEED = cnt0seed; + dcc->VALID0SEED = valid0seed; + dcc->CNT1SEED = cnt1seed; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_006 */ +/* DesignId : DCC_DesignId_006 */ +/* Requirements : CONQ_DCC_SR9 */ +/** @fn void dccSelectClockSource(dccBASE_t *dcc, uint32 cnt0_Clock_Source, uint32 + * cnt1_Clock_Source) + * @brief Set dcc counter Clock sources + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] cnt0_Clock_Source - Clock source for counter 0. + * @param[in] cnt1_Clock_Source - Clock source for counter 1. + * + * This function sets the dcc counter 0 and counter 1 clock sources. + * DCC must be disabled using dccDisable API before calling this + * function. + */ +void dccSelectClockSource( dccBASE_t * dcc, + uint32 cnt0_Clock_Source, + uint32 cnt1_Clock_Source ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + dcc->CNT1CLKSRC = ( ( uint32 ) ( ( uint32 ) 0xAU << 12U ) | /** DCC Enable Key */ + ( uint32 ) ( cnt1_Clock_Source + & 0x0000000FU ) ); /* Configure Clock source 1 */ + dcc->CNT0CLKSRC = cnt0_Clock_Source; /* Configure Clock source 0 */ + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_007 */ +/* DesignId : DCC_DesignId_007 */ +/* Requirements : CONQ_DCC_SR10 */ +/** @fn void dccEnable(dccBASE_t *dcc) + * @brief Enable dcc module to begin counting + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * This function enables the dcc counters to begin counting. + * + */ +void dccEnable( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( dcc->GCTRL & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_008 */ +/* DesignId : DCC_DesignId_008 */ +/* Requirements : CONQ_DCC_SR21 */ +/** @fn void dccDisable(dccBASE_t *dcc) + * @brief Make selected dcc module to stop counting + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * This function stops the dcc counters from counting. + * + */ +void dccDisable( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( dcc->GCTRL & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_009 */ +/* DesignId : DCC_DesignId_009 */ +/* Requirements : CONQ_DCC_SR12 */ +/** @fn uint32 dccGetErrStatus(dccBASE_t *dcc) + * @brief Get error status from selected dcc module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * + * @return The Error status of selected dcc module + * + * Returns the error status of selected dcc module. + * + */ +uint32 dccGetErrStatus( dccBASE_t * dcc ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + return ( dcc->STAT & 0x00000001U ); +} + +/* SourceId : DCC_SourceId_010 */ +/* DesignId : DCC_DesignId_010 */ +/* Requirements : CONQ_DCC_SR13 */ +/** @fn void dccEnableNotification(dccBASE_t *dcc, uint32 notification) + * @brief Enable notification of selected DCC module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] notification Select notification of DCC module: + * - dccNOTIFICATION_DONE: DCC DONE notification + * - dccNOTIFICATION_ERROR: DCC ERROR notification + * + * This function will enable the selected notification of a DCC module. + * It is possible to enable multiple notifications masked. + */ + +void dccEnableNotification( dccBASE_t * dcc, uint32 notification ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( ( dcc->GCTRL & 0xFFFF0F0FU ) | notification ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_011 */ +/* DesignId : DCC_DesignId_011 */ +/* Requirements : CONQ_DCC_SR14 */ +/** @fn void dccDisableNotification(dccBASE_t *dcc, uint32 notification) + * @brief Disable notification of selected DCC module + * @param[in] dcc Pointer to DCC module: + * - dccREG1: DCC1 module pointer + * - dccREG2: DCC2 module pointer + * @param[in] notification Select notification of DCC module: + * - dccNOTIFICATION_DONE: DCC DONE notification + * - dccNOTIFICATION_ERROR: DCC ERROR notification + * + * This function will enable the selected notification of a DCC module. + * It is possible to enable multiple notifications masked. + */ + +void dccDisableNotification( dccBASE_t * dcc, uint32 notification ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + dcc->GCTRL = ( ( dcc->GCTRL & 0xFFFF0F0FU ) | ( ( ~notification ) & 0x0000F0F0U ) ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : DCC_SourceId_012 */ +/* DesignId : DCC_DesignId_012 */ +/* Requirements : CONQ_DCC_SR18 */ +/** @fn void dcc1GetConfigValue(dcc_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void dcc1GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCTRL = DCC1_GCTRL_CONFIGVALUE; + config_reg->CONFIG_CNT0SEED = DCC1_CNT0SEED_CONFIGVALUE; + config_reg->CONFIG_VALID0SEED = DCC1_VALID0SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1SEED = DCC1_CNT1SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1CLKSRC = DCC1_CNT1CLKSRC_CONFIGVALUE; + config_reg->CONFIG_CNT0CLKSRC = DCC1_CNT0CLKSRC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + config_reg->CONFIG_GCTRL = dccREG1->GCTRL; + config_reg->CONFIG_CNT0SEED = dccREG1->CNT0SEED; + config_reg->CONFIG_VALID0SEED = dccREG1->VALID0SEED; + config_reg->CONFIG_CNT1SEED = dccREG1->CNT1SEED; + config_reg->CONFIG_CNT1CLKSRC = dccREG1->CNT1CLKSRC; + config_reg->CONFIG_CNT0CLKSRC = dccREG1->CNT0CLKSRC; + } +} + +/* SourceId : DCC_SourceId_013 */ +/* DesignId : DCC_DesignId_012 */ +/* Requirements : CONQ_DCC_SR19 */ +/** @fn void dcc2GetConfigValue(rti_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void dcc2GetConfigValue( dcc_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCTRL = DCC2_GCTRL_CONFIGVALUE; + config_reg->CONFIG_CNT0SEED = DCC2_CNT0SEED_CONFIGVALUE; + config_reg->CONFIG_VALID0SEED = DCC2_VALID0SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1SEED = DCC2_CNT1SEED_CONFIGVALUE; + config_reg->CONFIG_CNT1CLKSRC = DCC2_CNT1CLKSRC_CONFIGVALUE; + config_reg->CONFIG_CNT0CLKSRC = DCC2_CNT0CLKSRC_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Hardware status bit read check" */ + config_reg->CONFIG_GCTRL = dccREG2->GCTRL; + config_reg->CONFIG_CNT0SEED = dccREG2->CNT0SEED; + config_reg->CONFIG_VALID0SEED = dccREG2->VALID0SEED; + config_reg->CONFIG_CNT1SEED = dccREG2->CNT1SEED; + config_reg->CONFIG_CNT1CLKSRC = dccREG2->CNT1CLKSRC; + config_reg->CONFIG_CNT0CLKSRC = dccREG2->CNT0CLKSRC; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c new file mode 100644 index 00000000000..b5507af5a21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/ecap.c @@ -0,0 +1,1062 @@ +/** @file ecap.c + * @brief ECAP Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ECAP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "ecap.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void ecapInit(void) + * @brief Initializes the eCAP Driver + * + * This function initializes the eCAP module. + */ +/* SourceId : ECAP_SourceId_001 */ +/* DesignId : ECAP_DesignId_001 */ +/* Requirements : CONQ_ECAP_SR2 */ +void ecapInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** @b initialize @b ECAP1 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG1 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG1->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG1->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP2 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG2 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG2->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG2->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP3 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG3 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG3->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG3->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP4 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG4 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG4->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG4->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP5 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG5 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG5->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG5->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ + + /** @b initialize @b ECAP6 */ + + /** - Setup control register 1 + * - Set polarity and reset enable for Capture Events 1-4 + * - Enable/Disable loading on a capture event + * - Setup Event Filter prescale + */ + ecapREG6 + ->ECCTL1 = ( ( uint16 ) ( ( uint16 ) RISING_EDGE << 0U ) /* Capture Event 1 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 1U ) /* Counter Reset on + Capture Event 1 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 2U ) /* Capture Event 2 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 3U ) /* Counter Reset on + Capture Event 2 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 4U ) /* Capture Event 3 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 5U ) /* Counter Reset on + Capture Event 3 */ + | ( uint16 ) ( ( uint16 ) RISING_EDGE << 6U ) /* Capture Event 4 + Polarity */ + | ( uint16 ) ( ( uint16 ) RESET_DISABLE << 7U ) /* Counter Reset on + Capture Event 4 */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* Enable/Disable loading on + a capture event */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) ); /* Setup Event Filter + prescale */ + + /** - Setup control register 2 + * - Set operating mode + * - Set Stop/Wrap after capture + */ + ecapREG6->ECCTL2 = ( uint16 ) ( ( uint16 ) ONE_SHOT << 0U ) /* Capture Mode */ + | ( uint16 ) ( ( uint16 ) CAPTURE_EVENT1 << 1U ) /* Stop/Wrap value + */ + | ( uint16 ) ( ( uint16 ) 0U << 9U ) /* Enable/Disable APWM mode */ + | ( uint16 ) 0x00000010U; /* Start counter */ + + /** - Set interrupt enable */ + ecapREG6->ECEINT = 0x0000U /* Enable/Disable Capture Event 1 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 2 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 3 Interrupt */ + | 0x0000U /* Enable/Disable Capture Event 4 Interrupt */ + | 0x0000U /* Enable/Disable counter Overflow Interrupt */ + | 0x0000U /* Enable/Disable Period Equal Interrupt */ + | 0x0000U; /* Enable/Disable Compare Equal Interrupt */ +} + +/** @fn void ecapSetCounter(ecapBASE_t *ecap, uint32 value) + * @brief Set Time-Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] value 16-bit Counter value + * + * This function sets the Time-Stamp Counter register + */ +/* SourceId : ECAP_SourceId_002 */ +/* DesignId : ECAP_DesignId_002 */ +/* Requirements : CONQ_ECAP_SR3 */ +void ecapSetCounter( ecapBASE_t * ecap, uint32 value ) +{ + ecap->TSCTR = value; +} + +/** @fn void ecapEnableCounterLoadOnSync(ecapBASE_t *ecap, uint32 phase) + * @brief Enable counter register load from phase register when a sync event occurs + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] phase Counter value to be loaded when a sync event occurs + * + * This function enables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_003 */ +/* DesignId : ECAP_DesignId_003 */ +/* Requirements : CONQ_ECAP_SR6 */ +void ecapEnableCounterLoadOnSync( ecapBASE_t * ecap, uint32 phase ) +{ + ecap->ECCTL2 |= 0x0020U; + ecap->CTRPHS = phase; +} + +/** @fn void ecapDisableCounterLoadOnSync(ecapBASE_t *ecap) + * @brief Disable counter register load from phase register when a sync event occurs + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_004 */ +/* DesignId : ECAP_DesignId_004 */ +/* Requirements : CONQ_ECAP_SR7 */ +void ecapDisableCounterLoadOnSync( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0020U; +} + +/** @fn void ecapSetEventPrescaler(ecapBASE_t *ecap, ecapPrescale_t prescale) + * @brief Set Event prescaler + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] prescale Event Filter prescale select + * (ecapPrescale_By_1..ecapPrescale_By_62) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ECAP_SourceId_005 */ +/* DesignId : ECAP_DesignId_005 */ +/* Requirements : CONQ_ECAP_SR8 */ +void ecapSetEventPrescaler( ecapBASE_t * ecap, ecapPrescale_t prescale ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) 0x3E00U; + ecap->ECCTL1 |= ( uint16 ) prescale; +} + +/** @fn void ecapSetCaptureEvent1(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 1 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 1 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 1 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 1 + */ +/* SourceId : ECAP_SourceId_006 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent1( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 0U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 0U ); +} + +/** @fn void ecapSetCaptureEvent2(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 2 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 2 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 2 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 2 + */ +/* SourceId : ECAP_SourceId_007 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent2( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 2U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 2U ); +} + +/** @fn void ecapSetCaptureEvent3(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 3 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 3 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 3 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 3 + */ +/* SourceId : ECAP_SourceId_008 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent3( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 4U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 4U ); +} + +/** @fn void ecapSetCaptureEvent4(ecapBASE_t *ecap, ecapEdgePolarity_t edgePolarity, + * ecapReset_t resetenable) + * @brief Set Capture Event 4 + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] edgePolarity Capture Event 4 Polarity select + * - RISING_EDGE + * - FALLING_EDGE + * @param[in] resetenable Counter Reset on Capture Event 4 + * - RESET_ENABLE + * - RESET_DISABLE + * + * This function sets the polarity and reset enable for Capture event 4 + */ +/* SourceId : ECAP_SourceId_009 */ +/* DesignId : ECAP_DesignId_006 */ +/* Requirements : CONQ_ECAP_SR9 */ +void ecapSetCaptureEvent4( ecapBASE_t * ecap, + ecapEdgePolarity_t edgePolarity, + ecapReset_t resetenable ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) ( ( uint16 ) 0x3U << 6U ); + ecap->ECCTL1 |= ( uint16 ) ( ( ( uint16 ) edgePolarity + | ( uint16 ) ( ( uint16 ) resetenable << 1U ) ) + << 6U ); +} + +/** @fn void ecapSetCaptureMode(ecapBASE_t *ecap, ecapMode_t mode, ecapEvent_t event) + * @brief Set Capture mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] capMode Capture mode + * - CONTINUOUS + * - ONE_SHOT + * @param[in] event Stop/Wrap value + * - CAPTURE_EVENT1: Stop after Capture Event 1 in one-shot mode / + * Wrap after Capture Event 1 in continuous mode + * - CAPTURE_EVENT2: Stop after Capture Event 2 in one-shot mode / + * Wrap after Capture Event 2 in continuous mode. + * - CAPTURE_EVENT3: Stop after Capture Event 3 in one-shot mode / + * Wrap after Capture Event 3 in continuous mode. + * - CAPTURE_EVENT4: Stop after Capture Event 4 in one-shot mode / + * Wrap after Capture Event 4 in continuous mode. + * + * This function sets the capture mode and stop/wrap value + */ +/* SourceId : ECAP_SourceId_010 */ +/* DesignId : ECAP_DesignId_007 */ +/* Requirements : CONQ_ECAP_SR10 */ +void ecapSetCaptureMode( ecapBASE_t * ecap, ecapMode_t capMode, ecapEvent_t event ) +{ + ecap->ECCTL2 &= 0xFFF8U; + ecap->ECCTL2 |= ( ( uint16 ) ( ( uint16 ) event << 1U ) | ( uint16 ) capMode ); +} + +/** @fn void ecapEnableCapture(ecapBASE_t *ecap) + * @brief Enable Capture + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function enable loading of CAP1-4 registers on a capture event + */ +/* SourceId : ECAP_SourceId_011 */ +/* DesignId : ECAP_DesignId_008 */ +/* Requirements : CONQ_ECAP_SR11 */ +void ecapEnableCapture( ecapBASE_t * ecap ) +{ + ecap->ECCTL1 |= 0x0100U; +} + +/** @fn void ecapDisableCapture(ecapBASE_t *ecap) + * @brief Disable Capture + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disable loading of CAP1-4 registers on a capture event + */ +/* SourceId : ECAP_SourceId_012 */ +/* DesignId : ECAP_DesignId_009 */ +/* Requirements : CONQ_ECAP_SR12 */ +void ecapDisableCapture( ecapBASE_t * ecap ) +{ + ecap->ECCTL1 &= ( uint16 ) ~( uint16 ) 0x0100U; +} + +/** @fn void ecapStartCounter(ecapBASE_t *ecap) + * @brief Start Time Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function starts Time Stamp Counter + */ +/* SourceId : ECAP_SourceId_013 */ +/* DesignId : ECAP_DesignId_010 */ +/* Requirements : CONQ_ECAP_SR4 */ +void ecapStartCounter( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 |= 0x0010U; +} + +/** @fn void ecapStopCounter(ecapBASE_t *ecap)) + * @brief Stop Time Stamp Counter + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function stops Time Stamp Counter + */ +/* SourceId : ECAP_SourceId_014 */ +/* DesignId : ECAP_DesignId_011 */ +/* Requirements : CONQ_ECAP_SR5 */ +void ecapStopCounter( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0010U; +} + +/** @fn void ecapSetSyncOut(ecapBASE_t *ecap, ecapSyncOut_t syncOutSrc) + * @brief Set the source of Sync-out signal + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] syncOutSrc Sync-Out Select + * - SyncOut_SyncIn: Sync In used for Sync Out + * - SyncOut_CTRPRD: CTR = PRD used for Sync Out + * - SyncOut_None : Disables Sync Out + * + * This function sets the source of Sync-out signal + */ +/* SourceId : ECAP_SourceId_015 */ +/* DesignId : ECAP_DesignId_012 */ +/* Requirements : CONQ_ECAP_SR13 */ +void ecapSetSyncOut( ecapBASE_t * ecap, ecapSyncOut_t syncOutSrc ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x00C0U; + ecap->ECCTL2 |= syncOutSrc; +} + +/** @fn void ecapEnableAPWMmode(ecapBASE_t *ecap, ecapAPWMPolarity_t pwmPolarity, uint16 + * period, uint16 duty) + * @brief Enable APWM mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] pwmPolarity APWM output polarity select + * - ACTIVE_HIGH + * - ACTIVE_LOW + * @param[in] period APWM period (in terms of ticks) + * @param[in] duty APWM duty (in terms of ticks) + * + * This function enables and sets APWM mode + */ +/* SourceId : ECAP_SourceId_016 */ +/* DesignId : ECAP_DesignId_013 */ +/* Requirements : CONQ_ECAP_SR14 */ +void ecapEnableAPWMmode( ecapBASE_t * ecap, + ecapAPWMPolarity_t pwmPolarity, + uint32 period, + uint32 duty ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0400U; + ecap->ECCTL2 |= ( uint16 ) ( ( uint16 ) pwmPolarity << 10U ) + | ( uint16 ) ( ( uint16 ) 1U << 9U ); + ecap->CAP1 = period - 1U; + ecap->CAP2 = duty; +} + +/** @fn void ecapDisableAPWMMode(ecapBASE_t *ecap) + * @brief Disable APWM mode + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function disables APWM mode + */ +/* SourceId : ECAP_SourceId_017 */ +/* DesignId : ECAP_DesignId_014 */ +/* Requirements : CONQ_ECAP_SR15 */ +void ecapDisableAPWMMode( ecapBASE_t * ecap ) +{ + ecap->ECCTL2 &= ( uint16 ) ~( uint16 ) 0x0200U; +} + +/** @fn void ecapEnableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) + * @brief Enable eCAP interrupt sources + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] interrupts eCAP interrupt sources + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function enables eCAP interrupt sources + */ +/* SourceId : ECAP_SourceId_018 */ +/* DesignId : ECAP_DesignId_015 */ +/* Requirements : CONQ_ECAP_SR16 */ +void ecapEnableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ) +{ + ecap->ECEINT |= interrupts; +} + +/** @fn void ecapDisableInterrupt(ecapBASE_t *ecap, ecapInterrupt_t interrupts) + * @brief Disables eCAP interrupt sources + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] interrupts eCAP interrupt sources + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function disables eCAP interrupt sources + */ +/* SourceId : ECAP_SourceId_019 */ +/* DesignId : ECAP_DesignId_016 */ +/* Requirements : CONQ_ECAP_SR17 */ +void ecapDisableInterrupt( ecapBASE_t * ecap, ecapInterrupt_t interrupts ) +{ + ecap->ECEINT &= ( uint16 ) ~( uint16 ) interrupts; +} + +/** @fn uint16 ecapGetEventStatus(ecapBASE_t *ecap, ecapInterrupt_t events) + * @brief Return Event status + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] events eCAP events + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_Global : Denotes Capture global interrupt + * - ecapInt_All : Denotes All interrupts + * @return Event status + * + * This function returns the event status + */ +/* SourceId : ECAP_SourceId_020 */ +/* DesignId : ECAP_DesignId_017 */ +/* Requirements : CONQ_ECAP_SR18 */ +uint16 ecapGetEventStatus( ecapBASE_t * ecap, ecapInterrupt_t events ) +{ + return ( ecap->ECFLG & events ); +} + +/** @fn void ecapClearFlag(ecapBASE_t *ecap, ecapInterrupt_t events) + * @brief Clear Event status + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * @param[in] events eCAP events + * - ecapInt_CTR_CMP: Denotes CTR = CMP interrupt + * - ecapInt_CTR_PRD: Denotes CTR = PRD interrupt + * - ecapInt_CTR_OVF: Denotes CTROVF interrupt + * - ecapInt_CEVT4 : Denotes CEVT4 interrupt + * - ecapInt_CEVT3 : Denotes CEVT3 interrupt + * - ecapInt_CEVT2 : Denotes CEVT2 interrupt + * - ecapInt_CEVT1 : Denotes CEVT1 interrupt + * - ecapInt_Global : Denotes Capture global interrupt + * - ecapInt_All : Denotes All interrupts + * + * This function clears the event status + */ +/* SourceId : ECAP_SourceId_021 */ +/* DesignId : ECAP_DesignId_018 */ +/* Requirements : CONQ_ECAP_SR19 */ +void ecapClearFlag( ecapBASE_t * ecap, ecapInterrupt_t events ) +{ + ecap->ECCLR = events; +} + +/** @fn void uint32 ecapGetCAP1(ecapBASE_t *ecap) + * @brief Get CAP1 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 1 value + */ +/* SourceId : ECAP_SourceId_022 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP1( ecapBASE_t * ecap ) +{ + return ecap->CAP1; +} + +/** @fn void uint32 ecapGetCAP2(ecapBASE_t *ecap) + * @brief Get CAP2 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 2 value + */ +/* SourceId : ECAP_SourceId_023 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP2( ecapBASE_t * ecap ) +{ + return ecap->CAP2; +} + +/** @fn void uint32 ecapGetCAP3(ecapBASE_t *ecap) + * @brief Get CAP3 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 3 value + */ +/* SourceId : ECAP_SourceId_024 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP3( ecapBASE_t * ecap ) +{ + return ecap->CAP3; +} + +/** @fn void uint32 ecapGetCAP4(ecapBASE_t *ecap) + * @brief Get CAP4 value + * + * @param[in] ecap The capture (eCAP) object handle (ecapREG1..6) + * + * This function returns Capture 4 value + */ +/* SourceId : ECAP_SourceId_025 */ +/* DesignId : ECAP_DesignId_019 */ +/* Requirements : CONQ_ECAP_SR20 */ +uint32 ecapGetCAP4( ecapBASE_t * ecap ) +{ + return ecap->CAP4; +} + +/** @fn void ecap1GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_026 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap1GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP1_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP1_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP1_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP1_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG1->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG1->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG1->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG1->ECEINT; + } +} + +/** @fn void ecap2GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_027 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap2GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP2_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP2_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP2_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP2_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG2->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG2->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG2->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG2->ECEINT; + } +} + +/** @fn void ecap3GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_028 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap3GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP3_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP3_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP3_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP3_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG3->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG3->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG3->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG3->ECEINT; + } +} + +/** @fn void ecap4GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_029 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap4GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP4_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP4_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP4_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP4_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG4->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG4->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG4->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG4->ECEINT; + } +} + +/** @fn void ecap5GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_030 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap5GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP5_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP5_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP5_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP5_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG5->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG5->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG5->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG5->ECEINT; + } +} + +/** @fn void ecap6GetConfigValue(ecap_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ECAP_SourceId_031 */ +/* DesignId : ECAP_DesignId_020 */ +/* Requirements : CONQ_ECAP_SR21 */ +void ecap6GetConfigValue( ecap_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_CTRPHS = ECAP6_CTRPHS_CONFIGVALUE; + config_reg->CONFIG_ECCTL1 = ECAP6_ECCTL1_CONFIGVALUE; + config_reg->CONFIG_ECCTL2 = ECAP6_ECCTL2_CONFIGVALUE; + config_reg->CONFIG_ECEINT = ECAP6_ECEINT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_CTRPHS = ecapREG6->CTRPHS; + config_reg->CONFIG_ECCTL1 = ecapREG6->ECCTL1; + config_reg->CONFIG_ECCTL2 = ecapREG6->ECCTL2; + config_reg->CONFIG_ECEINT = ecapREG6->ECEINT; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c new file mode 100644 index 00000000000..fb35e4511fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emac.c @@ -0,0 +1,1965 @@ +/** + * \file emac.c + * + * \brief EMAC APIs. + * + * This file contains the device abstraction layer APIs for EMAC. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emac.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* Defining interface for all the emac instances */ +hdkif_t hdkif_data[ MAX_EMAC_INSTANCE ]; +/*SAFETYMCUSW 25 D MR:8.7 "Statically allocated memory needs to be available to + * entire application." */ +static uint8_t pbuf_array[ MAX_RX_PBUF_ALLOC ][ MAX_TRANSFER_UNIT ]; +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define EMAC_CONTROL_RESET ( 0x01U ) +#define EMAC_SOFT_RESET ( 0x01U ) +#define EMAC_MAX_HEADER_DESC ( 8U ) +#define EMAC_UNICAST_DISABLE ( 0xFFU ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Enables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_001 */ +/* DesignId : ETH_DesignId_001*/ +/* Requirements : CONQ_EMAC_SR9 */ +void EMACTxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_TXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnTXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the TXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Channel number for which the interrupt to be enabled in EMAC + *Control module \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_002 */ +/* DesignId : ETH_DesignId_002*/ +/* Requirements : CONQ_EMAC_SR10 */ +void EMACTxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnTXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Enables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be enabled. + * \param channel Channel number for which interrupt to be enabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_003 */ +/* DesignId : ETH_DesignId_003*/ +/* Requirements : CONQ_EMAC_SR11 */ +void EMACRxIntPulseEnable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXINTMASKSET ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + EMAC_CTRL_CnRXEN( ctrlCore ) ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables the RXPULSE Interrupt Generation. + * + * \param emacBase Base address of the EMAC Module registers. + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param ctrlCore Control core for which the interrupt to be disabled. + * \param channel Channel number for which interrupt to be disabled + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_004 */ +/* DesignId : ETH_DesignId_004*/ +/* Requirements : CONQ_EMAC_SR12 */ +void EMACRxIntPulseDisable( uint32 emacBase, + uint32 emacCtrlBase, + uint32 ctrlCore, + uint32 channel ) +{ + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) |= ( ( uint32 ) 1U << channel ); + + HWREG( emacCtrlBase + + EMAC_CTRL_CnRXEN( ctrlCore ) ) &= ( ~( ( uint32 ) 1U << channel ) ); +} +/** + * \brief This API sets the RMII speed. The RMII Speed can be 10 Mbps or + * 100 Mbps + * + * \param emacBase Base address of the EMAC Module registers. + * \param speed speed for setting. + * speed can take the following values. \n + * EMAC_RMIISPEED_10MBPS - 10 Mbps \n + * EMAC_RMIISPEED_100MBPS - 100 Mbps. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_005 */ +/* DesignId : ETH_DesignId_005*/ +/* Requirements : CONQ_EMAC_SR23 */ +void EMACRMIISpeedSet( uint32 emacBase, uint32 speed ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RMIISPEED ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= speed; +} +/* SourceId : ETH_SourceId_006 */ +/* DesignId : ETH_DesignId_006*/ +/* Requirements : CONQ_EMAC_SR21 */ +/** + * \brief This API set the GMII bit, RX and TX are enabled for receive and transmit. + * Note: This is not the API to enable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +void EMACMIIEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_GMIIEN; +} + +/** + * \brief This API clears the GMII bit, Rx and Tx are held in reset. + * Note: This is not the API to disable MII. + * \param emacBase Base address of the EMAC Module registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_007 */ +/* DesignId : ETH_DesignId_007*/ +/* Requirements : CONQ_EMAC_SR22 */ +void EMACMIIDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); +} + +/** + * \brief This API sets the duplex mode of operation(full/half) for MAC. + * + * \param emacBase Base address of the EMAC Module registers. + * \param duplexMode duplex mode of operation. + * duplexMode can take the following values. \n + * EMAC_DUPLEX_FULL - Full Duplex \n + * EMAC_DUPLEX_HALF - Half Duplex. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_008 */ +/* DesignId : ETH_DesignId_008*/ +/* Requirements : CONQ_EMAC_SR29 */ +void EMACDuplexSet( uint32 emacBase, uint32 duplexMode ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_FULLDUPLEX ); + + HWREG( emacBase + EMAC_MACCONTROL ) |= duplexMode; +} + +/** + * \brief API to enable the transmit in the TX Control Register + * After the transmit is enabled, any write to TXHDP of + * a channel will start transmission + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_009 */ +/* DesignId : ETH_DesignId_009*/ +/* Requirements : CONQ_EMAC_SR30 */ +void EMACTxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXEN; +} + +/** + * \brief API to disable the transmit in the TX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_010 */ +/* DesignId : ETH_DesignId_010*/ +/* Requirements : CONQ_EMAC_SR31 */ +void EMACTxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_TXCONTROL ) = EMAC_TXCONTROL_TXDIS; +} + +/** + * \brief API to enable the receive in the RX Control Register + * After the receive is enabled, and write to RXHDP of + * a channel, the data can be received in the destination + * specified by the corresponding RX buffer descriptor. + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_011*/ +/* DesignId : ETH_DesignId_011*/ +/* Requirements : CONQ_EMAC_SR32 */ +void EMACRxEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXEN; +} + +/** + * \brief API to disable the receive in the RX Control Register + * + * \param emacBase Base Address of the EMAC Module Registers. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_012*/ +/* DesignId : ETH_DesignId_012*/ +/* Requirements : CONQ_EMAC_SR33 */ +void EMACRxDisable( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXCONTROL ) = EMAC_RXCONTROL_RXDIS; +} + +/** + * \brief API to write the TX HDP register. If transmit is enabled, + * write to the TX HDP will immediately start transmission. + * The data will be taken from the buffer pointer of the TX buffer + * descriptor written to the TX HDP + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the TX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_013*/ +/* DesignId : ETH_DesignId_013*/ +/* Requirements : CONQ_EMAC_SR17 */ +void EMACTxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXHDP( channel ) ) = descHdr; +} + +/** + * \brief API to write the RX HDP register. If receive is enabled, + * write to the RX HDP will enable data reception to point to + * the corresponding RX buffer descriptor's buffer pointer. + * + * \param emacBase Base Address of the EMAC Module Registers.\n + * \param descHdr Address of the RX buffer descriptor + * \param channel Channel Number + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_014 */ +/* DesignId : ETH_DesignId_014*/ +/* Requirements : CONQ_EMAC_SR18 */ +void EMACRxHdrDescPtrWrite( uint32 emacBase, uint32 descHdr, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXHDP( channel ) ) = descHdr; +} + +/** + * \brief This API Initializes the EMAC and EMAC Control modules. The + * EMAC Control module is reset, the CPPI RAM is cleared. also, + * all the interrupts are disabled. This API does not enable any + * interrupt or operation of the EMAC. + * + * \param emacCtrlBase Base Address of the EMAC Control module + * registers.\n + * \param emacBase Base address of the EMAC module registers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_015 */ +/* DesignId : ETH_DesignId_015*/ +/* Requirements : CONQ_EMAC_SR1 */ +void EMACInit( uint32 emacCtrlBase, uint32 emacBase ) +{ + uint32 cnt; + + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + } /* Wait */ + + /* Reset the EMAC Module. This clears the CPPI RAM also */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + } /* Wait */ + + HWREG( emacBase + EMAC_MACCONTROL ) = 0U; + HWREG( emacBase + EMAC_RXCONTROL ) = 0U; + HWREG( emacBase + EMAC_TXCONTROL ) = 0U; + + /* Initialize all the header descriptor pointer registers */ + for( cnt = 0U; cnt < EMAC_MAX_HEADER_DESC; cnt++ ) + { + HWREG( emacBase + EMAC_RXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXHDP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_TXCP( cnt ) ) = 0U; + HWREG( emacBase + EMAC_RXFREEBUFFER( cnt ) ) = 0xFFU; + } + /* Clear the interrupt enable for all the channels */ + HWREG( emacBase + EMAC_TXINTMASKCLEAR ) = 0xFFU; + HWREG( emacBase + EMAC_RXINTMASKCLEAR ) = 0xFFU; + + HWREG( emacBase + EMAC_MACHASH1 ) = 0U; + HWREG( emacBase + EMAC_MACHASH2 ) = 0U; + + HWREG( emacBase + EMAC_RXBUFFEROFFSET ) = 0U; +} + +/** + * \brief Sets the MAC Address in MACSRCADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_016 */ +/* DesignId : ETH_DesignId_016*/ +/* Requirements : CONQ_EMAC_SR5 */ +void EMACMACSrcAddrSet( uint32 emacBase, uint8 macAddr[ 6 ] ) +{ + HWREG( emacBase + EMAC_MACSRCADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACSRCADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) ); +} + +/** + * \brief Sets the MAC Address in MACADDR registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param matchFilt Match or Filter + * \param macAddr Start address of a MAC address array. + * The array[0] shall be the LSB of the MAC address + * matchFilt can take the following values \n + * EMAC_MACADDR_NO_MATCH_NO_FILTER - Address is not used to match + * or filter incoming packet. \n + * EMAC_MACADDR_FILTER - Address is used to filter incoming packets \n + * EMAC_MACADDR_MATCH - Address is used to match incoming packets \n + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_017 */ +/* DesignId : ETH_DesignId_017*/ +/* Requirements : CONQ_EMAC_SR6 */ +void EMACMACAddrSet( uint32 emacBase, + uint32 channel, + uint8 macAddr[ 6 ], + uint32 matchFilt ) +{ + HWREG( emacBase + EMAC_MACINDEX ) = channel; + + HWREG( emacBase + EMAC_MACADDRHI ) = ( ( uint32 ) macAddr[ 5U ] + | ( ( uint32 ) macAddr[ 4U ] << 8U ) + | ( ( uint32 ) macAddr[ 3U ] << 16U ) + | ( ( uint32 ) macAddr[ 2U ] << 24U ) ); + HWREG( emacBase + EMAC_MACADDRLO ) = ( ( uint32 ) macAddr[ 1U ] + | ( ( uint32 ) macAddr[ 0U ] << 8U ) + | matchFilt | ( channel << 16U ) ); +} + +/** + * \brief Acknowledges an interrupt processed to the EMAC Control Core. + * + * \param emacBase Base Address of the EMAC module registers. + * \param eoiFlag Type of interrupt to acknowledge to the EMAC Control + * module. + * eoiFlag can take the following values \n + * EMAC_INT_CORE0_TX - Core 0 TX Interrupt + * EMAC_INT_CORE1_TX - Core 1 TX Interrupt + * EMAC_INT_CORE2_TX - Core 2 TX Interrupt + * EMAC_INT_CORE0_RX - Core 0 RX Interrupt + * EMAC_INT_CORE1_RX - Core 1 RX Interrupt + * EMAC_INT_CORE2_RX - Core 2 RX Interrupt + * \return None + * + **/ +/* SourceId : ETH_SourceId_018 */ +/* DesignId : ETH_DesignId_018*/ +/* Requirements : CONQ_EMAC_SR16 */ +void EMACCoreIntAck( uint32 emacBase, uint32 eoiFlag ) +{ + /* Acknowledge the EMAC Control Core */ + HWREG( emacBase + EMAC_MACEOIVECTOR ) = eoiFlag; +} + +/** + * \brief Writes the the TX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_019 */ +/* DesignId : ETH_DesignId_019*/ +/* Requirements : CONQ_EMAC_SR41 */ +void EMACTxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_TXCP( channel ) ) = comPtr; +} + +/** + * \brief Writes the the RX Completion Pointer for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param comPtr Completion Pointer Value to be written + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_020 */ +/* DesignId : ETH_DesignId_020*/ +/* Requirements : CONQ_EMAC_SR42 */ +void EMACRxCPWrite( uint32 emacBase, uint32 channel, uint32 comPtr ) +{ + HWREG( emacBase + EMAC_RXCP( channel ) ) = comPtr; +} + +/** + * \brief Enables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_021 */ +/* DesignId : ETH_DesignId_021*/ +/* Requirements : CONQ_EMAC_SR43 */ +void EMACRxBroadCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + + HWREG( + emacBase + + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXBROADEN + | ( ( uint32 ) channel + << ( uint32 ) EMAC_RXMBPENABLE_RXBROADCH_SHIFT ) ); +} + +/** + * \brief Disables a specific channel to receive broadcast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_022 */ +/* DesignId : ETH_DesignId_022*/ +/* Requirements : CONQ_EMAC_SR44 */ +void EMACRxBroadCastDisable( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADCH ); + /* Broadcast Frames are filtered. */ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXBROADEN ); +} + +/** + * \brief Enables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_023 */ +/* DesignId : ETH_DesignId_023*/ +/* Requirements : CONQ_EMAC_SR45 */ +void EMACRxMultiCastEnable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) |= ( ( uint32 ) EMAC_RXMBPENABLE_RXMULTEN + | ( channel ) ); +} + +/** + * \brief Disables a specific channel to receive multicast frames + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_024 */ +/* DesignId : ETH_DesignId_024*/ +/* Requirements : CONQ_EMAC_SR46 */ +void EMACRxMultiCastDisable( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTCH ); + + HWREG( emacBase + EMAC_RXMBPENABLE ) &= ( ~( uint32 ) EMAC_RXMBPENABLE_RXMULTEN ); +} + +/** + * \brief Enables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_025 */ +/* DesignId : ETH_DesignId_025*/ +/* Requirements : CONQ_EMAC_SR7 */ +void EMACRxUnicastSet( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXUNICASTSET ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Disables unicast for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_026 */ +/* DesignId : ETH_DesignId_026*/ +/* Requirements : CONQ_EMAC_SR8 */ +void EMACRxUnicastClear( uint32 emacBase, uint32 channel ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + HWREG( emacBase + EMAC_RXUNICASTCLEAR ) |= ( ( uint32 ) 1U << channel ); +} + +/** + * \brief Set the free buffers for a specific channel + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * \param nBuf Number of free buffers + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_027 */ +/* DesignId : ETH_DesignId_027*/ +/* Requirements : CONQ_EMAC_SR15 */ +void EMACNumFreeBufSet( uint32 emacBase, uint32 channel, uint32 nBuf ) +{ + HWREG( emacBase + EMAC_RXFREEBUFFER( channel ) ) = nBuf; +} + +/** + * \brief Gets the interrupt vectors of EMAC, which are pending + * + * \param emacBase Base Address of the EMAC module registers. + * + * \return Vectors + * + **/ +/* SourceId : ETH_SourceId_028 */ +/* DesignId : ETH_DesignId_028*/ +/* Requirements : CONQ_EMAC_SR14 */ +uint32 EMACIntVectorGet( uint32 emacBase ) +{ + return ( HWREG( emacBase + EMAC_MACINVECTOR ) ); +} + +/** + * Function to setup the instance parameters inside the interface + * @param hdkif Network interface structure + * @return none. + */ +/* SourceId : ETH_SourceId_029 */ +/* DesignId : ETH_DesignId_029*/ +/* Requirements : CONQ_EMAC_SR3 */ +void EMACInstConfig( hdkif_t * hdkif ) +{ + hdkif->emac_base = EMAC_0_BASE; + hdkif->emac_ctrl_base = EMAC_CTRL_0_BASE; + hdkif->emac_ctrl_ram = EMAC_CTRL_RAM_0_BASE; + hdkif->mdio_base = MDIO_BASE; + hdkif->phy_addr = 1U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker. + */ + hdkif->phy_autoneg = &PhyAutoNegotiate; + hdkif->phy_partnerability = &PhyPartnerAbilityGet; +} + +/** + * Function to setup the link. AutoNegotiates with the phy for link + * setup and set the EMAC with the result of autonegotiation. + * @param hdkif Network interface structure. + * @return ERR_OK if everything passed + * others if not passed + */ +/* SourceId : ETH_SourceId_030 */ +/* DesignId : ETH_DesignId_030*/ +/* Requirements : CONQ_EMAC_SR4 */ +uint32 EMACLinkSetup( hdkif_t * hdkif ) +{ + uint32 linkstat = EMAC_ERR_CONNECT; + uint16 partnr_ablty = 0U; + uint32 phyduplex = EMAC_DUPLEX_HALF; + volatile uint32 delay = 0xFFFFFU; + + if( PhyAutoNegotiate( ( uint32 ) hdkif->mdio_base, + ( uint32 ) hdkif->phy_addr, + ( uint16 ) ( ( uint16 ) DP83640_100BTX + | ( uint16 ) DP83640_100BTX_FD + | ( uint16 ) DP83640_10BT + | ( uint16 ) DP83640_10BT_FD ) ) + == TRUE ) + { + linkstat = EMAC_ERR_OK; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA + * checker (due to use of & ?) */ + ( void ) PhyPartnerAbilityGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_ablty ); + + /* Check for 100 Mbps and duplex capability */ + if( ( partnr_ablty & DP83640_100BTX_FD ) != 0U ) + { + phyduplex = EMAC_DUPLEX_FULL; + } + } + + else + { + linkstat = EMAC_ERR_CONNECT; + } + + /* Set the EMAC with the negotiation results if it is successful */ + if( linkstat == EMAC_ERR_OK ) + { + EMACDuplexSet( hdkif->emac_base, phyduplex ); + } + + /* Wait for the MII to settle down */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + delay--; + } + + return linkstat; +} + +/** + * \brief Perform a transmit queue teardown, that is, transmission is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_031 */ +/* DesignId : ETH_DesignId_031*/ +/* Requirements : CONQ_EMAC_SR34 */ +void EMACTxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_TXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform a receive queue teardown, that is, reception is aborted. + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_032 */ +/* DesignId : ETH_DesignId_032*/ +/* Requirements : CONQ_EMAC_SR35 */ +void EMACRxTeardown( uint32 emacBase, uint32 channel ) +{ + HWREG( emacBase + EMAC_RXTEARDOWN ) &= ( channel ); +} + +/** + * \brief Perform multicast frame filtering using the MAC Hash Registers. + * + * \param emacBase Base Address of the EMAC module registers. + * \param hashTable The hash table which specifies which bits are to be accepted. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_033 */ +/* DesignId : ETH_DesignId_033*/ +/* Requirements : CONQ_EMAC_SR38 */ +void EMACFrameSelect( uint32 emacBase, uint64 hashTable ) +{ + HWREG( emacBase + EMAC_MACHASH1 ) = ( uint32 ) ( hashTable & 0xFFFFFFFFU ); + HWREG( emacBase + EMAC_MACHASH2 ) = ( uint32 ) ( hashTable >> 32U ); +} + +/** + * \brief Sets the Transmit Queue Priority type in the MACCONTROL Register + * + * \param emacBase Base Address of the EMAC module registers. + * \param txPType The Transmit Queue Priority Type. + * 0 results in a round-robin scheme being used to select the next + *channel, while 1 results in a fixed-priority scheme( channel 7 highest priority). + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_034 */ +/* DesignId : ETH_DesignId_034*/ +/* Requirements : CONQ_EMAC_SR39 */ +void EMACTxPrioritySelect( uint32 emacBase, uint32 txPType ) +{ + /* 1- The queue uses a fixed-priority (channel 7 highest priority) scheme */ + if( txPType == 1U ) + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXPTYPE; + } + else + { + HWREG( emacBase + + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_TXPTYPE ) ); + } +} + +/** + * \brief Performs a soft reset of the EMAC and EMAC Control Modules. + * + * \param emacCtrlBase Base address of the EMAC CONTROL module registers + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_035 */ +/* DesignId : ETH_DesignId_035*/ +/* Requirements : CONQ_EMAC_SR40 */ +void EMACSoftReset( uint32 emacCtrlBase, uint32 emacBase ) +{ + /* Reset the EMAC Control Module. This clears the CPPI RAM also */ + HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) = EMAC_CONTROL_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacCtrlBase + EMAC_CTRL_SOFTRESET ) & EMAC_CONTROL_RESET ) + == EMAC_CONTROL_RESET ) + { + /* Wait for the reset to complete */ + } + + /* Reset the EMAC Module. */ + HWREG( emacBase + EMAC_SOFTRESET ) = EMAC_SOFT_RESET; + + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( emacBase + EMAC_SOFTRESET ) & EMAC_SOFT_RESET ) == EMAC_SOFT_RESET ) + { + /* Wait for the Reset to complete */ + } +} + +/** + * \brief Enable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_036 */ +/* DesignId : ETH_DesignId_036*/ +/* Requirements : CONQ_EMAC_SR51 */ +void EMACEnableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_CMDIDLE; +} + +/** + * \brief Disable Idle State of the EMAC Module. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_037 */ +/* DesignId : ETH_DesignId_037*/ +/* Requirements : CONQ_EMAC_SR52 */ +void EMACDisableIdleState( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) ( EMAC_MACCONTROL_CMDIDLE ) ); +} + +/** + * \brief Enables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_038 */ +/* DesignId : ETH_DesignId_038*/ +/* Requirements : CONQ_EMAC_SR70 */ +void EMACEnableLoopback( uint32 emacBase ) +/*SAFETYMCUSW 1 J MR:14.1 "LDRA Tool issue." */ +{ + uint32 GMIIENval = 0U; + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Enable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_LOOPBACK; + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Disables Loopback Mode. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_039 */ +/* DesignId : ETH_DesignId_039*/ +/* Requirements : CONQ_EMAC_SR71 */ +void EMACDisableLoopback( uint32 emacBase ) +{ + uint32 GMIIENval = 0U; + + /*Store the value of GMIIEN bit before deasserting it */ + GMIIENval = HWREG( emacBase + EMAC_MACCONTROL ) & EMAC_MACCONTROL_GMIIEN; + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_GMIIEN ); + + /*Disable Loopback */ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_LOOPBACK ); + + /*Restore the value of GMIIEN bit */ + HWREG( emacBase + EMAC_MACCONTROL ) |= GMIIENval; +} + +/** + * \brief Enable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_040 */ +/* DesignId : ETH_DesignId_040*/ +/* Requirements : CONQ_EMAC_SR24 */ +void EMACTxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_TXFLOWEN; +} + +/** + * \brief Disable Transmit Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_041 */ +/* DesignId : ETH_DesignId_041*/ +/* Requirements : CONQ_EMAC_SR25 */ +void EMACTxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_TXFLOWEN ); +} + +/** + * \brief Enable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_042 */ +/* DesignId : ETH_DesignId_042*/ +/* Requirements : CONQ_EMAC_SR26 */ +void EMACRxFlowControlEnable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) |= EMAC_MACCONTROL_RXBUFFERFLOWEN; +} + +/** + * \brief Disable Receive Flow Control. + * + * \param emacBase Base Address of the EMAC module registers. + * \return None + * + **/ +/* SourceId : ETH_SourceId_043 */ +/* DesignId : ETH_DesignId_043*/ +/* Requirements : CONQ_EMAC_SR27 */ +void EMACRxFlowControlDisable( uint32 emacBase ) +{ + HWREG( emacBase + EMAC_MACCONTROL ) &= ( ~( uint32 ) EMAC_MACCONTROL_RXBUFFERFLOWEN ); +} + +/** + * \brief Performs byte inversion of 32-bit data to counteract swizzling performed by + *CPU during reads of CPPI RAM.(Due to BE8 format) + * + * \param word The 32-bit word to be swizzled. + * \return uint32 + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : CONQ_EMAC_SR73 */ +uint32 EMACSwizzleData( uint32 word ) +{ +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + return word; +#else + return ( ( ( word << 24U ) & 0xFF000000U ) | ( ( word << 8U ) & 0x00FF0000U ) + | ( ( word >> 8U ) & 0x0000FF00U ) | ( ( word >> 24U ) & 0x000000FFU ) ); +#endif +} + +/** + * \brief Receive flow threshold. These bits contain the threshold value for issuing + *flow control on incoming frames for channel n (when enabled). + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param threshold threshold value for issuing flow control on incoming frames for + *the given channel \return None + * + **/ +/* SourceId : ETH_SourceId_044 */ +/* DesignId : ETH_DesignId_044*/ +/* Requirements : CONQ_EMAC_SR28 */ +void EMACRxSetFlowThreshold( uint32 emacBase, uint32 channel, uint32 threshold ) +{ + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) &= ( 0x0U ); + HWREG( emacBase + EMAC_RXFLOWTHRESH( channel ) ) |= threshold; +} + +/** + * \brief This function reads the contents of the 36 network statistics + *registers that are present in the module. \param emacBase Base Address of the EMAC + *module registers. \param statRegNo The number of the register with RXGOODFRAMES + *(Offset= 0x200) being 0. Refer the Technical Reference Manual for the list of registers + *and their contents. \return uint32 + **/ +/* SourceId : ETH_SourceId_045 */ +/* DesignId : ETH_DesignId_045*/ +/* Requirements : CONQ_EMAC_SR47 */ +uint32 EMACReadNetStatRegisters( uint32 emacBase, uint32 statRegNo ) +{ + return HWREG( emacBase + EMAC_NETSTATREGS( statRegNo ) ); +} + +/** + * \brief Function to read values of Transmit Interrupt Status registers + *(TXINTSTATMASKED and TXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param txintstat pointer to the emac_tx_int_status Structure that will store the + *register values that have been read \return None + * + **/ +/* SourceId : ETH_SourceId_046 */ +/* DesignId : ETH_DesignId_046*/ +/* Requirements : CONQ_EMAC_SR36 */ +void EMACTxIntStat( uint32 emacBase, uint32 channel, emac_tx_int_status_t * txintstat ) +{ + txintstat->intstatmasked = ( HWREG( emacBase + EMAC_TXINTSTATMASKED ) + & ( ( uint32 ) 1U << channel ) ); + txintstat->intstatraw = ( HWREG( emacBase + EMAC_TXINTSTATRAW ) + & ( ( uint32 ) 1U << channel ) ); +} + +/** + * \brief Function to read values of Receive Interrupt Status registers + *(RXINTSTATMASKED, RXINTSTATRAW) + * + * \param emacBase Base Address of the EMAC module registers. + * \param channel Channel Number + * \param rxintstat pointer to the emac_rx_int_status Structure that will store the + *register values that have been read. \return None + **/ +/* SourceId : ETH_SourceId_047 */ +/* DesignId : ETH_DesignId_047*/ +/* Requirements : CONQ_EMAC_SR37 */ +void EMACRxIntStat( uint32 emacBase, uint32 channel, emac_rx_int_status_t * rxintstat ) +{ + rxintstat->intstatmasked_pend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatmasked_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATMASKED ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); + + rxintstat->intstatraw_pend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U << ( uint32 ) ( channel ) ) ); + rxintstat->intstatraw_threshpend = ( HWREG( emacBase + EMAC_RXINTSTATRAW ) + & ( ( uint32 ) 0x1U + << ( ( uint32 ) 0x8U + + ( uint32 ) ( channel ) ) ) ); +} + +/** + * \brief Tx and Rx Buffer Descriptors are initialized. Buffer pointers are allocated to + *the Rx Descriptors. + * + * \param hdkif network interface structure + * \return None + * + **/ +/* SourceId : ETH_SourceId_048 */ +/* DesignId : ETH_DesignId_048*/ +/* Requirements : CONQ_EMAC_SR19,CONQ_EMAC_SR20 */ +void EMACDMAInit( hdkif_t * hdkif ) +{ + uint32 num_bd, pbuf_cnt = 0U; + volatile emac_tx_bd_t *curr_txbd, *last_txbd; + volatile emac_rx_bd_t *curr_bd, *last_bd; + txch_t * txch_dma; + rxch_t * rxch_dma; + uint8_t * p; + + txch_dma = &( hdkif->txchptr ); + + /** + * Initialize the Descriptor Memory For TX and RX + * Only single channel is supported for both TX and RX + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + txch_dma->free_head = ( volatile emac_tx_bd_t * ) ( hdkif->emac_ctrl_ram ); + txch_dma->next_bd_to_process = txch_dma->free_head; + txch_dma->active_tail = NULL; + + /* Set the number of descriptors for the channel */ + num_bd = ( SIZE_EMAC_CTRL_RAM >> 1U ) / sizeof( emac_tx_bd_t ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_txbd = txch_dma->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd = curr_txbd; + + /* Initialize all the TX buffer Descriptors */ + while( num_bd != 0U ) + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list + * is incremented." */ + curr_txbd->next = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) ( curr_txbd + 1U ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd->flags_pktlen = 0U; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_txbd = curr_txbd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_txbd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_txbd->next ); + num_bd--; + } + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_txbd->next = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) txch_dma->free_head ); + + /* Initialize the descriptors for the RX channel */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma = &( hdkif->rxchptr ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked list is + * incremented." */ + curr_txbd++; + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "Linked List pointer needs to be + * assigned." */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "Linked List pointer needs to be assigned." + */ + /*SAFETYMCUSW 344 S MR:11.5 "Linked List pointer needs to be assigned to a + * different structure." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_head = ( volatile emac_rx_bd_t * ) curr_txbd; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->free_head = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_dma->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = curr_bd; + + /* + ** Static allocation of a specific number of packet buffers as specified by + *MAX_RX_PBUF_ALLOC, whose value is entered by the user in HALCoGen GUI. + */ + + /*Commented part of allocation of pbufs need to check whether its true*/ + + for( pbuf_cnt = 0U; pbuf_cnt < MAX_RX_PBUF_ALLOC; pbuf_cnt++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + p = pbuf_array[ pbuf_cnt ]; + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = EMACSwizzleData( ( uint32 ) p ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( EMAC_BUF_DESC_OWNER ); + if( pbuf_cnt == ( MAX_RX_PBUF_ALLOC - 1U ) ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + else + { + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd->next = ( emac_rx_bd_t * ) EMACSwizzleData( + ( uint32 ) ( curr_bd + 1U ) ); + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Struct pointer used for linked + * list is incremented." */ + curr_bd++; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + } + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd->next = NULL; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + rxch_dma->active_tail = last_bd; +} + +/** + * \brief Initializes the EMAC module for transmission and reception. + * + * \param macaddr MAC Address of the Module. + * \param channel Channel Number. + * + * \return EMAC_ERR_OK if everything gets initialized + * EMAC_ERR_CONN in case of an error in connecting. + * + **/ +/* SourceId : ETH_SourceId_049 */ +/* DesignId : ETH_DesignId_049*/ +/* Requirements : CONQ_EMAC_SR2 */ +uint32 EMACHWInit( uint8_t macaddr[ 6U ] ) +{ + uint32 temp, channel; + volatile uint32 phyID = 0U; + volatile uint32 delay = 0xFFFU; + uint32 phyIdReadCount = 0xFFFFU; + volatile uint32 phyLinkRetries = 0xFFFFU; + hdkif_t * hdkif; + rxch_t * rxch; + uint32 retVal = EMAC_ERR_OK; + uint32 emacBase = 0U; +#if( EMAC_MII_ENABLE == 0U ) + uint16 partnr_spd; +#endif + + hdkif = &hdkif_data[ 0U ]; + EMACInstConfig( hdkif ); + /* set MAC hardware address */ + for( temp = 0U; temp < EMAC_HWADDR_LEN; temp++ ) + { + hdkif->mac_addr[ temp ] = macaddr[ ( EMAC_HWADDR_LEN - 1U ) - temp ]; + } + /*Initialize the EMAC, EMAC Control and MDIO modules. */ + EMACInit( hdkif->emac_ctrl_base, hdkif->emac_base ); + MDIOInit( hdkif->mdio_base, MDIO_FREQ_INPUT, MDIO_FREQ_OUTPUT ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( delay != 0U ) + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + delay--; + } + + /* Set the MAC Addresses in EMAC hardware */ + emacBase = hdkif->emac_base; /* MISRA Code Fix (12.2) */ + EMACMACSrcAddrSet( emacBase, hdkif->mac_addr ); + for( channel = 0U; channel < 8U; channel++ ) + { + emacBase = hdkif->emac_base; + EMACMACAddrSet( emacBase, channel, hdkif->mac_addr, EMAC_MACADDR_MATCH ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( phyID == 0U ) && ( phyIdReadCount > 0U ) ) + { + phyID = PhyIDGet( hdkif->mdio_base, hdkif->phy_addr ); + phyIdReadCount--; + } + + if( 0U == phyID ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( ( uint32 ) 0U + == ( ( MDIOPhyAliveStatusGet( hdkif->mdio_base ) >> hdkif->phy_addr ) + & ( uint32 ) 0x01U ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + +#if( EMAC_MII_ENABLE == 0U ) + PhyPartnerSpdGet( hdkif->mdio_base, hdkif->phy_addr, &partnr_spd ); + if( ( partnr_spd & 2U ) == 0U ) + { + EMACRMIISpeedSet( hdkif->emac_base, EMAC_MACCONTROL_RMIISPEED ); + } +#endif + + if( !PhyLinkStatusGet( hdkif->mdio_base, + ( uint32 ) EMAC_PHYADDRESS, + ( uint32 ) phyLinkRetries ) ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + if( EMACLinkSetup( hdkif ) != EMAC_ERR_OK ) + { + retVal = EMAC_ERR_CONNECT; + } + else + { + } + + /* The transmit and receive buffer descriptors are initialized here. + * Also, packet buffers are allocated to the receive buffer descriptors. + */ + + EMACDMAInit( hdkif ); + + /* Acknowledge receive and transmit interrupts for proper interrupt pulsing*/ + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_RX ); + EMACCoreIntAck( hdkif->emac_base, ( uint32 ) EMAC_INT_CORE0_TX ); + + /* Enable GMII bit in the MACCONTROL Rgister*/ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ + EMACMIIEnable( hdkif->emac_base ); + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_BROADCAST_ENABLE ) + EMACRxBroadCastEnable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxBroadCastDisable( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /* Enable Broadcast if enabled in the GUI. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_UNICAST_ENABLE ) + EMACRxUnicastSet( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxUnicastClear( hdkif->emac_base, ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /*Enable Full Duplex or Half-Duplex mode based on GUI Input. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_FULL_DUPLEX_ENABLE ) + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_FULL ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition arameter is taken as input from + * GUI." */ + EMACDuplexSet( EMAC_0_BASE, ( uint32 ) EMAC_DUPLEX_HALF ); +#endif + + /* Enable Loopback based on GUI Input */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_LOOPBACK_ENABLE ) + EMACEnableLoopback( hdkif->emac_base ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACDisableLoopback( hdkif->emac_base ); +#endif + + /* Enable Transmit and Transmit Interrupt */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_TX_ENABLE ) + EMACTxEnable( hdkif->emac_base ); + EMACTxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACTxDisable( hdkif->emac_base ); + EMACTxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + /* Enable Receive and Receive Interrupt. Then start receiving by writing to the HDP + * register. */ + /*SAFETYMCUSW 139 S MR:13.7 "Parameter is taken as input from GUI." */ +#if( EMAC_RX_ENABLE ) + EMACNumFreeBufSet( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) MAX_RX_PBUF_ALLOC ); + EMACRxEnable( hdkif->emac_base ); + EMACRxIntPulseEnable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); + rxch = &( hdkif->rxchptr ); + /* Write to the RX HDP for channel 0 */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) rxch->active_head, + ( uint32 ) EMAC_CHANNELNUMBER ); +#else + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + /*SAFETYMCUSW 1 J MR:14.1 "If condition parameter is taken as input from + * GUI." */ + EMACRxDisable( hdkif->emac_base ); + EMACRxIntPulseDisable( hdkif->emac_base, + hdkif->emac_ctrl_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) EMAC_CHANNELNUMBER ); +#endif + + return retVal; +} + +/** + * This function should do the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf might be + * chained. That is, one pbuf can span more than one tx buffer descriptors + * + * @param hdkif network interface structure + * @param pbuf the pbuf structure which contains the data to be sent using EMAC + * @return boolean. + * -Returns FALSE if a Null pointer was passed for transmission + * -Returns TRUE if valid data is sent and is transmitted. + */ +/* SourceId : ETH_SourceId_050 */ +/* DesignId : ETH_DesignId_050*/ +/* Requirements : CONQ_EMAC_SR49 */ +boolean EMACTransmit( hdkif_t * hdkif, pbuf_t * pbuf ) +{ + txch_t * txch; + pbuf_t * q; + uint32 flags_pktlen; + uint16 totLen; + uint16 qLen; + volatile emac_tx_bd_t *curr_bd, *active_head, *bd_end; + boolean retValue = FALSE; + if( ( pbuf != NULL ) && ( hdkif != NULL ) ) + { + txch = &( hdkif->txchptr ); + + /* Get the buffer descriptor which is free to transmit */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->free_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + active_head = curr_bd; + + /* Update the total packet length */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + totLen = pbuf->tot_len; + + curr_bd->flags_pktlen = 0U; + flags_pktlen = ( ( uint32 ) ( totLen ) + | ( EMAC_BUF_DESC_SOP | EMAC_BUF_DESC_OWNER ) ); + /* Indicate the start of the packet */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( flags_pktlen ); + + /* Copy pbuf information into TX buffer descriptors */ + q = pbuf; + while( q != NULL ) + { + /* Initialize the buffer pointer and length */ + /*SAFETYMCUSW 439 S MR:11.3 "RHS is a pointer value required to be + * stored. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufptr = EMACSwizzleData( ( uint32 ) ( q->payload ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + qLen = ( uint16 ) ( q->len ); + curr_bd->bufoff_len = ( uint32 ) EMACSwizzleData( + ( ( uint32 ) ( qLen ) & 0xFFFFU ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + q = q->next; + } + + /* Indicate the start and end of the packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + bd_end->next = NULL; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + bd_end->flags_pktlen |= EMACSwizzleData( EMAC_BUF_DESC_EOP ); + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required scope." + */ + txch->free_head = curr_bd; + + /* For the first time, write the HDP with the filled bd */ + if( txch->active_tail == NULL ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /* + * Chain the bd's. If the DMA engine, already reached the end of the chain, + * the EOQ will be set. In that case, the HDP shall be written again. + */ + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = txch->active_tail; + /* Wait for the EOQ bit is set */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( EMAC_BUF_DESC_EOQ + != ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) ) + { + } + /* Don't write to TXHDP0 until it turns to zero */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + while( ( ( uint32 ) 0U != *( ( uint32 * ) 0xFCF78600U ) ) ) + { + } + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->next = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) active_head ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( EMAC_BUF_DESC_EOQ + == ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) ) + { + /* Write the Header Descriptor Pointer and start DMA */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACTxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( active_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + } + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch->active_tail = bd_end; + retValue = TRUE; + } + else + { + retValue = FALSE; + } + return retValue; +} + +/** + * Function for processing Tx buffer descriptors. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_051 */ +/* DesignId : ETH_DesignId_051*/ +/* Requirements : CONQ_EMAC_SR13 */ +void EMACTxIntHandler( hdkif_t * hdkif ) +{ + txch_t * txch_int; + volatile emac_tx_bd_t *curr_bd, *next_bd_to_process; + + txch_int = &( hdkif->txchptr ); + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = next_bd_to_process; + + /* Check for correct start of packet */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_SOP ) + == EMAC_BUF_DESC_SOP ) + { + /* Make sure that the transmission is over */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_OWNER ) + == EMAC_BUF_DESC_OWNER ) + { + } + + /* Traverse till the end of packet is reached */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( ( EMACSwizzleData( curr_bd->flags_pktlen ) ) & EMAC_BUF_DESC_EOP ) + != EMAC_BUF_DESC_EOP ) + { + curr_bd = ( emac_tx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + } + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process->flags_pktlen &= ~( EMACSwizzleData( EMAC_BUF_DESC_SOP ) ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen &= ~( EMACSwizzleData( EMAC_BUF_DESC_EOP ) ); + + /** + * If there are no more data transmitted, the next interrupt + * shall happen with the pbuf associated with the free_head + */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( curr_bd->next == NULL ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = txch_int->free_head; + } + + else + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + txch_int->next_bd_to_process = ( emac_tx_bd_t * ) EMACSwizzleData( + ( uint32 ) curr_bd->next ); + } + + /* Acknowledge the EMAC and free the corresponding pbuf */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as as + * an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 344 S MR:11.5 "Address stored in pointer is passed as as + * an int parameter." */ + EMACTxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) curr_bd ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + next_bd_to_process = txch_int->next_bd_to_process; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = next_bd_to_process; + } +} + +/** + * Function for processing received packets. + * + * @param hdkif interface structure + * @return none + */ +/* SourceId : ETH_SourceId_052 */ +/* DesignId : ETH_DesignId_052*/ +/* Requirements : CONQ_EMAC_SR50 */ +void EMACReceive( hdkif_t * hdkif ) +{ + rxch_t * rxch_int; + volatile emac_rx_bd_t *curr_bd, *curr_tail, *last_bd; + + /* The receive structure that holds data about a particular receive channel */ + rxch_int = &( hdkif->rxchptr ); + + /* Get the buffer descriptors which contain the earliest filled data */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + curr_bd = rxch_int->active_head; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + last_bd = rxch_int->active_tail; + + /** + * Process the descriptors as long as data is available + * when the DMA is receiving data, SOP flag will be set + */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are assigned in + * this driver" */ + while( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_SOP ) + == EMAC_BUF_DESC_SOP ) + { + /* Start processing once the packet is loaded */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_OWNER ) + != EMAC_BUF_DESC_OWNER ) + { + /* this bd chain will be freed after processing */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + + /* Get the total length of the packet. curr_bd points to the start + * of the packet. + */ + + /* + * The loop runs till it reaches the end of the packet. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + while( ( EMACSwizzleData( curr_bd->flags_pktlen ) & EMAC_BUF_DESC_EOP ) + != EMAC_BUF_DESC_EOP ) + { + /*Update the flags for the descriptor again and the length of the buffer*/ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( ( uint32 ) EMAC_BUF_DESC_OWNER ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( ( uint32 ) MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_rx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + } + + /* Updating the last descriptor (which contained the EOP flag) */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->flags_pktlen = EMACSwizzleData( ( uint32 ) EMAC_BUF_DESC_OWNER ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd->bufoff_len = EMACSwizzleData( ( uint32 ) MAX_TRANSFER_UNIT ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd = curr_bd; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_bd = ( emac_rx_bd_t * ) EMACSwizzleData( ( uint32 ) curr_bd->next ); + + /* Acknowledge that this packet is processed */ + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is passed as + * as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxCPWrite( hdkif->emac_base, + ( uint32 ) EMAC_CHANNELNUMBER, + ( uint32 ) last_bd ); + + /* The next buffer descriptor is the new head of the linked list. */ + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->active_head = curr_bd; + + /* The processed descriptor is now the tail of the linked list. */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail = rxch_int->active_tail; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + curr_tail->next = ( emac_rx_bd_t * ) EMACSwizzleData( + ( uint32 ) rxch_int->free_head ); + + /* The last element in the already processed Rx descriptor chain is now the + * end of list. */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + last_bd->next = NULL; + + /** + * Check if the reception has ended. If the EOQ flag is set, the NULL + * Pointer is taken by the DMA engine. So we need to write the RX HDP + * with the next descriptor. + */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + if( ( EMACSwizzleData( curr_tail->flags_pktlen ) & EMAC_BUF_DESC_EOQ ) + == EMAC_BUF_DESC_EOQ ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Address stored in pointer is + * passed as as an int parameter. - Advisory as per MISRA" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + EMACRxHdrDescPtrWrite( hdkif->emac_base, + ( uint32 ) ( rxch_int->free_head ), + ( uint32 ) EMAC_CHANNELNUMBER ); + } + + /*SAFETYMCUSW 71 S MR:17.6 "Assigned pointer value has required + * scope." */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * assigned in this driver" */ + rxch_int->free_head = curr_bd; + rxch_int->active_tail = last_bd; + } + } +} + +/** @fn void EMACGetConfigValue(emac_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETH_SourceId_053 */ +/* DesignId : ETH_DesignId_053*/ +/* Requirements : CONQ_EMAC_SR74 */ +void EMACGetConfigValue( emac_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->TXCONTROL = EMAC_TXCONTROL_CONFIGVALUE; + config_reg->RXCONTROL = EMAC_RXCONTROL_CONFIGVALUE; + config_reg->TXINTMASKSET = EMAC_TXINTMASKSET_CONFIGVALUE; + config_reg->TXINTMASKCLEAR = EMAC_TXINTMASKCLEAR_CONFIGVALUE; + config_reg->RXINTMASKSET = EMAC_RXINTMASKSET_CONFIGVALUE; + config_reg->RXINTMASKCLEAR = EMAC_RXINTMASKCLEAR_CONFIGVALUE; + config_reg->MACSRCADDRHI = EMAC_MACSRCADDRHI_CONFIGVALUE; + config_reg->MACSRCADDRLO = EMAC_MACSRCADDRLO_CONFIGVALUE; + config_reg->MDIOCONTROL = EMAC_MDIOCONTROL_CONFIGVALUE; + config_reg->C0RXEN = EMAC_C0RXEN_CONFIGVALUE; + config_reg->C0TXEN = EMAC_C0TXEN_CONFIGVALUE; + } + else + { + config_reg->TXCONTROL = HWREG( EMAC_0_BASE + EMAC_TXCONTROL ); + config_reg->RXCONTROL = HWREG( EMAC_0_BASE + EMAC_RXCONTROL ); + config_reg->TXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_TXINTMASKSET ); + config_reg->TXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_TXINTMASKCLEAR ); + config_reg->RXINTMASKSET = HWREG( EMAC_0_BASE + EMAC_RXINTMASKSET ); + config_reg->RXINTMASKCLEAR = HWREG( EMAC_0_BASE + EMAC_RXINTMASKCLEAR ); + config_reg->MACSRCADDRHI = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRHI ); + config_reg->MACSRCADDRLO = HWREG( EMAC_0_BASE + EMAC_MACSRCADDRLO ); + config_reg->MDIOCONTROL = HWREG( MDIO_0_BASE + MDIO_CONTROL ); + config_reg->C0RXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnRXEN( 0U ) ); + config_reg->C0TXEN = HWREG( EMAC_CTRL_0_BASE + EMAC_CTRL_CnTXEN( 0U ) ); + } +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c new file mode 100644 index 00000000000..1274b7d517c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/emif.c @@ -0,0 +1,320 @@ +/** @file emif.c + * @brief emif Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void emif_SDRAMInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function has been deprecated. + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF clock + * below 40MHz. Hence the init function needs to be called from the startup before the PLL + * is configured. A new function emif_SDRAM_StartupInit has been added and is called from + * the startup. This function need not be called from the main, and is preserved for + * compatibilty. + */ + +/* SourceId : EMIF_SourceId_001 */ +/* DesignId : EMIF_DesignId_001 */ +/* Requirements : CONQ_EMIF_SR2 */ +void emif_SDRAMInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC1Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_002 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR3 */ +void emif_ASYNC1Init( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + emifREG->CE2CFG = 0x00000000U; + emifREG->CE2CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 16U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFFFF00U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 1U ) + | ( uint32 ) ( ( uint32 ) 0U ); + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC2Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_003 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR4 */ +void emif_ASYNC2Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + emifREG->CE3CFG = 0x00000000U; + emifREG->CE3CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 18U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFFFF00FFU ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ); + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void emif_ASYNC3Init(void) + * @brief Initializes the emif Driver for ASYNC memories + * + * This function initializes the emif driver for Asynchronous memories like Nor and Nand + * Flashes,Asynchronous RAM. + */ +/* SourceId : EMIF_SourceId_004 */ +/* DesignId : EMIF_DesignId_002 */ +/* Requirements : CONQ_EMIF_SR5 */ +void emif_ASYNC3Init( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + emifREG->CE4CFG = 0x00000000U; + emifREG->CE4CFG = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 15U << 26U ) + | ( uint32 ) ( ( uint32 ) 63U << 20U ) + | ( uint32 ) ( ( uint32 ) 7U << 17U ) + | ( uint32 ) ( ( uint32 ) 15U << 13U ) + | ( uint32 ) ( ( uint32 ) 63U << 7U ) + | ( uint32 ) ( ( uint32 ) 7U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) emif_8_bit_port ); + + emifREG->AWCC = ( emifREG->AWCC & 0xC0FF0000U ) + | ( uint32 ) ( ( uint32 ) emif_pin_high << 29U ) + | ( uint32 ) ( ( uint32 ) emif_pin_low << 28U ) + | ( uint32 ) ( ( uint32 ) emif_wait_pin0 << 20U ) + | ( uint32 ) ( ( uint32 ) 0U ); + + emifREG->PMCR = ( emifREG->PMCR & 0xFF00FFFFU ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) emif_4_words << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void emifGetConfigValue(emif_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the EMIF configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EMIF_SourceId_005 */ +/* DesignId : EMIF_DesignId_003 */ +/* Requirements : CONQ_EMIF_SR6 */ +void emifGetConfigValue( emif_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_AWCC = EMIF_AWCC_CONFIGVALUE; + config_reg->CONFIG_SDCR = EMIF_SDCR_CONFIGVALUE; + config_reg->CONFIG_SDRCR = EMIF_SDRCR_CONFIGVALUE; + config_reg->CONFIG_CE2CFG = EMIF_CE2CFG_CONFIGVALUE; + config_reg->CONFIG_CE3CFG = EMIF_CE3CFG_CONFIGVALUE; + config_reg->CONFIG_CE4CFG = EMIF_CE4CFG_CONFIGVALUE; + config_reg->CONFIG_CE5CFG = EMIF_CE5CFG_CONFIGVALUE; + config_reg->CONFIG_SDTIMR = EMIF_SDTIMR_CONFIGVALUE; + config_reg->CONFIG_SDSRETR = EMIF_SDSRETR_CONFIGVALUE; + config_reg->CONFIG_INTMSK = EMIF_INTMSK_CONFIGVALUE; + config_reg->CONFIG_PMCR = EMIF_PMCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_AWCC = emifREG->AWCC; + config_reg->CONFIG_SDCR = emifREG->SDCR; + config_reg->CONFIG_SDRCR = emifREG->SDRCR; + config_reg->CONFIG_CE2CFG = emifREG->CE2CFG; + config_reg->CONFIG_CE3CFG = emifREG->CE3CFG; + config_reg->CONFIG_CE4CFG = emifREG->CE4CFG; + config_reg->CONFIG_CE5CFG = emifREG->CE5CFG; + config_reg->CONFIG_SDTIMR = emifREG->SDTIMR; + config_reg->CONFIG_SDSRETR = emifREG->SDSRETR; + config_reg->CONFIG_INTMSK = emifREG->INTMSK; + config_reg->CONFIG_PMCR = emifREG->PMCR; + } +} + +/** @fn void emif_SDRAM_StartupInit(void) + * @brief Initializes the emif Driver for SDRAM + * + * This function initializes the emif driver for SDRAM (SDRAM initialization function). + * SDRAM Configuration Procedure B as documented in the TRM is implemented. + * + * Note: This function is called in the startup. Do not call the function inside main. + */ + +/* SourceId : EMIF_SourceId_006 */ +/* DesignId : EMIF_DesignId_004 */ +/* Requirements : CONQ_EMIF_SR2 */ +void emif_SDRAM_StartupInit( void ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + volatile uint32 buffer; + + /* Procedure B Step 1: EMIF Clock Frequency is assumed to be configured in the + * startup */ + + /* Procedure B Step 2: Program SDTIMR and SDSRETR to satisfy requirements of SDRAM + * Device */ + emifREG->SDTIMR = ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ); + + emifREG->SDSRETR = ( uint32 ) 0U; + + /* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of + * initialization time */ + emifREG->SDRCR = 1605U; + + /* Procedure B Step 4: Program SDRCR to Trigger Initialization Sequence */ + /** -general clearing of register + * -for NM for setting 16 bit data bus + * -cas latency + * -BIT11_9CLOCK to allow the cl field to be written + * -selecting the banks + * -setting the pagesize + */ + emifREG->SDCR = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 1U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 1U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) elements_256 ); + + /* Procedure B Step 5: Read of SDRAM memory location causes processor to wait until + * SDRAM Initialization completes */ + buffer = *PTR; + /* prevents optimization */ + buffer = buffer; + + /* Procedure B Step 6: Program the RR field to the default Refresh Interval of the + * SDRAM*/ + emifREG->SDRCR = 0U; + + /* Place the EMIF in Self Refresh Mode For Clock Change */ + /* Must only write to the upper byte of the SDCR to avoid */ + /* a second intiialization sequence */ + /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */ + *( ( unsigned char * ) ( &emifREG->SDCR ) + 0x3U ) = 0x80U; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c new file mode 100644 index 00000000000..1a16ccee63b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/epc.c @@ -0,0 +1,369 @@ +/** @file epc.c + * @brief EPC Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * This file contains APIs for the Error Profiling Controller Module. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "epc.h" +#include "system.h" +#include "reg_esm.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void epcEnableIP1ErrorGen(void) + * @brief Enable ECC error generation for ECC errors on DMA Port A + * + * Enable ECC error generation for ECC errors detected on DMA Port A master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_001 */ +/* DesignId : EPC_DesignId_001 */ +/* Requirements : CONQ_EPC_SR1 */ +void epcEnableIP1ErrorGen( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void epcDisableIP1ErrorGen(void) + * @brief Disable ECC error generation for ECC errors on DMA Port A + * + * Disable ECC error generation for ECC errors detected on DMA Port A master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_002 */ +/* DesignId : EPC_DesignId_002 */ +/* Requirements : CONQ_EPC_SR2 */ +void epcDisableIP1ErrorGen( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void epcEnableIP2ErrorGen(void) + * @brief Enable ECC error generation for ECC errors on PS_SCR_M + * + * Enable ECC error generation for ECC errors detected on PS_SCR_M master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_003 */ +/* DesignId : EPC_DesignId_003 */ +/* Requirements : CONQ_EPC_SR3 */ +void epcEnableIP2ErrorGen( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFF0FFU ) | 0xA00U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void epcDisableIP2ErrorGen(void) + * @brief Disable ECC error generation for ECC errors on PS_SCR_M + * + * Disable ECC error generation for ECC errors detected on PS_SCR_M master by the + * CPU Interconnect Subsystem + */ +/* SourceId : EPC_SourceId_004 */ +/* DesignId : EPC_DesignId_004 */ +/* Requirements : CONQ_EPC_SR4 */ +void epcDisableIP2ErrorGen( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + systemREG2->IP1ECCERREN = ( systemREG2->IP1ECCERREN & 0xFFFFF0FFU ) | 0x500U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void epcEnableSERREvent(void) + * @brief Single (correctable) bit error event enable. + * + * These bits (when enabled) cause EPC to + * generate the serr_event if there is a correctable ECC fault address arrives from one + * of the EPC-IP interface and the CAM has an empty entry. + */ +/* SourceId : EPC_SourceId_005 */ +/* DesignId : EPC_DesignId_005 */ +/* Requirements : CONQ_EPC_SR5 */ +void epcEnableSERREvent( void ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFFFF0U ) | 0xAU; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void epcDisableSERREvent(void) + * @brief Single (correctable) bit error event disable. + * + * These bits (when enabled) cause EPC to + * disable the serr_event generation. + */ +/* SourceId : EPC_SourceId_006 */ +/* DesignId : EPC_DesignId_006 */ +/* Requirements : CONQ_EPC_SR6 */ +void epcDisableSERREvent( void ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFFFF0U ) | 0x5U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn void epcEnableInterrupt(void) + * @brief CAM or FIFO full interrupt enable. + * + * If this bit is set and CAM is full, CAM Full Interrupt + * is generated. + */ +/* SourceId : EPC_SourceId_007 */ +/* DesignId : EPC_DesignId_007 */ +/* Requirements : CONQ_EPC_SR7 */ +void epcEnableInterrupt( void ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL |= ( uint32 ) ( ( uint32 ) 1U << 24U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void epcDisableInterrupt(void) + * @brief CAM or FIFO full interrupt disable. + * + * Disables interrupt generation in case CAM is full. + */ +/* SourceId : EPC_SourceId_008 */ +/* DesignId : EPC_DesignId_008 */ +/* Requirements : CONQ_EPC_SR8 */ +void epcDisableInterrupt( void ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + epcREG1->EPCCNTRL &= ~( uint32 ) ( ( uint32 ) 1U << 24U ); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void epcCAMInit(void) + * @brief Initializes CAM. + * + * CAM entries are cleared and available for future CAM usage. + */ +/* SourceId : EPC_SourceId_009 */ +/* DesignId : EPC_DesignId_009 */ +/* Requirements : CONQ_EPC_SR9 */ +void epcCAMInit( void ) +{ + uint8 i; + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + for( i = 0U; i < 8U; i++ ) + { + epcREG1->CAM_INDEX[ i ] = 0x05050505U; + } + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void epcDiagnosticTest(void) + * @brief CAM diagnostic test. + * @return TRUE if diagnostic test passed, FALSE otherwise + * + * This function executes a diagnostic test on EPC and returns the result + */ +/* SourceId : EPC_SourceId_010 */ +/* DesignId : EPC_DesignId_010 */ +/* Requirements : CONQ_EPC_SR14 */ +boolean epcDiagnosticTest( void ) +{ + uint32 epccntrl_bk, camCont_bk, camIndex_bk; + uint32 camAvailable; + boolean status = true; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* Back up EPCCNTRL register */ + epccntrl_bk = epcREG1->EPCCNTRL; + + /* Back up CAM_CONTENT[0] and CAM_INDEX[0] registers */ + camCont_bk = epcREG1->CAM_CONTENT[ 0U ]; + camIndex_bk = epcREG1->CAM_INDEX[ 0U ]; + + /* Enter CAM diagnostic mode and and enable Single (correctable) bit error event + * generation */ + epcREG1->EPCCNTRL = ( epcREG1->EPCCNTRL & 0xFFFFF0F0U ) | 0x0A0AU; + + /* Clear first CAM entry */ + epcREG1->CAM_INDEX[ 0U ] = ( epcREG1->CAM_INDEX[ 0U ] & 0xFFFFFFF0U ) | 0x5U; + + /* Identify the number of CAM entries available */ + camAvailable = epcREG1->CAMAVAILSTAT; + + /* New CAM Entry */ + epcREG1->CAM_CONTENT[ 0U ] = 0x1000U; + + /* The number of CAM entries must reduce by 1 */ + if( ( ( esmREG->SR1[ 0U ] & 0x10U ) != 0x10U ) + || ( epcREG1->CAMAVAILSTAT != ( camAvailable - 1U ) ) + || ( epcCheckCAMEntry( 0U ) == true ) ) + { + status = false; + } + + /* Restore CAM_CONTENT and CAM_INDEX[0] registers */ + epcREG1->CAM_CONTENT[ 0U ] = camCont_bk; + epcREG1->CAM_INDEX[ 0U ] = camIndex_bk; + + /* Disable CAM diagnostic mode and restore EPCCNTRL register */ + epcREG1->EPCCNTRL = epccntrl_bk; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + return status; +} + +/** @fn void epcAddCAMEEntry(uint32 address) + * @brief Add a new CAM Entry + * + * Allows you to write a new CAM entry, after checking if there are any available + * entries. + */ +/* SourceId : EPC_SourceId_011 */ +/* DesignId : EPC_DesignId_011 */ +/* Requirements : CONQ_EPC_SR10 */ +boolean epcAddCAMEEntry( uint32 address ) +{ + uint8 i = 0U; + boolean status = false; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + if( epcREG1->CAMAVAILSTAT != 0U ) + { + for( i = 0U; i < 32U; i++ ) + { + if( epcCheckCAMEntry( i ) == true ) + { + epcREG1->CAM_CONTENT[ i ] = address; + status = true; + break; + } + } + } + else + { + status = false; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + return status; +} + +/** @fn void epcCheckCAMEntry(uint32 CAMIndex) + * @brief Checks if CAM entry is available. + * + * Checks if the CAM Entry is available and ready for future usage. + */ +/* SourceId : EPC_SourceId_012 */ +/* DesignId : EPC_DesignId_012 */ +/* Requirements : CONQ_EPC_SR11 */ +boolean epcCheckCAMEntry( uint32 index ) +{ + uint32 i, j; + boolean status = false; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + i = index / 4U; + j = ( index % 4U ) * 8U; + + /* Check for availability of CAM Entry for future CAM usage. */ + if( ( epcREG1->CAM_INDEX[ i ] & ( uint32 ) ( ( uint32 ) 0xFU << j ) ) + == ( uint32 ) ( ( uint32 ) 0x5U << j ) ) + { + status = true; + } + else + { + status = false; + } + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + return status; +} + +/* USER CODE BEGIN (28) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c new file mode 100644 index 00000000000..fec49834f0e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/eqep.c @@ -0,0 +1,1273 @@ +/** @file eqep.c + * @brief EQEP Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the EQEP driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "eqep.h" +#include "sys_vim.h" + +/*the functions + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void QEPInit(void) + * @brief Initializes the eQEP Driver + * + * This function initializes the eQEP module. + */ +/* SourceId : EQEP_SourceId_001 */ +/* DesignId : EQEP_DesignId_001 */ +/* Requirements : CONQ_QEP_SR1 */ +void QEPInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG1->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG1->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG1->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG1->QPOSCMP = 0x00000000U; + + /** - Clear the time base */ + eqepREG1->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG1->QUPRD = ( uint32 ) 0x00000000U; + + /** - Clear Watchdog Timer register */ + eqepREG1->QWDTMR = ( uint16 ) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG1->QWDPRD = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG1->QDECCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) + | ( uint16 ) ( ( uint16 ) 0U << 13U ) + | ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) + | ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Stobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG1 + ->QEPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) + | ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) + | ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ + << 2U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG1->QPOSCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) + | ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP + << 14U ) + | ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) + | ( uint16 ) ( ( uint16 ) 0x000U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG1->QCAPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) + | ( uint16 ) 0x0000U ); + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG1->QCLR = ( uint16 ) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG1->QEINT = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) ( ( uint16 ) 0U << 4U ) + | ( uint16 ) ( ( uint16 ) 0U << 3U ) + | ( uint16 ) ( ( uint16 ) 0U << 2U ) + | ( uint16 ) ( ( uint16 ) 0U << 1U ) ); + + /** - Clear Capture Timer register */ + eqepREG1->QCTMR = ( uint16 ) 0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG1->QCPRD = ( uint16 ) 0x0000U; + + /** - Clear Period Latch register */ + eqepREG1->QCPRDLAT = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + /** - Clear Position Counter register */ + eqepREG2->QPOSCNT = 0x00000000U; + + /** - Initialize Position Counter value register */ + eqepREG2->QPOSINIT = 0x00000000U; + + /** - Set Maximum position counter value */ + eqepREG2->QPOSMAX = 0x00000000U; + + /** - Set the initial Position compare value */ + eqepREG2->QPOSCMP = 0U; + + /** - Clear the time base */ + eqepREG2->QUTMR = 0x00000000U; + + /** - Configure unit period register */ + eqepREG2->QUPRD = ( uint32 ) 0U; + + /** - Clear Watchdog Timer register */ + eqepREG2->QWDTMR = ( uint16 ) 0x00000000U; + + /** - Configure Watchdog Period */ + eqepREG2->QWDPRD = ( uint16 ) 0U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /** - Setup Decoder Control Register + * - Select Position counter Mode + * - Enable / Disable Sync Output + * - Select Sync Output Pin + * - Select external Clock rate ( resolution) + * - Enable / Disable Swap Quadrature clock input + * - Enable / Disable Gating of index pulse with Strobe. + * - Enable / Disable Negate QEPA input + * - Enable / Disable Negate QEPB input + * - Enable / Disable Negate QEPI input + * - Enable / Disable Negate QEPS input + */ + eqepREG2->QDECCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_DIRECTION_COUNT << 14U ) + | ( uint16 ) ( ( uint16 ) 0U << 13U ) + | ( uint16 ) ( ( uint16 ) eQEP_INDEX_PIN << 12U ) + | ( uint16 ) ( ( uint16 ) eQEP_RESOLUTION_1x << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Control Register + * - Select Position counter Reset Mode + * - Enable & Select Strobe event initialization of position counter + * - Enable & Select Index event initialization of position counter + * - Enable / Disable Software Initialization of Position counter. + * - Select Strobe event latch of position counter. + * - Select Index event latch of position counter. + * - Select EQEP capture Latch mode + */ + eqepREG2 + ->QEPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_MAX_POSITION << 12U ) + | ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) eQEP_DIRECTON_DEPENDENT << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) eQEP_RISING_EDGE << 6U ) + | ( uint16 ) ( ( uint16 ) eQEP_LATCH_RISING_EDGE << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_ON_POSITION_COUNTER_READ + << 2U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Position Control Register + * - Enable / Disable Position compare shadow. + * - Select Position compare shadow load mode. + * - Select Polarity of Sync output. + * - Select Position compare sync output pulse width. + */ + eqepREG2->QPOSCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 15U ) + | ( uint16 ) ( ( uint16 ) eQEP_QPOSCNT_EQ_QPSCMP + << 14U ) + | ( uint16 ) ( ( uint16 ) eQEP_ACTIVE_HIGH << 13U ) + | ( uint16 ) ( ( uint16 ) 0U ) + | ( uint16 ) 0x0000U ); + + /** - Setup eQEP Capture Control Register + * - Select capture timer clock prescaler. + * - Select Unit position event prescaler. + */ + eqepREG2->QCAPCTL = ( uint16 ) ( ( uint16 ) ( ( uint16 ) eQEP_PS_8 << 4U ) + | ( uint16 ) ( ( uint16 ) eQEP_PS_512 ) + | ( uint16 ) 0x0000U ); + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Clear Interrupt Flag register */ + eqepREG2->QCLR = ( uint16 ) 0xFFFFU; + + /** - Setup eQEP Interrupt Enable Register + * Enable / Diable UTO Interrupt + * Enable / Diable IEL Interrupt + * Enable / Diable SEL Interrupt + * Enable / Diable PCM Interrupt + * Enable / Diable PCR Interrupt + * Enable / Diable PCO Interrupt + * Enable / Diable PCU Interrupt + * Enable / Diable WTO Interrupt + * Enable / Diable QDC Interrupt + * Enable / Diable QPE Interrupt + * Enable / Diable PCE Interrupt + */ + eqepREG2->QEINT = ( uint16 ) ( ( uint16 ) ( ( uint16 ) 0U << 11U ) + | ( uint16 ) ( ( uint16 ) 0U << 10U ) + | ( uint16 ) ( ( uint16 ) 0U << 9U ) + | ( uint16 ) ( ( uint16 ) 0U << 8U ) + | ( uint16 ) ( ( uint16 ) 0U << 7U ) + | ( uint16 ) ( ( uint16 ) 0U << 6U ) + | ( uint16 ) ( ( uint16 ) 0U << 5U ) + | ( uint16 ) ( ( uint16 ) 0U << 4U ) + | ( uint16 ) ( ( uint16 ) 0U << 3U ) + | ( uint16 ) ( ( uint16 ) 0U << 2U ) + | ( uint16 ) ( ( uint16 ) 0U << 1U ) ); + + /** - Clear Capture Timer register */ + eqepREG2->QCTMR = ( uint16 ) 0x0000U; + + /** - Clear the Capture Period regiter */ + eqepREG2->QCPRD = ( uint16 ) 0x0000U; + + /** - Clear Period Latch register */ + eqepREG2->QCPRDLAT = ( uint16 ) 0x0000U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @brief Clears all QEP interrupt flags + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_002 */ +/* DesignId : EQEP_DesignId_002 */ +/* Requirements : CONQ_QEP_SR2 */ +void eqepClearAllInterruptFlags( eqepBASE_t * eqep ) +{ + eqep->QCLR = 0xfffU; + + return; +} /*end of eQEP_clear_all_interrupt_flags() function */ + +/** @brief Clears a single interrupt flag + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Interrupt flag + */ +/* SourceId : EQEP_SourceId_003 */ +/* DesignId : EQEP_DesignId_003 */ +/* Requirements : CONQ_QEP_SR3 */ +void eqepClearInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QCLR |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_clear_interrupt_flag() function */ + +/** @brief Clears the position counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_004 */ +/* DesignId : EQEP_DesignId_004 */ +/* Requirements : CONQ_QEP_SR4 */ +void eqepClearPosnCounter( eqepBASE_t * eqep ) +{ + eqep->QPOSCNT = 0U; + + return; +} /*end of eQEP_clear_posn_counter() function */ + +/** @brief Disables all interrupts + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_005 */ +/* DesignId : EQEP_DesignId_005 */ +/* Requirements : CONQ_QEP_SR5 */ +void eqepDisableAllInterrupts( eqepBASE_t * eqep ) +{ + eqep->QEINT = 0U; + + return; +} /*end of eQEP_disable_all_interrupts () function */ + +/** @brief Disable capture + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_006 */ +/* DesignId : EQEP_DesignId_006 */ +/* Requirements : CONQ_QEP_SR6 */ +void eqepDisableCapture( eqepBASE_t * eqep ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_disable_capture () function */ + +/** @brief Disable gating of index pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_007 */ +/* DesignId : EQEP_DesignId_007 */ +/* Requirements : CONQ_QEP_SR7 */ +void eqepDisableGateIndex( eqepBASE_t * eqep ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_IGATE; + + return; +} /*end of eQEP_disable_gate_index () function */ + +/** @brief Disable individual interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Individual interrupts + */ +/* SourceId : EQEP_SourceId_008 */ +/* DesignId : EQEP_DesignId_008 */ +/* Requirements : CONQ_QEP_SR8 */ +void eqepDisableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QEINT &= ( uint16 ) ~( uint16 ) QEINT_type; + + return; +} /*end of eQEP_disable_interrupt */ + +/** @brief Disable position compare + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_009 */ +/* DesignId : EQEP_DesignId_009 */ +/* Requirements : CONQ_QEP_SR9 */ +void eqepDisablePosnCompare( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_disable_posn_compare () function */ + +/** @brief Disable position compare shadowing + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_010 */ +/* DesignId : EQEP_DesignId_010 */ +/* Requirements : CONQ_QEP_SR10 */ +void eqepDisablePosnCompareShadow( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_disable_posn_compare_shadow () function */ + +/** @brief Disable output sync pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_011 */ +/* DesignId : EQEP_DesignId_011 */ +/* Requirements : CONQ_QEP_SR11 */ +void eqepDisableSyncOut( eqepBASE_t * eqep ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_disable_sync_out () function */ + +/** @brief Disable unit timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_012 */ +/* DesignId : EQEP_DesignId_012 */ +/* Requirements : CONQ_QEP_SR12 */ +void eqepDisableUnitTimer( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_disable_unit_timer () function */ + +/** @brief Disable watchdog timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_013 */ +/* DesignId : EQEP_DesignId_013 */ +/* Requirements : CONQ_QEP_SR13 */ +void eqepDisableWatchdog( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_disable_watchdog () function */ + +/** @brief Enable capture + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_014 */ +/* DesignId : EQEP_DesignId_014 */ +/* Requirements : CONQ_QEP_SR14 */ +void eqepEnableCapture( eqepBASE_t * eqep ) +{ + eqep->QCAPCTL |= eQEP_QCAPCTL_CEN; + + return; +} /*end of eQEP_enable_capture () function */ + +/** @brief Enable counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_015 */ +/* DesignId : EQEP_DesignId_015 */ +/* Requirements : CONQ_QEP_SR15 */ +void eqepEnableCounter( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_QPEN; + + return; +} /*end of eQEP_enable_counter () function */ + +/** @brief Enable gating of index pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_016 */ +/* DesignId : EQEP_DesignId_016 */ +/* Requirements : CONQ_QEP_SR16 */ +void eqepEnableGateIndex( eqepBASE_t * eqep ) +{ + eqep->QDECCTL |= ( uint16 ) eQEP_Igate_Enable; + + return; +} /*end of eQEP_enable_gate_index () function */ + +/** @brief Enable individual interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT_type Individual interrupts + */ +/* SourceId : EQEP_SourceId_017 */ +/* DesignId : EQEP_DesignId_017 */ +/* Requirements : CONQ_QEP_SR17 */ +void eqepEnableInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QEINT |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_enable_interrupt () function */ + +/** @brief Enable position compare + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_018 */ +/* DesignId : EQEP_DesignId_018 */ +/* Requirements : CONQ_QEP_SR18 */ +void eqepEnablePosnCompare( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL |= eQEP_QPOSCTL_PCE; + + return; +} /*end of eQEP_enable_posn_compare () function */ + +/** @brief Enable position compare shadowing + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_019 */ +/* DesignId : EQEP_DesignId_019 */ +/* Requirements : CONQ_QEP_SR19 */ +void eqepEnablePosnCompareShadow( eqepBASE_t * eqep ) +{ + eqep->QPOSCTL |= eQEP_QPOSCTL_PCSHDW; + + return; +} /*end of eQEP_enable_posn_compare_shadow () function */ + +/** @brief Enable output sync pulse + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_020 */ +/* DesignId : EQEP_DesignId_020 */ +/* Requirements : CONQ_QEP_SR46 */ +void eqepEnableSyncOut( eqepBASE_t * eqep ) +{ + eqep->QDECCTL |= eQEP_QDECCTL_SOEN; + + return; +} /*end of eQEP_enable_sync_out () function */ + +/** @brief Enable unit timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_021 */ +/* DesignId : EQEP_DesignId_021 */ +/* Requirements : CONQ_QEP_SR20 */ +void eqepEnableUnitTimer( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_UTE; + + return; +} /*end of eQEP_enable_unit_timer () function */ + +/** @brief Enable watchdog timer + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_022 */ +/* DesignId : EQEP_DesignId_022 */ +/* Requirements : CONQ_QEP_SR21 */ +void eqepEnableWatchdog( eqepBASE_t * eqep ) +{ + eqep->QEPCTL |= eQEP_QEPCTL_WDE; + + return; +} /*end of eQEP_enable_watchdog () function */ + +/** @brief Manually force QEP interrupt + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Individual interrupt + */ +/* SourceId : EQEP_SourceId_023 */ +/* DesignId : EQEP_DesignId_023 */ +/* Requirements : CONQ_QEP_SR22 */ +void eqepForceInterrupt( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + eqep->QFRC |= ( uint16 ) QEINT_type; + + return; +} /*end of eQEP_force_interrupt () function */ + +/** @brief Reads capture period latch + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_024 */ +/* DesignId : EQEP_DesignId_024 */ +/* Requirements : CONQ_QEP_SR23 */ +uint16 eqepReadCapturePeriodLatch( eqepBASE_t * eqep ) +{ + return eqep->QCPRDLAT; +} /*end of eQEP_read_capture_period_latch () function */ + +/** @brief Reads timer latch + * @param[in] eqep Handle to QEP object + * @return Timer value + */ +/* SourceId : EQEP_SourceId_025 */ +/* DesignId : EQEP_DesignId_025 */ +/* Requirements : CONQ_QEP_SR24 */ +uint16 eqepReadCaptureTimerLatch( eqepBASE_t * eqep ) +{ + return eqep->QCTMRLAT; +} /*end of eQEP_read_capture_timer_latch () function */ + +/** @brief Reads interrupt flag value + * @param[in] eqep Handle to QEP object + * @param[in] QEINT Which interrupt to interrogate + * @return Interrupt flag value + */ +/* SourceId : EQEP_SourceId_064 */ +/* DesignId : EQEP_DesignId_064 */ +/* Requirements : CONQ_QEP_SR25 */ +uint16 eqepReadInterruptFlag( eqepBASE_t * eqep, QEINT_t QEINT_type ) +{ + return ( uint16 ) ( eqep->QFLG & ( uint16 ) QEINT_type ); +} /*end of eQEP_read_interrupt_flag () function */ + +/** @brief Reads position compare register + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_026 */ +/* DesignId : EQEP_DesignId_026 */ +/* Requirements : CONQ_QEP_SR26 */ +uint32 eqepReadPosnCompare( eqepBASE_t * eqep ) +{ + return eqep->QPOSCMP; +} /*end of eQEP_read_posn_compare () function */ + +/** @brief Reads position counter + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_027 */ +/* DesignId : EQEP_DesignId_027 */ +/* Requirements : CONQ_QEP_SR27 */ +uint32 eqepReadPosnCount( eqepBASE_t * eqep ) +{ + return eqep->QPOSCNT; +} /*end of eQEP_read_posn_count () function */ + +/** @brief Reads position counter value index pulse latch register + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_028 */ +/* DesignId : EQEP_DesignId_028 */ +/* Requirements : CONQ_QEP_SR28 */ +uint32 eqepReadPosnIndexLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSILAT; +} /*end of eQEP_read_posn_index_latch () function */ + +/** @brief Reads position counter value + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_029 */ +/* DesignId : EQEP_DesignId_029 */ +/* Requirements : CONQ_QEP_SR29 */ +uint32 eqepReadPosnLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSLAT; +} /*end of eQEP_read_posn_latch () function */ + +/** @brief Reads position strobe latch + * @param[in] eqep Handle to QEP object + * @return Counter value + */ +/* SourceId : EQEP_SourceId_030 */ +/* DesignId : EQEP_DesignId_030 */ +/* Requirements : CONQ_QEP_SR30 */ +uint32 eqepReadPosnStrobeLatch( eqepBASE_t * eqep ) +{ + return eqep->QPOSSLAT; +} /*end of eQEP_read_posn_strobe_latch () function */ + +/** @brief Reads status register + * @param[in] eqep Handle to QEP object + * @return Status register value + */ +/* SourceId : EQEP_SourceId_031 */ +/* DesignId : EQEP_DesignId_031 */ +/* Requirements : CONQ_QEP_SR31 */ +uint16 eqepReadStatus( eqepBASE_t * eqep ) +{ + return eqep->QEPSTS; +} /*end of eqepReadStatus () function */ + +/** @brief Resets counter + * @param[in] eqep Handle to QEP object + */ +/* SourceId : EQEP_SourceId_032 */ +/* DesignId : EQEP_DesignId_032 */ +/* Requirements : CONQ_QEP_SR32 */ +void eqepResetCounter( eqepBASE_t * eqep ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_QPEN; + + return; +} /*end of eqepResetCounter () function */ + +/** @brief Sets capture latch mode + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Qclm capture latch mode + */ +/* SourceId : EQEP_SourceId_033 */ +/* DesignId : EQEP_DesignId_033 */ +/* Requirements : CONQ_QEP_SR33 */ +void eqepSetCaptureLatchMode( eqepBASE_t * eqep, QEPCTL_Qclm_t QEPCTL_Qclm ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_QCLM; + eqep->QEPCTL |= QEPCTL_Qclm; + + return; +} /*end of eqepSetCaptureLatchMode () function */ + +/** @brief Sets capture period + * @param[in] eqep Handle to QEP object + * @param[in] period Capture period + */ +/* SourceId : EQEP_SourceId_034 */ +/* DesignId : EQEP_DesignId_034 */ +/* Requirements : CONQ_QEP_SR34 */ +void eqepSetCapturePeriod( eqepBASE_t * eqep, uint16 period ) +{ + eqep->QCPRD = period; + + return; +} /*end of eqepSetCapturePeriod () function */ + +/** @brief Sets capture pre-scaler + * @param[in] eqep Handle to QEP object + * @param[in] QCAPCTL_Ccps Capture pre-scaler + */ +/* SourceId : EQEP_SourceId_035 */ +/* DesignId : EQEP_DesignId_035 */ +/* Requirements : CONQ_QEP_SR35 */ +void eqepSetCapturePrescale( eqepBASE_t * eqep, QCAPCTL_Ccps_t QCAPCTL_Ccps ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_CCPS; + eqep->QCAPCTL |= QCAPCTL_Ccps; +} /*end of eqepSetCapturePrescale () function */ + +/** @brief Sets emulation control + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Freesoft Emulation control bits + */ +/* SourceId : EQEP_SourceId_036 */ +/* DesignId : EQEP_DesignId_036 */ +/* Requirements : CONQ_QEP_SR36 */ +void eqepSetEmuControl( eqepBASE_t * eqep, QEPCTL_Freesoft_t QEPCTL_Freesoft ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_FREESOFT; + eqep->QEPCTL |= QEPCTL_Freesoft; + + return; +} /*end of eqepSetEmuControl () function */ + +/** @brief Sets external clock rate + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Xcr External clock rate + */ +/* SourceId : EQEP_SourceId_037 */ +/* DesignId : EQEP_DesignId_037 */ +/* Requirements : CONQ_QEP_SR37 */ +void eqepSetExtClockRate( eqepBASE_t * eqep, eQEP_Xcr_t eQEP_Xcr ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_XCR; + eqep->QDECCTL |= ( uint16 ) eQEP_Xcr; + + return; +} /*end of eqepSetExtClockRate () function */ + +/** @brief Sets the event which initializes the counter register + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Iei Index event + */ +/* SourceId : EQEP_SourceId_038 */ +/* DesignId : EQEP_DesignId_038 */ +/* Requirements : CONQ_QEP_SR38 */ +void eqepSetIndexEventInit( eqepBASE_t * eqep, QEPCTL_Iei_t QEPCTL_Iei ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_IEI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Iei; + + return; +} /*end of eqepSetIndexEventInit () function */ + +/** @brief Sets the index event which latches the position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Iel Latch event + */ +/* SourceId : EQEP_SourceId_039 */ +/* DesignId : EQEP_DesignId_039 */ +/* Requirements : CONQ_QEP_SR39 */ +void eqepSetIndexEventLatch( eqepBASE_t * eqep, QEPCTL_Iel_t QEPCTL_Iel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_IEL; + eqep->QEPCTL |= QEPCTL_Iel; + + return; +} /*end of eqepSetIndexEventLatch */ + +/** @brief Sets index polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qip Index polarity + */ +/* SourceId : EQEP_SourceId_040 */ +/* DesignId : EQEP_DesignId_040 */ +/* Requirements : CONQ_QEP_SR40 */ +void eqepSetIndexPolarity( eqepBASE_t * eqep, eQEP_Qip_t eQEP_Qip ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QIP; + eqep->QDECCTL |= eQEP_Qip; + + return; +} /*end of eqepSetIndexPolarity () function */ + +/** @brief Sets max position count + * @param[in] eqep Handle to QEP object + * @param[in] max_count Maximum counter value + */ +/* SourceId : EQEP_SourceId_041 */ +/* DesignId : EQEP_DesignId_041 */ +/* Requirements : CONQ_QEP_SR41 */ +void eqepSetMaxPosnCount( eqepBASE_t * eqep, uint32 max_count ) +{ + eqep->QPOSMAX = max_count; + + return; +} /*end of eqepSetMaxPosnCount () function */ + +/** @brief Sets output pulse width when a match occur + * @param[in] eqep Handle to QEP object + * @param[in] pulse_width Pulse width value + */ +/* SourceId : EQEP_SourceId_042 */ +/* DesignId : EQEP_DesignId_042 */ +/* Requirements : CONQ_QEP_SR42 */ +void eqepSetPosnComparePulseWidth( eqepBASE_t * eqep, uint16 pulse_width ) +{ + uint16 pulse_width_masked; + + pulse_width_masked = pulse_width & 4095U; + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCSPW; + eqep->QPOSCTL |= pulse_width_masked; + + return; +} /*end of eqepSetPosnComparePulseWidth () function */ + +/** @brief Sets position compare shadow load mode + * @param[in] eqep Handle to QEP object + * @param[in] QPOSCTL_Pcload PC load event + */ +/* SourceId : EQEP_SourceId_043 */ +/* DesignId : EQEP_DesignId_043 */ +/* Requirements : CONQ_QEP_SR43 */ +void eqepSetPosnCompareShadowLoad( eqepBASE_t * eqep, QPOSCTL_Pcload_t QPOSCTL_Pcload ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCLOAD; + eqep->QPOSCTL |= ( uint16 ) QPOSCTL_Pcload; + + return; +} /*end of eqepSetPosnCompareShadowLoad () function */ + +/** @brief Sets position counter reset mode + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Pcrm Position counter reset mode + */ +/* SourceId : EQEP_SourceId_044 */ +/* DesignId : EQEP_DesignId_044 */ +/* Requirements : CONQ_QEP_SR44 */ +void eqepSetPosnCountResetMode( eqepBASE_t * eqep, QEPCTL_Pcrm_t QEPCTL_Pcrm ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_PCRM; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Pcrm; + + return; +} /*end of eqepSetPosnCountResetMode () function */ + +/** @brief Sets initial position counter value + * @param[in] eqep Handle to QEP object + * @param[in] init_count initial counter value + */ +/* SourceId : EQEP_SourceId_045 */ +/* DesignId : EQEP_DesignId_045 */ +/* Requirements : CONQ_QEP_SR45 */ +void eqepSetPosnInitCount( eqepBASE_t * eqep, uint32 init_count ) +{ + eqep->QPOSINIT = init_count; + + return; +} /*end of eqepSetPosnInitCount () function */ + +/** @brief Selects whether index or strobe pin is used for sync output + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_SPsel Selected pin + */ +/* SourceId : EQEP_SourceId_046 */ +/* DesignId : EQEP_DesignId_046 */ +/* Requirements : CONQ_QEP_SR47 */ +void eqepSetSelectSyncPin( eqepBASE_t * eqep, eQEP_Spsel_t eQEP_SPsel ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SPSEL; + eqep->QDECCTL |= ( uint16 ) eQEP_SPsel; + + return; +} /*end of eQEP_set_select_sync_pin () function */ + +/** @brief Determines if software initialization of position counter enabled + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Swi Enable/disable position counter initialization + */ +/* SourceId : EQEP_SourceId_047 */ +/* DesignId : EQEP_DesignId_047 */ +/* Requirements : CONQ_QEP_SR48 */ +void eqepSetSoftInit( eqepBASE_t * eqep, QEPCTL_Swi_t QEPCTL_Swi ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SWI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Swi; + + return; +} /*end of eQEP_set_soft_init () function */ + +/** @brief Determines strobe initialization of position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sei Strobe initialization of position counter (disabled, + * rising edge of QEPI) or rising/falling depending on direction + */ +/* SourceId : EQEP_SourceId_048 */ +/* DesignId : EQEP_DesignId_048 */ +/* Requirements : CONQ_QEP_SR49 */ +void eqepSetStrobeEventInit( eqepBASE_t * eqep, QEPCTL_Sei_t QEPCTL_Sei ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEI; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Sei; + + return; +} /*end of eQEP_set_strobe_event_init () function */ + +/** @brief Sets up strobe latch of position counter + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sel Sets strobe latch of position counter + */ +/* SourceId : EQEP_SourceId_049 */ +/* DesignId : EQEP_DesignId_049 */ +/* Requirements : CONQ_QEP_SR50 */ +void eqepSetStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= QEPCTL_Sel; + + return; +} /*end of eQEP_set_strobe_event_latch () function */ + +/** @brief Sets up strobe polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qsp Strobe polarity + */ +/* SourceId : EQEP_SourceId_050 */ +/* DesignId : EQEP_DesignId_050 */ +/* Requirements : CONQ_QEP_SR51 */ +void eqepSetStrobePolarity( eqepBASE_t * eqep, eQEP_Qsp_t eQEP_Qsp ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QSP; + eqep->QDECCTL |= eQEP_Qsp; + + return; +} /*end of eqepSetStrobePolarity () function */ + +/** @brief Sets up swapping of A/B channels + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Swap Swap/don't swap A/B channels + */ +/* SourceId : EQEP_SourceId_051 */ +/* DesignId : EQEP_DesignId_051 */ +/* Requirements : CONQ_QEP_SR52 */ +void eqepSetSwapQuadInputs( eqepBASE_t * eqep, eQEP_Swap_t eQEP_Swap ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_SWAP; + eqep->QDECCTL |= ( uint16 ) eQEP_Swap; + + return; +} /*end of eqepSetSwapQuadInputs () function */ + +/** @brief Sets sync output compare polarity + * @param[in] eqep Handle to QEP object + * @param[in] QPOSCTL_Pcpol Polarity of sync output + */ +/* SourceId : EQEP_SourceId_052 */ +/* DesignId : EQEP_DesignId_052 */ +/* Requirements : CONQ_QEP_SR53 */ +void eqepSetSynchOutputComparePolarity( eqepBASE_t * eqep, QPOSCTL_Pcpol_t QPOSCTL_Pcpol ) +{ + eqep->QPOSCTL &= ( uint16 ) ~eQEP_QPOSCTL_PCPOL; + eqep->QPOSCTL |= ( uint16 ) QPOSCTL_Pcpol; + + return; +} /*end of eqepSetSynchOutputComparePolarity () function */ + +/** @brief Sets unit timer period + * @param[in] eqep Handle to QEP object + * @param[in] unit_period Unit period + */ +/* SourceId : EQEP_SourceId_053 */ +/* DesignId : EQEP_DesignId_053 */ +/* Requirements : CONQ_QEP_SR54 */ +void eqepSetUnitPeriod( eqepBASE_t * eqep, uint32 unit_period ) +{ + eqep->QUPRD = unit_period; + + return; +} /*end of eqepSetUnitPeriod () function */ + +/** @brief Sets unit timer prescaling + * @param[in] eqep Handle to QEP object + * @param[in] QCAPCTL_Upps Unit timer prescaling + */ +/* SourceId : EQEP_SourceId_054 */ +/* DesignId : EQEP_DesignId_054 */ +/* Requirements : CONQ_QEP_SR55 */ +void eqepSetUnitPosnPrescale( eqepBASE_t * eqep, QCAPCTL_Upps_t QCAPCTL_Upps ) +{ + eqep->QCAPCTL &= ( uint16 ) ~eQEP_QCAPCTL_UPPS; + eqep->QCAPCTL |= ( uint16 ) QCAPCTL_Upps; + + return; +} /*end of eqepSetUnitPosnPrescale () function */ + +/** @brief Sets watchdog period + * @param[in] eqep Handle to QEP object + * @param[in] watchdog_period Watchdog period + */ +/* SourceId : EQEP_SourceId_055 */ +/* DesignId : EQEP_DesignId_055 */ +/* Requirements : CONQ_QEP_SR56 */ +void eqepSetWatchdogPeriod( eqepBASE_t * eqep, uint16 watchdog_period ) +{ + eqep->QWDPRD = watchdog_period; + + return; +} /*end of eqepSetWatchdogPeriod () function */ + +/** @brief Sets strobe event latch + * @param[in] eqep Handle to QEP object + * @param[in] QEPCTL_Sel Sets strobe latch of position counter + */ +/* SourceId : EQEP_SourceId_056 */ +/* DesignId : EQEP_DesignId_056 */ +/* Requirements : CONQ_QEP_SR57 */ +void eqepSetupStrobeEventLatch( eqepBASE_t * eqep, QEPCTL_Sel_t QEPCTL_Sel ) +{ + eqep->QEPCTL &= ( uint16 ) ~eQEP_QEPCTL_SEL; + eqep->QEPCTL |= ( uint16 ) QEPCTL_Sel; + + return; +} /*end of eqepSetupStrobeEventLatch () function */ + +/** @brief Sets A polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qap Channel A polarity + */ +/* SourceId : EQEP_SourceId_057 */ +/* DesignId : EQEP_DesignId_057 */ +/* Requirements : CONQ_QEP_SR58 */ +void eqepSetAPolarity( eqepBASE_t * eqep, eQEP_Qap_t eQEP_Qap ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QAP; + eqep->QDECCTL |= ( uint16 ) eQEP_Qap; + + return; +} /*end of eqepSetAPolarity () function */ + +/** @brief Sets B polarity + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qbp Channel B polarity + */ +/* SourceId : EQEP_SourceId_058 */ +/* DesignId : EQEP_DesignId_058 */ +/* Requirements : CONQ_QEP_SR59 */ +void eqepSetBPolarity( eqepBASE_t * eqep, eQEP_Qbp_t eQEP_Qbp ) +{ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QBP; + eqep->QDECCTL |= ( uint16 ) eQEP_Qbp; + + return; +} /*end of eQEP_set_B_polarity () function */ + +/** @brief Set QEP counting mode + * @param[in] eqep Handle to QEP object + * @param[in] eQEP_Qsrc Sets QEP counting mode + */ +/* SourceId : EQEP_SourceId_059 */ +/* DesignId : EQEP_DesignId_059 */ +/* Requirements : CONQ_QEP_SR60 */ +void eqepSetQEPSource( eqepBASE_t * eqep, eQEP_Qsrc_t eQEP_Qsrc ) +{ + /* set the value */ + eqep->QDECCTL &= ( uint16 ) ~eQEP_QDECCTL_QSRC; + eqep->QDECCTL |= ( uint16 ) eQEP_Qsrc; + + return; +} /*end of eQEP_set_eQEP_source () function */ + +/** @brief Writes a value to the position compare register + * @param[in] eqep Handle to QEP object + * @param[in] posn Position compare register value + */ +/* SourceId : EQEP_SourceId_060 */ +/* DesignId : EQEP_DesignId_060 */ +/* Requirements : CONQ_QEP_SR61 */ +void eqepWritePosnCompare( eqepBASE_t * eqep, uint32 posn ) +{ + eqep->QPOSCMP = posn; + + return; +} /*end of eQEP_write_posn_compare () function */ + +/** @fn void eqep1GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EQEP_SourceId_061 */ +/* DesignId : EQEP_DesignId_061 */ +/* Requirements : CONQ_QEP_SR64 */ +void eqep1GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_QPOSINIT = EQEP1_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP1_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP1_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP1_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP1_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP1_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP1_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP1_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP1_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP1_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG1->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG1->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG1->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG1->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG1->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG1->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG1->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG1->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG1->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG1->QEINT; + } +} + +/** @fn void eqep2GetConfigValue(eqep_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : EQEP_SourceId_062 */ +/* DesignId : EQEP_DesignId_062 */ +/* Requirements : CONQ_QEP_SR65 */ +void eqep2GetConfigValue( eqep_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_QPOSINIT = EQEP2_QPOSINIT_CONFIGVALUE; + config_reg->CONFIG_QPOSMAX = EQEP2_QPOSMAX_CONFIGVALUE; + config_reg->CONFIG_QPOSCMP = EQEP2_QPOSCMP_CONFIGVALUE; + config_reg->CONFIG_QUPRD = EQEP2_QUPRD_CONFIGVALUE; + config_reg->CONFIG_QWDPRD = EQEP2_QWDPRD_CONFIGVALUE; + config_reg->CONFIG_QDECCTL = EQEP2_QDECCTL_CONFIGVALUE; + config_reg->CONFIG_QEPCTL = EQEP2_QEPCTL_CONFIGVALUE; + config_reg->CONFIG_QCAPCTL = EQEP2_QCAPCTL_CONFIGVALUE; + config_reg->CONFIG_QPOSCTL = EQEP2_QPOSCTL_CONFIGVALUE; + config_reg->CONFIG_QEINT = EQEP2_QEINT_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_QPOSINIT = eqepREG2->QPOSINIT; + config_reg->CONFIG_QPOSMAX = eqepREG2->QPOSMAX; + config_reg->CONFIG_QPOSCMP = eqepREG2->QPOSCMP; + config_reg->CONFIG_QUPRD = eqepREG2->QUPRD; + config_reg->CONFIG_QWDPRD = eqepREG2->QWDPRD; + config_reg->CONFIG_QDECCTL = eqepREG2->QDECCTL; + config_reg->CONFIG_QEPCTL = eqepREG2->QEPCTL; + config_reg->CONFIG_QCAPCTL = eqepREG2->QCAPCTL; + config_reg->CONFIG_QPOSCTL = eqepREG2->QPOSCTL; + config_reg->CONFIG_QEINT = eqepREG2->QEINT; + } +} + +/*end of file*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c new file mode 100644 index 00000000000..b5bb5023b4d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata.c @@ -0,0 +1,273 @@ +/** @file errata.c + * @brief Errata workaround Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Errata workaround API's + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "errata.h" +#include "sys_core.h" +#include "sys_pmu.h" + +/** @fn void errataFailNotification(uint32 flag) + * @brief Errata fail service routine + * + * This function is called if there is a errata workaround fail with appropriate flag + */ +void errataFailNotification( uint32 flag ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/** @fn void errata_PBIST_4(void) + * @brief Workaround for the Errata PBIST#4. + * + * This function is workaround for Errata PBIST#4. + * This function is designed to initialize the ROMs using the PBIST controller. + * The CPU will configure the PBIST controller to test the PBIST ROM and STC ROM. + * This function should be called at startup after system init before using the ROMs. + * + * @note : This Function uses register's which are not exposed to users through + * TRM , to run custom algorithm. User can use this function as Black box. + * + */ +void errata_PBIST_4( void ) +{ + volatile uint32 i = 0U; + uint8 ROM_count; + sint32 PBIST_wait_done_loop; + uint32 pmuCalibration, pmuCount; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* PMU calibration */ + _pmuInit_(); + _pmuEnableCountersGlobal_(); + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + _pmuStopCounters_( pmuCYCLE_COUNTER ); + pmuCalibration = _pmuGetCycleCount_(); + + /* ROM_init Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + *( volatile uint32 * ) 0xFFFF0400U = 0x0000000AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000EE0AU; + + /* Loop for Executing PBIST ROM and STC ROM */ + for( ROM_count = 0U; ROM_count < 4U; ROM_count++ ) + { + PBIST_wait_done_loop = 0; + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* PBIST Clocks did not disable */ + if( pbistREG->PACT != 0x0U ) + { + errataFailNotification( PBISTERRATA_FAIL3 ); + } + else + { + /* PBIST ROM clock frequency = GCLK frequency /4 */ + /* Disable memory self controller */ + systemREG1->MSTGCR = 0x00000205U; + + /* Disable Memory Initialization controller */ + systemREG1->MINITGCR = 0x5U; + + /* Enable memory self controller */ + systemREG1->MSTGCR = 0x0000020AU; + + /* Clear PBIST Done */ + systemREG1->MSTCGSTAT = 0x1U; + + /* Enable PBIST controller */ + systemREG1->MSINENA = 0x1U; + + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /*SAFETYMCUSW 134 S MR:12.2 "Wait for few clock cycles (Value of i + * not used)" */ + /* wait for 64 VBUS clock cycles at least, based on HCLK to VCLK ratio */ + for( i = 0U; i < ( 64U + ( 64U * 1U ) ); i++ ) + { /* Wait */ + } + + /* Enable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x3U; + + /* CPU control of PBIST */ + pbistREG->DLR = 0x10U; + + /* Load PBIST ALGO to initialize the ROMs */ + *( volatile uint32 * ) 0xFFFFE400U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE440U = 0x00000025U; + *( volatile uint32 * ) 0xFFFFE404U = 0x62400001U; + *( volatile uint32 * ) 0xFFFFE444U = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE408U = 0x00068003U; + *( volatile uint32 * ) 0xFFFFE448U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE40CU = 0x00000004U; + *( volatile uint32 * ) 0xFFFFE44CU = 0x00006860U; + *( volatile uint32 * ) 0xFFFFE410U = 0x00000000U; + *( volatile uint32 * ) 0xFFFFE450U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE540U = 0x000003E8U; + *( volatile uint32 * ) 0xFFFFE550U = 0x00000001U; + *( volatile uint32 * ) 0xFFFFE530U = 0x00000000U; + + /* SELECT ROM */ + if( ROM_count == 0U ) + { + /* SELECT STC1 ROM1 */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x07B3FFFFU; + pbistREG->RAMT = 0x0E01200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else if( ROM_count == 1U ) + { + /* SELECT STC1 ROM2 */ + *( volatile uint32 * ) 0xFFFFE520U = 0xA88FA473U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00BD719DU; + pbistREG->RAMT = 0x0E02200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 2U; /* CSR */ + } + else if( ROM_count == 2U ) + { + /* SELECT STC2 ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0xFFF0007CU; + *( volatile uint32 * ) 0xFFFFE524U = 0x06E3FFFFU; + pbistREG->RAMT = 0x0F01200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else if( ROM_count == 3U ) + { + /* SELECT PBIST ROM */ + *( volatile uint32 * ) 0xFFFFE520U = 0x00000002U; + *( volatile uint32 * ) 0xFFFFE524U = 0x00000000U; + pbistREG->RAMT = 0x0101200CU; + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 4U ] = 1U; /* CSR */ + } + else + { + /* Empty */ + } + + /* Setup using special reserved registers as part of errata fix */ + /* (Only to be used in this function) */ + pbistREG->rsvd1[ 0U ] = 8U; /* CMS */ + + /* Start PMU counter */ + _pmuResetCounters_(); + _pmuStartCounters_( pmuCYCLE_COUNTER ); + + /* PBIST_RUN */ + pbistREG->rsvd1[ 1U ] = 1U; + + /* wait until memory self-test done is indicated */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->MSTCGSTAT & 0x1U ) != 0x1U ) + { + } /* Wait */ + + /* Stop PMU counter */ + _pmuStopCounters_( pmuCYCLE_COUNTER ); + + /* Get CPU cycle count */ + pmuCount = _pmuGetCycleCount_(); + + /* Calculate PBIST test complete time in ROM Clock */ + /* 4 - Divide value ( Default is 4 in HALCoGen) */ + /* 1000 = 0x3E8 - Test Loop count in ROM Algorithm */ + pmuCount = pmuCount - pmuCalibration; + PBIST_wait_done_loop = ( ( sint32 ) pmuCount / 4 ) - 1000; + + /* Check PBIST status results (Address, Status, Count, etc...) */ + if( ( pbistREG->FSRA0 | pbistREG->FSRA1 | pbistREG->FSRDL0 | pbistREG->rsvd3 + | pbistREG->FSRDL1 | pbistREG->rsvd4[ 0U ] | pbistREG->rsvd4[ 1U ] ) + != 0U ) + { + /* PBIST Failure for the Algorithm chosen above */ + errataFailNotification( PBISTERRATA_FAIL1 ); + } + + /* Check that the algorithm executed in the expected amount of time. */ + /* This time is dependent on the ROMCLKDIV selected */ + if( ( PBIST_wait_done_loop <= 20 ) || ( PBIST_wait_done_loop >= 200 ) ) + { + errataFailNotification( PBISTERRATA_FAIL2 ); + } + + /* Disable PBIST clocks and ROM clock */ + pbistREG->PACT = 0x0U; + + /* Disable PBIST */ + systemREG1->MSTGCR &= 0xFFFFFFF0U; + systemREG1->MSTGCR |= 0x5U; + } + } /* ROM Loop */ + + /* ROM restore default setup */ + /* (must be completed before continuing) */ + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA0AU; + *( volatile uint32 * ) 0xFFFF040CU = 0x0000AA05U; + *( volatile uint32 * ) 0xFFFF0400U = 0x00000005U; + + _pmuDisableCountersGlobal_(); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c new file mode 100644 index 00000000000..3fada34da53 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/errata_SSWF021_45.c @@ -0,0 +1,374 @@ +/** @file errata_SSWF021_45.c + * @brief errata for PLLs + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include "errata_SSWF021_45_defs.h" +#include "errata_SSWF021_45.h" + +static uint32 check_frequency( uint32 cnt1_clksrc ); +static uint32 disable_plls( uint32 plls ); + +/** @fn uint32 _errata_SSWF021_45_both_plls(uint32 count) +* @brief This handles the errata for PLL1 and PLL2. This function is called in device +startup +* +* @param[in] count : Number of retries until both PLLs are locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_both_plls( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while( ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + || ( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) == 0U ) ) ) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll1(uint32 count) +* @brief This handles the errata for PLL1. This function is called in device startup +* +* @param[in] count : Number of retries until both PLL1 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll1( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + systemREG1->PLLCTL1 = 0x20001A00U; + systemREG1->PLLCTL2 = 0x3FC0723DU; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL1; + /* Check for PLL1 valid or PLL1 slip*/ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL1 ) == 0U ) + && ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) == 0U ) ) + { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if( ( ( esmREG->SR1[ 0U ] & ESM_SR1_PLL1SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 1U; + } + else + { + failCode |= check_frequency( dcc1CNT1_CLKSRC_PLL1 ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL1 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 _errata_SSWF021_45_pll2(uint32 count) +* @brief This handles the errata for PLL2. This function is called in device startup +* +* @param[in] count : Number of retries until PLL2 is locked successfully +* Minimum value recommended is 5 +* +* @return 0 = Success (the PLL or both PLLs have successfully locked and then been +disabled) +* 1 = PLL1 failed to successfully lock in "count" tries +* 2 = PLL2 failed to successfully lock in "count" tries +* 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries +* 4 = The workaround function was not able to disable at least one of the PLLs. +The most likely reason is that a PLL is already being used as a clock source. This can be +caused by the workaround function being called from the wrong place in the code. +*/ +uint32 _errata_SSWF021_45_pll2( uint32 count ) +{ + uint32 failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = systemREG1->CLKCNTL; + /* First set VCLK2 = HCLK */ + systemREG1->CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + systemREG1->CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for( retries = 0U; ( retries < count ); retries++ ) + { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + if( failCode != 0U ) + { + break; + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + systemREG2->PLLCTL3 = 0x20001A00U; + systemREG1->CSDISCLR = SYS_CLKSRC_PLL2; + /* Check for PLL2 valid or PLL2 slip */ + while( ( ( systemREG1->CSVSTAT & SYS_CLKSRC_PLL2 ) == 0U ) + && ( ( esmREG->SR4[ 0 ] & ESM_SR4_PLL2SLIP ) == 0U ) ) + { + /* Wait */ + } + /* If PLL2 valid, check the frequency */ + if( ( ( esmREG->SR4[ 0U ] & ESM_SR4_PLL2SLIP ) != 0U ) + || ( ( systemREG1->GBLSTAT & 0x00000300U ) != 0U ) ) + { + failCode |= 2U; + } + else + { + failCode |= ( check_frequency( dcc1CNT1_CLKSRC_PLL2 ) << 1U ); + } + if( failCode == 0U ) + { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls( SYS_CLKSRC_PLL2 ); + /* restore CLKCNTL, VCLKR and PENA first */ + systemREG1->CLKCNTL = ( clkCntlSav & 0x000F0100U ); + /* restore CLKCNTL, VCLK2R */ + systemREG1->CLKCNTL = clkCntlSav; + return failCode; +} +/** @fn uint32 check_frequency(uint32 cnt1_clksrc) + * @brief This function checks for the PLL frequency. + * + * @param[in] cnt1_clksrc : Clock source for Counter1 + * 0U - PLL1 (clock source 0) + * 1U - PLL2 (clock source 1) + * + * @return DCC Error status + * 0 - DCC error has not occurred + * 1 - DCC error has occurred + */ +static uint32 check_frequency( uint32 cnt1_clksrc ) +{ + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0x5U | /** Disable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + dccREG1->STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + dccREG1->CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + dccREG1->VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + dccREG1->CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + dccREG1->CNT1CLKSRC = ( uint32 ) ( ( uint32 ) 10U << 12U ) | /** DCC Enable / Disable + Key */ + ( uint32 ) cnt1_clksrc; /** DCC1 Clock Source 1 */ + + dccREG1->CNT0CLKSRC = ( uint32 ) DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + dccREG1->GCTRL = ( uint32 ) 0xAU | /** Enable DCC1 */ + ( uint32 ) ( ( uint32 ) 0x5U << 4U ) | /** No Error Interrupt */ + ( uint32 ) ( ( uint32 ) 0xAU << 8U ) | /** Single Shot mode */ + ( uint32 ) ( ( uint32 ) 0x5U << 12U ); /** No Done Interrupt */ + while( dccREG1->STAT == 0U ) + { + /* Wait */ + } + return ( dccREG1->STAT & 0x01U ); +} +/** @fn uint32 disable_plls(uint32 plls) + * @brief This function disables plls and clears the respective ESM flags. + * + * @param[in] plls : Clock source for Counter1 + * 2U - PLL1 + * 40U - PLL2 + * + * @return failCode + * 0 = Success (the PLL or both PLLs have successfully locked and then been + * disabled) 4 = The workaround function was not able to disable at least one of the PLLs. + * The most likely reason is that a PLL is already being used as a clock source. This can + * be caused by the workaround function being called from the wrong place in the code. + */ +static uint32 disable_plls( uint32 plls ) +{ + uint32 timeout, failCode; + + systemREG1->CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout--; + while( ( ( systemREG1->CSVSTAT & ( plls ) ) != 0U ) && ( timeout != 0U ) ) + { + /* Clear ESM and GLBSTAT PLL slip flags */ + systemREG1->GBLSTAT = 0x00000300U; + + if( ( plls & SYS_CLKSRC_PLL1 ) == SYS_CLKSRC_PLL1 ) + { + esmREG->SR1[ 0U ] = ESM_SR1_PLL1SLIP; + } + if( ( plls & SYS_CLKSRC_PLL2 ) == SYS_CLKSRC_PLL2 ) + { + esmREG->SR4[ 0U ] = ESM_SR4_PLL2SLIP; + } + timeout--; + /* Wait */ + } + if( timeout == 0U ) + { + failCode = 4U; + } + else + { + failCode = 0U; + } + return failCode; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c new file mode 100644 index 00000000000..8cf11f1fcda --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/esm.c @@ -0,0 +1,1068 @@ +/** @file esm.c + * @brief Esm Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the Esm driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "esm.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void esmInit(void) + * @brief Initializes Esm Driver + * + * This function initializes the Esm driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : ESM_SourceId_001 */ +/* DesignId : ESM_DesignId_001 */ +/* Requirements : CONQ_ESM_SR2 */ +void esmInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Disable error pin channels */ + esmREG->DEPAPR1 = 0xFFFFFFFFU; + esmREG->IEPCR4 = 0xFFFFFFFFU; + esmREG->IEPCR7 = 0xFFFFFFFFU; + + /** - Disable interrupts */ + esmREG->IECR1 = 0xFFFFFFFFU; + esmREG->IECR4 = 0xFFFFFFFFU; + esmREG->IECR7 = 0xFFFFFFFFU; + + /** - Clear error status flags */ + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SSR2 = 0xFFFFFFFFU; + esmREG->SR1[ 2U ] = 0xFFFFFFFFU; + + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + + /** - Setup LPC preload */ + esmREG->LTCPR = 16384U - 1U; + + /** - Reset error pin */ + if( esmREG->EPSR == 0U ) + { + esmREG->EKR = 0x00000005U; + } + else + { + esmREG->EKR = 0x00000000U; + } + + /** - Clear interrupt level */ + esmREG->ILCR1 = 0xFFFFFFFFU; + esmREG->ILCR4 = 0xFFFFFFFFU; + esmREG->ILCR7 = 0xFFFFFFFFU; + + /** - Set interrupt level */ + esmREG->ILSR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->ILSR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable error pin channels */ + esmREG->EEPAPR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IEPSR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Enable interrupts */ + esmREG->IESR1 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR4 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + esmREG->IESR7 = ( uint32 ) ( ( uint32 ) 0U << 31U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn uint32 esmError(void) + * @brief Return Error status + * + * @return The error status + * + * Returns the error status. + */ +/* SourceId : ESM_SourceId_002 */ +/* DesignId : ESM_DesignId_002 */ +/* Requirements : CONQ_ESM_SR3 */ +uint32 esmError( void ) +{ + uint32 status; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + status = esmREG->EPSR; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_003 */ +/* DesignId : ESM_DesignId_003 */ +/* Requirements : CONQ_ESM_SR4 */ +void esmEnableError( uint64 channels ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + esmREG->IEPSR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->EEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/** @fn void esmEnableError(uint64 channels) + * @brief Enable Group 1 Channels Error Signals propagation for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_004 */ +/* DesignId : ESM_DesignId_004 */ +/* Requirements : CONQ_ESM_SR4 */ +void esmEnableErrorUpper( uint64 channels ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + esmREG->IEPSR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_005 */ +/* DesignId : ESM_DesignId_005 */ +/* Requirements : CONQ_ESM_SR5 */ +void esmDisableError( uint64 channels ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + esmREG->IEPCR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->DEPAPR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/** @fn void esmDisableError(uint64 channels) + * @brief Disable Group 1 Channels Error Signals propagation for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Error Signals propagation to the error pin. + */ +/* SourceId : ESM_SourceId_006 */ +/* DesignId : ESM_DesignId_006 */ +/* Requirements : CONQ_ESM_SR5 */ +void esmDisableErrorUpper( uint64 channels ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + esmREG->IEPCR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} +/** @fn void esmTriggerErrorPinReset(void) + * @brief Trigger error pin reset and switch back to normal operation + * + * Trigger error pin reset and switch back to normal operation. + */ +/* SourceId : ESM_SourceId_007 */ +/* DesignId : ESM_DesignId_007 */ +/* Requirements : CONQ_ESM_SR6 */ +void esmTriggerErrorPinReset( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + esmREG->EKR = 5U; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/** @fn void esmActivateNormalOperation(void) + * @brief Activate normal operation + * + * Activates normal operation mode. + */ +/* SourceId : ESM_SourceId_008 */ +/* DesignId : ESM_DesignId_008 */ +/* Requirements : CONQ_ESM_SR7 */ +void esmActivateNormalOperation( void ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + esmREG->EKR = 0U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_009 */ +/* DesignId : ESM_DesignId_009 */ +/* Requirements : CONQ_ESM_SR8 */ +void esmEnableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + esmREG->IESR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IESR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/** @fn void esmEnableInterrupt(uint64 channels) + * @brief Enable Group 1 Channels Interrupts for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Enable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_010 */ +/* DesignId : ESM_DesignId_010 */ +/* Requirements : CONQ_ESM_SR8 */ +void esmEnableInterruptUpper( uint64 channels ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + esmREG->IESR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} +/** @fn void esmDisableInterrupt(uint32 channels) + * @brief Disable Group 1 Channels Interrupts for channels 0-63 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_011 */ +/* DesignId : ESM_DesignId_011 */ +/* Requirements : CONQ_ESM_SR9 */ +void esmDisableInterrupt( uint64 channels ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + esmREG->IECR4 = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + esmREG->IECR1 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/** @fn void esmDisableInterrupt(uint64 channels) + * @brief Disable Group 1 Channels Interrupts for channels 64-95 + * + * @param[in] channels - Channel mask + * + * Disable Group 1 Channels Interrupts. + */ +/* SourceId : ESM_SourceId_012 */ +/* DesignId : ESM_DesignId_012 */ +/* Requirements : CONQ_ESM_SR9 */ +void esmDisableInterruptUpper( uint64 channels ) +{ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + esmREG->IECR7 = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels for channels 0-63 + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_013 */ +/* DesignId : ESM_DesignId_013 */ +/* Requirements : CONQ_ESM_SR10 */ +void esmSetInterruptLevel( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + esmREG->ILCR4 = ( uint32 ) ( ( ( channels & ( ~flags ) ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILSR4 = ( uint32 ) ( ( ( channels & flags ) >> 32U ) & 0xFFFFFFFFU ); + esmREG->ILCR1 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR1 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/** @fn void esmSetInterruptLevel(uint64 channels, uint64 flags) + * @brief Set Group 1 Channels Interrupt Levels for channels 64-95 + * + * @param[in] channels - Channel mask + * @param[in] flags - Level mask: - 0: Low priority interrupt + * - 1: High priority interrupt + * + * Set Group 1 Channels Interrupts levels. + */ +/* SourceId : ESM_SourceId_014 */ +/* DesignId : ESM_DesignId_014 */ +/* Requirements : CONQ_ESM_SR10 */ +void esmSetInterruptLevelUpper( uint64 channels, uint64 flags ) +{ + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + esmREG->ILCR7 = ( uint32 ) ( ( channels & ( ~flags ) ) & 0xFFFFFFFFU ); + esmREG->ILSR7 = ( uint32 ) ( ( channels & flags ) & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatus(uint32 group, uint32 channels) + * @brief Clear Group error status + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_015 */ +/* DesignId : ESM_DesignId_015 */ +/* Requirements : CONQ_ESM_SR14 */ +void esmClearStatus( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + esmREG->SR1[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + if( group == 0U ) + { + esmREG->SR4[ group ] = ( uint32 ) ( ( channels >> 32U ) & 0xFFFFFFFFU ); + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} + +/** @fn void esmClearStatusUpper(uint32 group, uint64 channels) + * @brief Clear Group error status for channels 64-95 + * + * @param[in] group - Error group + * @param[in] channels - Channel mask + * + * Clear Group error status. + */ +/* SourceId : ESM_SourceId_016 */ +/* DesignId : ESM_DesignId_016 */ +/* Requirements : CONQ_ESM_SR14 */ +void esmClearStatusUpper( uint32 group, uint64 channels ) +{ + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + esmREG->SR7[ group ] = ( uint32 ) ( channels & 0xFFFFFFFFU ); + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ +} +/** @fn void esmClearStatusBuffer(uint32 channels) + * @brief Clear Group 2 error status buffer + * + * @param[in] channels - Channel mask + * + * Clear Group 2 error status buffer. + */ +/* SourceId : ESM_SourceId_017 */ +/* DesignId : ESM_DesignId_017 */ +/* Requirements : CONQ_ESM_SR15 */ +void esmClearStatusBuffer( uint32 channels ) +{ + /* USER CODE BEGIN (35) */ + /* USER CODE END */ + + esmREG->SSR2 = channels; + + /* USER CODE BEGIN (36) */ + /* USER CODE END */ +} + +/** @fn void esmSetCounterPreloadValue(uint32 value) + * @brief Set counter preload value + * + * @param[in] value - Counter preload value + * + * Set counter preload value. + */ +/* SourceId : ESM_SourceId_018 */ +/* DesignId : ESM_DesignId_018 */ +/* Requirements : CONQ_ESM_SR11 */ +void esmSetCounterPreloadValue( uint32 value ) +{ + /* USER CODE BEGIN (37) */ + /* USER CODE END */ + + esmREG->LTCPR = value & 0xC000U; + + /* USER CODE BEGIN (38) */ + /* USER CODE END */ +} + +/** @fn uint64 esmGetStatus(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group (Channels from 0-63) + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_019 */ +/* DesignId : ESM_DesignId_019 */ +/* Requirements : CONQ_ESM_SR12 */ +uint64 esmGetStatus( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS4, ESM_ESTATUS1; + if( group == 0U ) + { + ESM_ESTATUS4 = esmREG->SR4[ group ]; + } + else + { + ESM_ESTATUS4 = 0U; + } + ESM_ESTATUS1 = esmREG->SR1[ group ]; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( ( ( uint64 ) ESM_ESTATUS4 ) << 32U ) | ( uint64 ) ESM_ESTATUS1 ) + & channels; + + /* USER CODE BEGIN (40) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusUpper(uint32 group, uint64 channels) + * @brief Return Error status + * + * @param[in] group - Error group + * @param[in] channels - Error Channels + * + * @return The channels status of selected group (Channels from 64-95) + * + * Returns the channels status of selected group. + */ +/* SourceId : ESM_SourceId_020 */ +/* DesignId : ESM_DesignId_020 */ +/* Requirements : CONQ_ESM_SR12 */ +uint64 esmGetStatusUpper( uint32 group, uint64 channels ) +{ + uint64 status; + uint32 ESM_ESTATUS7 = esmREG->SR7[ group ]; + + /* USER CODE BEGIN (41) */ + /* USER CODE END */ + /*SAFETYMCUSW 51 S MR:12.3 "Needs shifting for 64-bit value" */ + status = ( ( uint64 ) ESM_ESTATUS7 ) & channels; + + /* USER CODE BEGIN (42) */ + /* USER CODE END */ + + return status; +} + +/** @fn uint64 esmGetStatusBuffer(uint64 channels) + * @brief Return Group 2 channel x Error status buffer + * + * @param[in] channels - Error Channels + * + * @return The channels status + * + * Returns the group 2 buffered status of selected channels. + */ +/* SourceId : ESM_SourceId_021 */ +/* DesignId : ESM_DesignId_021 */ +/* Requirements : CONQ_ESM_SR17 */ +uint32 esmGetStatusBuffer( uint32 channels ) +{ + uint32 status; + + /* USER CODE BEGIN (43) */ + /* USER CODE END */ + status = esmREG->SSR2 & channels; + + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmEnterSelfTest(void) + * @brief Return ESM Self test status + * + * @return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_022 */ +/* DesignId : ESM_DesignId_022 */ +/* Requirements : CONQ_ESM_SR16 */ +esmSelfTestFlag_t esmEnterSelfTest( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (45) */ + /* USER CODE END */ + + uint32 errPinStat = esmREG->EPSR & 0x1U; + uint32 esmKeyReg = esmREG->EKR; + if( ( errPinStat == 0x0U ) && ( esmKeyReg == 0x0U ) ) + { + status = esmSelfTest_NotStarted; + } + else + { + esmREG->EKR = 0xAU; + status = esmSelfTest_Active; + if( ( esmREG->EPSR & 0x1U ) != 0x0U ) + { + status = esmSelfTest_Failed; + } + esmREG->EKR = 0x5U; + } + + /* USER CODE BEGIN (46) */ + /* USER CODE END */ + + return status; +} + +/** @fn esmSelfTestFlag_t esmSelfTestStatus(void) + * @brief Return ESM Self test status + * + * Returns the ESM Self test status. + */ +/* SourceId : ESM_SourceId_023 */ +/* DesignId : ESM_DesignId_023 */ +/* Requirements : CONQ_ESM_SR17 */ +esmSelfTestFlag_t esmSelfTestStatus( void ) +{ + esmSelfTestFlag_t status; + + /* USER CODE BEGIN (47) */ + /* USER CODE END */ + + if( ( esmREG->EPSR & 0x1U ) == 0x0U ) + { + if( esmREG->EKR == 0x5U ) + { + status = esmSelfTest_Active; + } + else + { + status = esmSelfTest_Failed; + } + } + else + { + status = esmSelfTest_Passed; + } + + /* USER CODE BEGIN (48) */ + /* USER CODE END */ + + return status; +} + +/** @fn void esmGetConfigValue(esm_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +/* SourceId : ESM_SourceId_024 */ +/* DesignId : ESM_DesignId_024 */ +/* Requirements : CONQ_ESM_SR18 */ +void esmGetConfigValue( esm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_EEPAPR1 = ESM_EEPAPR1_CONFIGVALUE; + config_reg->CONFIG_IESR1 = ESM_IESR1_CONFIGVALUE; + config_reg->CONFIG_ILSR1 = ESM_ILSR1_CONFIGVALUE; + config_reg->CONFIG_LTCPR = ESM_LTCPR_CONFIGVALUE; + config_reg->CONFIG_EKR = ESM_EKR_CONFIGVALUE; + config_reg->CONFIG_IEPSR4 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR4 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR4 = ESM_ILSR4_CONFIGVALUE; + config_reg->CONFIG_IEPSR7 = ESM_IEPSR4_CONFIGVALUE; + config_reg->CONFIG_IESR7 = ESM_IESR4_CONFIGVALUE; + config_reg->CONFIG_ILSR7 = ESM_ILSR4_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_EEPAPR1 = esmREG->EEPAPR1; + config_reg->CONFIG_IESR1 = esmREG->IESR1; + config_reg->CONFIG_ILSR1 = esmREG->ILSR1; + config_reg->CONFIG_LTCPR = esmREG->LTCPR; + config_reg->CONFIG_EKR = esmREG->EKR; + config_reg->CONFIG_IEPSR4 = esmREG->IEPSR4; + config_reg->CONFIG_IESR4 = esmREG->IESR4; + config_reg->CONFIG_ILSR4 = esmREG->ILSR4; + config_reg->CONFIG_IEPSR7 = esmREG->IEPSR7; + config_reg->CONFIG_IESR7 = esmREG->IESR7; + config_reg->CONFIG_ILSR7 = esmREG->ILSR7; + } +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/** @fn void esmHighInterrupt(void) + * @brief High Level Interrupt for ESM + */ + +/* SourceId : ESM_SourceId_025 */ +/* DesignId : ESM_DesignId_025 */ +/* Requirements : CONQ_ESM_SR19 */ +void esmHighInterrupt( void ) +{ + /* Note : Group 1 Error */ + /* 1 to 32 -> channel 0 to 31 */ + /* 65 to 96 -> channel 32 to 63 */ + /* 129 to 160 -> channel 64 to 95 */ + /* Note : Group 2 Error */ + /* 33 to 64 -> channel 0 to 31 */ + + uint32 vec = esmREG->IOFFHR - 1U; + + /* USER CODE BEGIN (50) */ + /* USER CODE END */ + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( esmREG, ( vec ) ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( esmREG, ( vec - 32U ) ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( esmREG, ( vec - 32U ) ); + } + else if( ( vec >= 128U ) && ( vec < 160U ) ) + { + esmREG->SR7[ 0U ] = ( uint32 ) 1U << ( vec - 128U ); + esmGroup1Notification( esmREG, ( vec - 96U ) ); + } + else + { + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (55) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c new file mode 100644 index 00000000000..9acbe119a7d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/etpwm.c @@ -0,0 +1,2393 @@ +/** @file etpwm.c + * @brief ETPWM Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the ETPWM driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "etpwm.h" +#include "pinmux.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/** @fn void etpwmInit(void) + * @brief Initializes the eTPWM Driver + * + * This function initializes the eTPWM module. + * + * @note This function sets the time-base counters in up-count mode. + * Application can configure the module in a different mode using other functions in + * this driver.(Sample code provided in the examples folder) In that case, application + * need not call etpwmInit function. pinmuxInit needs to be called before this function. + * + */ +/* SourceId : ETPWM_SourceId_001 */ +/* DesignId : ETPWM_DesignId_001 */ +/* Requirements : CONQ_EPWM_SR2 */ +void etpwmInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** @b initialize @b ETPWM1 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG1->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG1->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG1->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG1->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG1->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG1->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG1->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG1->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0u << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG1->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG1->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG1->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG1->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG1 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG1->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG1->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG1->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG1->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG1->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG1->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM2 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG2->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG2->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG2->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG2->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG2->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG2->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG2->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG2->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG2->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG2->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG2->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG2->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG2 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG2->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG2->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG2->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG2->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG2->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG2->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM3 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG3->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG3->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG3->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG3->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG3->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG3->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG3->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG3->DBCTL = ( ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising + Edge Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ) ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG3->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG3->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG3->PCCTL = ( ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper + module */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle + */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ) ); /* Chopping Clock + Frequency */ + + /** - Set trip source enable */ + etpwmREG3->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG3 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG3->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG3->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG3->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG3->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG3->ETSEL |= ( ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ) ); + + /** - Sets up the ADC SOC period */ + etpwmREG3->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM4 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG4->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG4->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG4->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG4->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG4->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG4->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG4->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG4->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG4->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG4->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG4->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG4->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG4 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG4->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG4->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG4->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG4->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG4->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG4->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM5 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG5->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG5->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG5->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG5->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG5->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG5->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG5->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG5->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG5->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG5->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG5->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG5->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG5 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG5->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG5->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG5->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG5->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG5->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG5->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM6 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG6->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG6->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG6->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG6->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG6->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG6->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG6->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG6->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG6->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG6->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG6->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG6->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG6 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG6->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG6->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG6->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG6->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG6->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG6->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /** @b initialize @b ETPWM7 */ + + /** - Sets high speed time-base clock prescale bits */ + etpwmREG7->TBCTL = ( uint16 ) 0U << 7U; + + /** - Sets time-base clock prescale bits */ + etpwmREG7->TBCTL |= ( uint16 ) ( ( uint16 ) 0U << 10U ); + + /** - Sets time period or frequency for ETPWM block both PWMA and PWMB*/ + etpwmREG7->TBPRD = 1000U; + + /** - Setup the duty cycle for PWMA */ + etpwmREG7->CMPA = 50U; + + /** - Setup the duty cycle for PWMB */ + etpwmREG7->CMPB = 50U; + + /** - Force EPWMxA output high when counter reaches zero and low when counter reaches + * Compare A value */ + etpwmREG7->AQCTLA = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 4U ) ); + + /** - Force EPWMxB output high when counter reaches zero and low when counter reaches + * Compare B value */ + etpwmREG7->AQCTLB = ( ( uint16 ) ( ( uint16 ) ActionQual_Set << 0U ) + | ( uint16 ) ( ( uint16 ) ActionQual_Clear << 8U ) ); + + /** - Mode setting for Dead Band Module + * -Select the input mode for Dead Band Module + * -Select the output mode for Dead Band Module + * -Select Polarity of the output PWMs + */ + etpwmREG7->DBCTL = ( uint16 ) ( ( uint16 ) 0U << 5U ) /* Source for Falling edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 4U ) /* Source for Rising edge + delay(0-PWMA, 1-PWMB) */ + | ( uint16 ) ( ( uint16 ) 0U << 3U ) /* Enable/Disable EPWMxB + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 2U ) /* Enable/Disable EPWMxA + invert */ + | ( uint16 ) ( ( uint16 ) 0U << 1U ) /* Enable/Disable Rising Edge + Delay */ + | ( uint16 ) ( ( uint16 ) 0U << 0U ); /* Enable/Disable Falling + Edge Delay */ + + /** - Set the rising edge delay */ + etpwmREG7->DBRED = 1U; + + /** - Set the falling edge delay */ + etpwmREG7->DBFED = 1U; + + /** - Enable the chopper module for ETPWMx + * -Sets the One shot pulse width in a chopper modulated wave + * -Sets the dutycycle for the subsequent pulse train + * -Sets the period for the subsequent pulse train + */ + etpwmREG7->PCCTL = ( uint16 ) ( ( uint16 ) 0U << 0U ) /* Enable/Disable chopper module + */ + | ( uint16 ) ( ( uint16 ) 1U << 1U ) /* One-shot Pulse Width */ + | ( uint16 ) ( ( uint16 ) 3U << 8U ) /* Chopping Clock Duty Cycle */ + | ( uint16 ) ( ( uint16 ) 0U << 5U ); /* Chopping Clock Frequency */ + + /** - Set trip source enable */ + etpwmREG7->TZSEL = 0x0000U /** - Enable/Disable TZ1 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ6 as a one-shot trip source */ + | 0x0000U /** - Enable/Disable TZ1 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ2 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ3 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ4 as a CBC trip source */ + | 0x0000U /** - Enable/Disable TZ5 as a CBC trip source */ + | 0x0000U; /** - Enable/Disable TZ6 as a CBC trip source */ + + /** - Set interrupt enable */ + etpwmREG7 + ->TZEINT = 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 1 */ + | 0x0000U /** - Enable/Disable Digital Comparator Output A Event 2 */ + | 0x0000U /** - Enable/Disable one-shot interrupt generation */ + | 0x0000U; /** - Enable/Disable cycle-by-cycle interrupt generation */ + + /** - Sets up the event for interrupt */ + etpwmREG7->ETSEL = ( uint16 ) NO_EVENT; + + if( ( etpwmREG7->ETSEL & 0x0007U ) != 0U ) + { + etpwmREG7->ETSEL |= 0x0008U; + } + /** - Setup the frequency of the interrupt generation */ + etpwmREG7->ETPS = 1U; + + /** - Sets up the ADC SOC interrupt */ + etpwmREG7->ETSEL |= ( uint16 ) ( 0x0000U ) | ( uint16 ) ( 0x0000U ) + | ( uint16 ) ( ( uint16 ) DCAEVT1 << 8U ) + | ( uint16 ) ( ( uint16 ) DCBEVT1 << 12U ); + + /** - Sets up the ADC SOC period */ + etpwmREG7->ETPS |= ( ( uint16 ) ( ( uint16 ) 1U << 8U ) + | ( uint16 ) ( ( uint16 ) 1U << 12U ) ); + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/** @fn void etpwmStartTBCLK() + * @brief Start the time-base clocks of all eTPWMx modules + * + * This function starts the time-base clocks of all eTPWMx modules. + */ +/* SourceId : ETPWM_SourceId_002 */ +/* DesignId : ETPWM_DesignId_002 */ +/* Requirements : CONQ_EPWM_SR45 */ +void etpwmStartTBCLK( void ) +{ + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMUX[ 166U ] = ( pinMuxReg->PINMUX[ 166U ] + & PINMUX_ETPWM_TBCLK_SYNC_MASK ) + | ( PINMUX_ETPWM_TBCLK_SYNC_ON ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmStopTBCLK() + * @brief Stop the time-base clocks of all eTPWMx modules + * + * This function stops the time-base clocks of all eTPWMx modules. + */ +/* SourceId : ETPWM_SourceId_003 */ +/* DesignId : ETPWM_DesignId_003 */ +/* Requirements : CONQ_EPWM_SR46 */ +void etpwmStopTBCLK( void ) +{ + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + pinMuxReg->PINMUX[ 166U ] = ( pinMuxReg->PINMUX[ 166U ] + & PINMUX_ETPWM_TBCLK_SYNC_MASK ) + | ( PINMUX_ETPWM_TBCLK_SYNC_OFF ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; +} + +/** @fn void etpwmSetClkDiv(etpwmBASE_t *etpwm, etpwmClkDiv_t clkdiv, etpwmHspClkDiv_t + * hspclkdiv) + * @brief Sets the Time-base Clock divider + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param clkdiv Time-base clock divider + * - ClkDiv_by_1 + * - ClkDiv_by_2 + * - ClkDiv_by_4 + * - ClkDiv_by_8 + * - ClkDiv_by_16 + * - ClkDiv_by_32 + * - ClkDiv_by_64 + * - ClkDiv_by_128 + * @param hspclkdiv High Speed Time-base clock divider + * - HspClkDiv_by_1 + * - HspClkDiv_by_2 + * - HspClkDiv_by_4 + * - HspClkDiv_by_6 + * - HspClkDiv_by_8 + * - HspClkDiv_by_10 + * - HspClkDiv_by_12 + * - HspClkDiv_by_14 + * + * This function sets the TimeBase Clock and the High Speed time base clock divider + * TBCLK = VCLK4 / (HSPCLKDIV � CLKDIV) + */ +/* SourceId : ETPWM_SourceId_004 */ +/* DesignId : ETPWM_DesignId_004 */ +/* Requirements : CONQ_EPWM_SR3 */ +void etpwmSetClkDiv( etpwmBASE_t * etpwm, + etpwmClkDiv_t clkdiv, + etpwmHspClkDiv_t hspclkdiv ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x1F80U; + etpwm->TBCTL |= ( uint16 ) clkdiv | ( uint16 ) hspclkdiv; +} + +/** @fn void etpwmSetTimebasePeriod(etpwmBASE_t *etpwm, uint16 period) + * @brief Sets period of timebase counter + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param period 16-bit Time-base period + * + * This function sets period of timebase counter + */ +/* SourceId : ETPWM_SourceId_005 */ +/* DesignId : ETPWM_DesignId_005 */ +/* Requirements : CONQ_EPWM_SR4 */ +void etpwmSetTimebasePeriod( etpwmBASE_t * etpwm, uint16 period ) +{ + etpwm->TBPRD = period; +} + +/** @fn void etpwmSetCount(etpwmBASE_t *etpwm, uint16 count) + * @brief Sets timebase counter + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param count 16-bit Counter value + * + * This function sets the timebase counter + */ +/* SourceId : ETPWM_SourceId_006 */ +/* DesignId : ETPWM_DesignId_006 */ +/* Requirements : CONQ_EPWM_SR5 */ +void etpwmSetCount( etpwmBASE_t * etpwm, uint16 count ) +{ + etpwm->TBCTR = count; +} + +/** @fn void etpwmDisableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for time-base period register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for time-base period register + */ +/* SourceId : ETPWM_SourceId_007 */ +/* DesignId : ETPWM_DesignId_007 */ +/* Requirements : CONQ_EPWM_SR6 */ +void etpwmDisableTimebasePeriodShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL |= 0x0008U; +} + +/** @fn void etpwmEnableTimebasePeriodShadowMode(etpwmBASE_t *etpwm) + * @brief Enable shadow mode for time-base period register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function enables shadow mode for time-base period register + */ +/* SourceId : ETPWM_SourceId_008 */ +/* DesignId : ETPWM_DesignId_008 */ +/* Requirements : CONQ_EPWM_SR7 */ +void etpwmEnableTimebasePeriodShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0008U; +} + +/** @fn void etpwmEnableCounterLoadOnSync(etpwmBASE_t *etpwm, uint16 phase, uint16 + * direction) + * @brief Enable counter register load from phase register when a sync event occurs + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param phase Counter value to be loaded when a sync event occurs + * @param direction Direction of the counter after the sync event (Applied only if + * counter is in updown-count mode, ignores otherwise) + * - COUNT_UP + * - COUNT_DOWN + * - Pass 0 if not applied + * + * This function enables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ETPWM_SourceId_009 */ +/* DesignId : ETPWM_DesignId_009 */ +/* Requirements : CONQ_EPWM_SR8 */ +void etpwmEnableCounterLoadOnSync( etpwmBASE_t * etpwm, uint16 phase, uint16 direction ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x2000U; + etpwm->TBCTL |= 0x0004U | direction; + etpwm->TBPHS = phase; +} + +/** @fn void etpwmDisableCounterLoadOnSync(etpwmBASE_t *etpwm) + * @brief Disable counter register load from phase register when a sync event occurs + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables counter register load from phase register when a sync event + * occurs + */ +/* SourceId : ETPWM_SourceId_010 */ +/* DesignId : ETPWM_DesignId_010 */ +/* Requirements : CONQ_EPWM_SR9 */ +void etpwmDisableCounterLoadOnSync( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0004U; +} + +/** @fn void etpwmSetSyncOut(etpwmBASE_t *etpwm, etpwmSyncMode_t syncmode) + * @brief Set the source of EPWMxSYNCO signal + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param syncOutSrc Synchronization Output Select + * - SyncOut_EPWMxSYNCI + * - SyncOut_CtrEqZero + * - SyncOut_CtrEqCmpB + * - SyncOut_Disable + * + * This function sets the source of synchronization output signal + */ +/* SourceId : ETPWM_SourceId_011 */ +/* DesignId : ETPWM_DesignId_011 */ +/* Requirements : CONQ_EPWM_SR10 */ +void etpwmSetSyncOut( etpwmBASE_t * etpwm, etpwmSyncOut_t syncOutSrc ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0030U; + etpwm->TBCTL |= syncOutSrc; +} + +/** @fn void etpwmSetCounterMode(etpwmBASE_t *etpwm, etpwmCounterMode_t countermode) + * @brief Set the time-base counter mode + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param countermode Counter Mode + * - CounterMode_Up + * - Countermode_Down + * - CounterMode_UpDown + * - CounterMode_Stop + * + * This function sets the time-base counter mode of operation. + */ +/* SourceId : ETPWM_SourceId_012 */ +/* DesignId : ETPWM_DesignId_012 */ +/* Requirements : CONQ_EPWM_SR11 */ +void etpwmSetCounterMode( etpwmBASE_t * etpwm, etpwmCounterMode_t countermode ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0x0003U; + etpwm->TBCTL |= countermode; +} + +/** @fn void etpwmTriggerSWSync(etpwmBASE_t *etpwm) + * @brief Trigger a software synchronization pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function triggers a software synchronization pulse. SWFSYNC is valid (operates) + * only when EPWMxSYNCI as SyncOut + */ +/* SourceId : ETPWM_SourceId_013 */ +/* DesignId : ETPWM_DesignId_013 */ +/* Requirements : CONQ_EPWM_SR12 */ +void etpwmTriggerSWSync( etpwmBASE_t * etpwm ) +{ + etpwm->TBCTL |= 0x0040U; +} + +/** @fn void etpwmSetRunMode(etpwmBASE_t *etpwm, etpwmRunMode_t runmode) + * @brief Set the pulse width modulation (ETPWM) run mode + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param runmode Run mode + * - RunMode_SoftStopAfterIncr : Stop after the next time-base + * counter increment + * - RunMode_SoftStopAfterDecr : Stop after the next time-base + * counter decrement + * - RunMode_SoftStopAfterCycle : Stop when counter completes a whole + * cycle + * - RunMode_FreeRun : Free-run + * + * This function select the behaviour of the ePWM time-base counter during emulation + * events + */ +/* SourceId : ETPWM_SourceId_014 */ +/* DesignId : ETPWM_DesignId_014 */ +/* Requirements : CONQ_EPWM_SR13 */ +void etpwmSetRunMode( etpwmBASE_t * etpwm, etpwmRunMode_t runmode ) +{ + etpwm->TBCTL &= ( uint16 ) ~( uint16 ) 0xC000U; + etpwm->TBCTL |= runmode; +} + +/** @fn void etpwmSetCmpA(etpwmBASE_t *etpwm, uint16 value) + * @brief Set the Compare A value + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param value 16-bit Compare A value + * + * This function sets the compare A value + */ +/* SourceId : ETPWM_SourceId_015 */ +/* DesignId : ETPWM_DesignId_015 */ +/* Requirements : CONQ_EPWM_SR14 */ +void etpwmSetCmpA( etpwmBASE_t * etpwm, uint16 value ) +{ + etpwm->CMPA = value; +} + +/** @fn void etpwmSetCmpB(etpwmBASE_t *etpwm, uint16 value) + * @brief Set the Compare B value + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param value 16-bit Compare B value + * + * This function sets the compare B register + */ +/* SourceId : ETPWM_SourceId_016 */ +/* DesignId : ETPWM_DesignId_016 */ +/* Requirements : CONQ_EPWM_SR15 */ +void etpwmSetCmpB( etpwmBASE_t * etpwm, uint16 value ) +{ + etpwm->CMPB = value; +} + +/** @fn void etpwmEnableCmpAShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) + * @brief Enable shadow mode for Compare A register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param loadmode Active Counter-Compare A (CMPA) Load From Shadow Select Mode + * - LoadMode_CtrEqZero : Load on CTR = Zero + * - LoadMode_CtrEqPeriod : Load on CTR = PRD + * - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD + * - LoadMode_Freeze : Freeze (no loads possible) + * + * This function enables shadow mode for Compare A register + */ +/* SourceId : ETPWM_SourceId_017 */ +/* DesignId : ETPWM_DesignId_017 */ +/* Requirements : CONQ_EPWM_SR16 */ +void etpwmEnableCmpAShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode ) +{ + etpwm->CMPCTL &= ( uint16 ) ~( uint16 ) 0x0013U; + etpwm->CMPCTL |= loadmode; +} + +/** @fn void etpwmDisableCmpAShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for Compare A register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for Compare A register + */ +/* SourceId : ETPWM_SourceId_018 */ +/* DesignId : ETPWM_DesignId_018 */ +/* Requirements : CONQ_EPWM_SR17 */ +void etpwmDisableCmpAShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->CMPCTL |= 0x0010U; +} + +/** @fn void etpwmEnableCmpBShadowMode(etpwmBASE_t *etpwm, etpwmLoadMode_t loadmode) + * @brief Enable shadow mode for Compare B register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param loadmode Active Counter-Compare B (CMPB) Load From Shadow Select Mode + * - LoadMode_CtrEqZero : Load on CTR = Zero + * - LoadMode_CtrEqPeriod : Load on CTR = PRD + * - LoadMode_CtrEqZeroPeriod : Load on either CTR = Zero or CTR = PRD + * - LoadMode_Freeze : Freeze (no loads possible) + * + * This function enables shadow mode for Compare B register + */ +/* SourceId : ETPWM_SourceId_019 */ +/* DesignId : ETPWM_DesignId_019 */ +/* Requirements : CONQ_EPWM_SR18 */ +void etpwmEnableCmpBShadowMode( etpwmBASE_t * etpwm, etpwmLoadMode_t loadmode ) +{ + etpwm->CMPCTL &= ( uint16 ) ~( uint16 ) 0x004CU; + etpwm->CMPCTL |= ( uint16 ) ( ( uint16 ) loadmode << 2U ); +} + +/** @fn void etpwmDisableCmpBShadowMode(etpwmBASE_t *etpwm) + * @brief Disable shadow mode for Compare B register + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables shadow mode for Compare B register + */ +/* SourceId : ETPWM_SourceId_020 */ +/* DesignId : ETPWM_DesignId_020 */ +/* Requirements : CONQ_EPWM_SR19 */ +void etpwmDisableCmpBShadowMode( etpwmBASE_t * etpwm ) +{ + etpwm->CMPCTL |= 0x0040U; +} + +/** @fn void etpwmSetActionQualPwmA(etpwmBASE_t *etpwm, etpwmActionQualConfig_t + * actionqualconfig) + * @brief Configure Action Qualifier submodule to generate PWMA + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param actionqualconfig Action Qualifier configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmActionQualConfig_t configA + * configA.CtrEqZero_Action = ActionQual_Set + * configA.CtrEqPeriod_Action = ActionQual_Disabled + * configA.CtrEqCmpAUp_Action = ActionQual_Clear + * configA.CtrEqCmpADown_Action = ActionQual_Disabled + * configA.CtrEqCmpBUp_Action = ActionQual_Disabled + * configA.CtrEqCmpBDown_Action = ActionQual_Disabled + * void etpwmSetActionQualPwmA(etpwmREG1, configA) + * + * This function configures Action Qualifier submodule to generate PWMA + */ +/* SourceId : ETPWM_SourceId_021 */ +/* DesignId : ETPWM_DesignId_021 */ +/* Requirements : CONQ_EPWM_SR20 */ +void etpwmSetActionQualPwmA( etpwmBASE_t * etpwm, + etpwmActionQualConfig_t actionqualconfig ) +{ + etpwm + ->AQCTLA = ( ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqZero_Action << 0U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqPeriod_Action << 2U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpAUp_Action << 4U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpADown_Action + << 6U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBUp_Action << 8U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBDown_Action + << 10U ) ); +} + +/** @fn void etpwmSetActionQualPwmB(etpwmBASE_t *etpwm, etpwmActionQualConfig_t + * actionqualconfig) + * @brief Configure Action Qualifier submodule to generate PWMB + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param actionqualconfig Action Qualifier configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmActionQualConfig_t configB + * configB.CtrEqZero_Action = ActionQual_Set + * configB.CtrEqPeriod_Action = ActionQual_Disabled + * configB.CtrEqCmpAUp_Action = ActionQual_Disabled + * configB.CtrEqCmpADown_Action = ActionQual_Disabled + * configB.CtrEqCmpBUp_Action = ActionQual_Clear + * configB.CtrEqCmpBDown_Action = ActionQual_Disabled + * void etpwmSetActionQualPwmB(etpwmREG1, configB) + * + * This function configures Action Qualifier submodule to generate PWMB + */ +/* SourceId : ETPWM_SourceId_022 */ +/* DesignId : ETPWM_DesignId_022 */ +/* Requirements : CONQ_EPWM_SR21 */ +void etpwmSetActionQualPwmB( etpwmBASE_t * etpwm, + etpwmActionQualConfig_t actionqualconfig ) +{ + etpwm + ->AQCTLB = ( ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqZero_Action << 0U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqPeriod_Action << 2U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpAUp_Action << 4U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpADown_Action + << 6U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBUp_Action << 8U ) + | ( uint16 ) ( ( uint16 ) actionqualconfig.CtrEqCmpBDown_Action + << 10U ) ); +} + +/** @fn void etpwmEnableDeadBand(etpwmBASE_t *etpwm, etpwmDeadBandConfig_t deadbandconfig) + * @brief Enable DeadBand module + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param deadbandconfig DeadBand configuration + * + * This function configures Action Qualifier submodule to generate PWMB + */ +/* SourceId : ETPWM_SourceId_023 */ +/* DesignId : ETPWM_DesignId_023 */ +/* Requirements : CONQ_EPWM_SR22 */ +void etpwmEnableDeadBand( etpwmBASE_t * etpwm, etpwmDeadBandConfig_t deadbandconfig ) +{ + uint16 halfCycleMask = ( uint16 ) ( ( deadbandconfig.halfCycleEnable ) ? 0x8000U + : 0U ); + etpwm->DBCTL = ( ( uint16 ) deadbandconfig.inputmode + | ( uint16 ) deadbandconfig.outputmode + | ( uint16 ) deadbandconfig.polarity | halfCycleMask ); +} + +/** @fn void etpwmDisableDeadband(etpwmBASE_t *etpwm) + * @brief Disable DeadBand module + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * + * This function bypasses the Deadband submodule + */ +/* SourceId : ETPWM_SourceId_024 */ +/* DesignId : ETPWM_DesignId_024 */ +/* Requirements : CONQ_EPWM_SR23 */ +void etpwmDisableDeadband( etpwmBASE_t * etpwm ) +{ + etpwm->DBCTL = 0U; +} + +/** @fn void etpwmSetDeadBandDelay(etpwmBASE_t *etpwm, uint16 Rdelay, uint16 Fdelay) + * @brief Sets the rising and falling edge delay + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param Rdelay 16-bit rising edge delay in terms of TCLK ticks + * @param Fdelay 16-bit falling edge delay in terms of TCLK ticks + * + * This function sets the rising and falling edge delays in the DeadBand submodule + */ +/* SourceId : ETPWM_SourceId_025 */ +/* DesignId : ETPWM_DesignId_025 */ +/* Requirements : CONQ_EPWM_SR24 */ +void etpwmSetDeadBandDelay( etpwmBASE_t * etpwm, uint16 Rdelay, uint16 Fdelay ) +{ + etpwm->DBRED = Rdelay; + etpwm->DBFED = Fdelay; +} + +/** @fn void etpwmEnableChopping(etpwmBASE_t *etpwm, etpwmChoppingConfig_t choppingconfig) + * @brief Enable chopping + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param choppingconfig Chopper submodule configuration + * + * This function enables the chopper submodule with the given configuration + */ +/* SourceId : ETPWM_SourceId_026 */ +/* DesignId : ETPWM_DesignId_026 */ +/* Requirements : CONQ_EPWM_SR25 */ +void etpwmEnableChopping( etpwmBASE_t * etpwm, etpwmChoppingConfig_t choppingconfig ) +{ + etpwm->PCCTL = ( ( uint16 ) 0x0001U | ( uint16 ) choppingconfig.oswdth + | ( uint16 ) choppingconfig.freq | ( uint16 ) choppingconfig.duty ); +} + +/** @fn void etpwmDisableChopping(etpwmBASE_t *etpwm) + * @brief Disable chopping + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables the chopper submodule + */ +/* SourceId : ETPWM_SourceId_027 */ +/* DesignId : ETPWM_DesignId_027 */ +/* Requirements : CONQ_EPWM_SR26 */ +void etpwmDisableChopping( etpwmBASE_t * etpwm ) +{ + etpwm->PCCTL = 0U; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) + * @brief Select the tripzone zources + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param sources Trip zone sources (sources can be ORed) + * - CycleByCycle_TZ1 : Enable TZ1 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ2 : Enable TZ2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ3 : Enable TZ3 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ4 : Enable TZ4 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ5 : Enable TZ5 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ6 : Enable TZ6 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCAEVT2 : Enable DCAEVT2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCBEVT2 : Enable DCBEVT2 as a Cycle-by-cycle trip + * source + * - OneShot_TZ1 : Enable TZ1 as a One-shot trip source + * - OneShot_TZ2 : Enable TZ2 as a One-shot trip source + * - OneShot_TZ3 : Enable TZ3 as a One-shot trip source + * - OneShot_TZ4 : Enable TZ4 as a One-shot trip source + * - OneShot_TZ5 : Enable TZ5 as a One-shot trip source + * - OneShot_TZ6 : Enable TZ6 as a One-shot trip source + * - OneShot_DCAEVT1 : Enable DCAEVT1 as a One-shot trip source + * - OneShot_DCBEVT1 : Enable DCBEVT1 as a One-shot trip source + * + * This function selects the tripzone sources for cycle-by-cycle and one-shot trip + */ +/* SourceId : ETPWM_SourceId_028 */ +/* DesignId : ETPWM_DesignId_028 */ +/* Requirements : CONQ_EPWM_SR27 */ +void etpwmEnableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources ) +{ + etpwm->TZSEL |= sources; +} + +/** @fn void etpwmEnableTripZoneSources(etpwmBASE_t *etpwm, etpwmTripZoneSrc_t sources) + * @brief Disable the tripzone zources + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param sources Trip zone sources (sources can be ORed) + * - CycleByCycle_TZ1 : Disable TZ1 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ2 : Disable TZ2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ3 : Disable TZ3 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ4 : Disable TZ4 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ5 : Disable TZ5 as a Cycle-by-cycle trip + * source + * - CycleByCycle_TZ6 : Disable TZ6 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCAEVT2 : Disable DCAEVT2 as a Cycle-by-cycle trip + * source + * - CycleByCycle_DCBEVT2 : Disable DCBEVT2 as a Cycle-by-cycle trip + * source + * - OneShot_TZ1 : Disable TZ1 as a One-shot trip source + * - OneShot_TZ2 : Disable TZ2 as a One-shot trip source + * - OneShot_TZ3 : Disable TZ3 as a One-shot trip source + * - OneShot_TZ4 : Disable TZ4 as a One-shot trip source + * - OneShot_TZ5 : Disable TZ5 as a One-shot trip source + * - OneShot_TZ6 : Disable TZ6 as a One-shot trip source + * - OneShot_DCAEVT1 : Disable DCAEVT1 as a One-shot trip source + * - OneShot_DCBEVT1 : Disable DCBEVT1 as a One-shot trip source + * + * This function disables the tripzone sources for cycle-by-cycle or one-shot trip + */ +/* SourceId : ETPWM_SourceId_029 */ +/* DesignId : ETPWM_DesignId_029 */ +/* Requirements : CONQ_EPWM_SR28 */ +void etpwmDisableTripZoneSources( etpwmBASE_t * etpwm, etpwmTripZoneSrc_t sources ) +{ + etpwm->TZSEL &= ( uint16 ) ~( uint16 ) sources; +} + +/** @fn void etpwmSetTripAction(etpwmBASE_t *etpwm, etpwmTripActionConfig_t + * tripactionconfig) + * @brief Set the action for each trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param tripactionconfig Trip action configuration + * + * This function sets the action for each trip event + */ +/* SourceId : ETPWM_SourceId_030 */ +/* DesignId : ETPWM_DesignId_030 */ +/* Requirements : CONQ_EPWM_SR29 */ +void etpwmSetTripAction( etpwmBASE_t * etpwm, etpwmTripActionConfig_t tripactionconfig ) +{ + etpwm->TZCTL = ( ( uint16 ) ( ( uint16 ) tripactionconfig.TripEvent_ActionOnPWMA + << 0U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.TripEvent_ActionOnPWMB + << 2U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCAEVT1_ActionOnPWMA + << 4U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCAEVT2_ActionOnPWMA + << 6U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCBEVT1_ActionOnPWMB + << 8U ) + | ( uint16 ) ( ( uint16 ) tripactionconfig.DCBEVT2_ActionOnPWMB + << 10U ) ); +} + +/** @fn void etpwmEnableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) + * @brief Enables interrupt(EPWMx_TZINT) for the trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param interrupts Interrupts to be enabled (Interrupts can be ORed) + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function enables interrupt(EPWMx_TZINT) for the trip event + */ +/* SourceId : ETPWM_SourceId_031 */ +/* DesignId : ETPWM_DesignId_031 */ +/* Requirements : CONQ_EPWM_SR30 */ +void etpwmEnableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts ) +{ + etpwm->TZEINT |= interrupts; +} + +/** @fn void etpwmDisableTripInterrupt(etpwmBASE_t *etpwm, etpwmTrip_t interrupts) + * @brief Disables interrupt(EPWMx_TZINT) for the trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param interrupts Trip Interrupts to be disabled (Interrupts can be ORed) + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function disables interrupt(EPWMx_TZINT) for the trip event + */ +/* SourceId : ETPWM_SourceId_032 */ +/* DesignId : ETPWM_DesignId_032 */ +/* Requirements : CONQ_EPWM_SR31 */ +void etpwmDisableTripInterrupt( etpwmBASE_t * etpwm, etpwmTrip_t interrupts ) +{ + etpwm->TZEINT &= ( uint16 ) ~( uint16 ) interrupts; +} + +/** @fn void etpwmClearTripCondition(etpwmBASE_t *etpwm, etpwmTrip_t trips) + * @brief Clears the trip event flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param trips Trip events + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function clears the trip event / Digital Compare output event flag + */ +/* SourceId : ETPWM_SourceId_033 */ +/* DesignId : ETPWM_DesignId_033 */ +/* Requirements : CONQ_EPWM_SR32 */ +void etpwmClearTripCondition( etpwmBASE_t * etpwm, etpwmTrip_t trips ) +{ + etpwm->TZCLR = trips; +} + +/** @fn void etpwmClearTripInterruptFlag(etpwmBASE_t *etpwm) + * @brief Clears the trip interrupt flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function clears the trip interrupt flag + */ +/* SourceId : ETPWM_SourceId_034 */ +/* DesignId : ETPWM_DesignId_034 */ +/* Requirements : CONQ_EPWM_SR33 */ +void etpwmClearTripInterruptFlag( etpwmBASE_t * etpwm ) +{ + etpwm->TZCLR = 1U; +} + +/** @fn void etpwmForceTripEvent(etpwmBASE_t *etpwm, etpwmTrip_t trip) + * @brief Force a trip event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param trip Trip events + * - CycleByCycleTrip + * - OneShotTrip + * - DCAEVT1_inter + * - DCAEVT2_inter + * - DCBEVT1_inter + * - DCBEVT2_inter + * + * This function forces a trip event / Digital Compare trip event via software + */ +/* SourceId : ETPWM_SourceId_035 */ +/* DesignId : ETPWM_DesignId_035 */ +/* Requirements : CONQ_EPWM_SR34 */ +void etpwmForceTripEvent( etpwmBASE_t * etpwm, etpwmTrip_t trip ) +{ + etpwm->TZFRC = trip; +} + +/** @fn void etpwmEnableSOCA(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ADC Start of Conversion A pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMxSOCA Selection Options + * - DCAEVT1 : DCAEVT1.soc event + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMxSOCA Period Select + * - EventPeriod_FirstEvent : Generate SOCA pulse on the first + * event + * - EventPeriod_SecondEvent : Generate SOCA pulse on the second + * event + * - EventPeriod_ThirdEvent : Generate SOCA pulse on the third + * event + * + * This function enables ADC Start of Conversion A pulse + */ +/* SourceId : ETPWM_SourceId_036 */ +/* DesignId : ETPWM_DesignId_036 */ +/* Requirements : CONQ_EPWM_SR35 */ +void etpwmEnableSOCA( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0xF0FFU; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 11U ) + | ( uint16 ) ( ( uint16 ) eventsource << 8U ); + + etpwm->ETPS &= 0xF0FFU; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 8U ); +} + +/** @fn void etpwmDisableSOCA(etpwmBASE_t *etpwm) + * @brief Disable ADC Start of Conversion A pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables ADC Start of Conversion A pulse + */ +/* SourceId : ETPWM_SourceId_037 */ +/* DesignId : ETPWM_DesignId_037 */ +/* Requirements : CONQ_EPWM_SR36 */ +void etpwmDisableSOCA( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0xF0FFU; +} + +/** @fn void etpwmEnableSOCB(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ADC Start of Conversion B pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMxSOCB Selection Options + * - DCBEVT1 : DCBEVT1.soc event + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMxSOCB Period Select + * - EventPeriod_FirstEvent : Generate SOCB pulse on the first + * event + * - EventPeriod_SecondEvent : Generate SOCB pulse on the second + * event + * - EventPeriod_ThirdEvent : Generate SOCB pulse on the third + * event + * + * This function enables ADC Start of Conversion B pulse + */ +/* SourceId : ETPWM_SourceId_038 */ +/* DesignId : ETPWM_DesignId_038 */ +/* Requirements : CONQ_EPWM_SR37 */ +void etpwmEnableSOCB( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0x0FFFU; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 15U ) + | ( uint16 ) ( ( uint16 ) eventsource << 12U ); + + etpwm->ETPS &= 0x0FFFU; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 12U ); +} + +/** @fn void etpwmDisableSOCB(etpwmBASE_t *etpwm) + * @brief Disable ADC Start of Conversion B pulse + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables ADC Start of Conversion B pulse + */ +/* SourceId : ETPWM_SourceId_039 */ +/* DesignId : ETPWM_DesignId_039 */ +/* Requirements : CONQ_EPWM_SR38 */ +void etpwmDisableSOCB( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0x0FFFU; +} + +/** @fn void etpwmEnableInterrupt(etpwmBASE_t *etpwm, etpwmEventSrc_t eventsource, + * etpwmEventPeriod_t eventperiod) + * @brief Enable ePWM Interrupt + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param eventsource EPWMx_INT Selection Options + * - CTR_ZERO : Event CTR = Zero + * - CTR_PRD : Event CTR = PRD + * - CTR_ZERO_PRD : Event CTR = Zero or CTR = PRD + * - CTR_UP_CMPA : Event CTR = CMPA when the timer is + * incrementing + * - CTR_D0WM_CMPA : Event CTR = CMPA when the timer is + * decrementing + * - CTR_UP_CMPB : Event CTR = CMPB when the timer is + * incrementing + * - CTR_D0WM_CMPB : Event CTR = CMPB when the timer is + * decrementing + * @param eventperiod EPWMx_INT Period Select + * - EventPeriod_FirstEvent : Generate interrupt on the first + * event + * - EventPeriod_SecondEvent : Generate interrupt on the second + * event + * - EventPeriod_ThirdEvent : Generate interrupt on the third + * event + * + * This function enables EPWMx_INT generation + */ +/* SourceId : ETPWM_SourceId_040 */ +/* DesignId : ETPWM_DesignId_040 */ +/* Requirements : CONQ_EPWM_SR39 */ +void etpwmEnableInterrupt( etpwmBASE_t * etpwm, + etpwmEventSrc_t eventsource, + etpwmEventPeriod_t eventperiod ) +{ + etpwm->ETSEL &= 0xFFF0U; + etpwm->ETSEL |= ( uint16 ) ( ( uint16 ) 1U << 3U ) + | ( uint16 ) ( ( uint16 ) eventsource << 0U ); + + etpwm->ETPS &= 0xFFF0U; + etpwm->ETPS |= ( uint16 ) ( ( uint16 ) eventperiod << 0U ); +} + +/** @fn void etpwmDisableInterrupt(etpwmBASE_t *etpwm) + * @brief Disable ePWM Interrupt + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * + * This function disables EPWMx_INT generation + */ +/* SourceId : ETPWM_SourceId_041 */ +/* DesignId : ETPWM_DesignId_041 */ +/* Requirements : CONQ_EPWM_SR40 */ +void etpwmDisableInterrupt( etpwmBASE_t * etpwm ) +{ + etpwm->ETSEL &= 0xFFF0U; +} + +/** @fn uint16 etpwmGetEventStatus(etpwmBASE_t *etpwm) + * @brief Return event status flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @return event status flag + * Bit 0: ePWM Interrupt(EPWMx_INT) Status Flag + * Bit 2: ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag + * Bit 3: ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag + * + * This function returns the event status flags + */ +/* SourceId : ETPWM_SourceId_042 */ +/* DesignId : ETPWM_DesignId_042 */ +/* Requirements : CONQ_EPWM_SR47 */ +uint16 etpwmGetEventStatus( etpwmBASE_t * etpwm ) +{ + return etpwm->ETFLG; +} + +/** @fn void etpwmClearEventFlag(etpwmBASE_t *etpwm, etpwmEvent_t events) + * @brief Clear event status flag + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @param events status flag (flags can be ORed) + * - Event_Interrupt + * - Event_SOCA + * - Event_SOCB + * + * This function clears the event status flags + */ +/* SourceId : ETPWM_SourceId_043 */ +/* DesignId : ETPWM_DesignId_043 */ +/* Requirements : CONQ_EPWM_SR48 */ +void etpwmClearEventFlag( etpwmBASE_t * etpwm, etpwmEvent_t events ) +{ + etpwm->ETCLR = events; +} + +/** @fn void etpwmTriggerEvent(etpwmBASE_t *etpwm, etpwmEvent_t events) + * @brief Force an event + * + * @param etpwm The pulse width modulation (ETPWM) object handle (etpwmREG1..7) + * @return events (events can be ORed) + * - Event_Interrupt + * - Event_SOCA + * - Event_SOCB + * + * This function forces an event + */ +/* SourceId : ETPWM_SourceId_044 */ +/* DesignId : ETPWM_DesignId_044 */ +/* Requirements : CONQ_EPWM_SR49 */ +void etpwmTriggerEvent( etpwmBASE_t * etpwm, etpwmEvent_t events ) +{ + etpwm->ETFRC = events; +} + +/** @fn void etpwmEnableDigitalCompareEvents(etpwmBASE_t *etpwm, + * etpwmDigitalCompareConfig_t digitalcompareconfig) + * @brief Enable and configure digital compare events + * + * @param etpwm The pulse width modulation (ETPWM) object handle + * (etpwmREG1..7) + * @param digitalcompareconfig Digital Compare modue configuration + * + * Example usage (Removing semicolons to avoid MISRA warnings): + * etpwmDigitalCompareConfig_t config1 + * config1.DCAH_src = TZ1 + * config1.DCAL_src = TZ2 + * config1.DCBH_src = TZ1 + * config1.DCBL_src = TZ3 + * config1.DCAEVT1_event = DCAH_High + * config1.DCAEVT2_event = DCAL_High + * config1.DCBEVT1_event = DCBL_High + * config1.DCBEVT2_event = DCBL_High_DCBH_low + * etpwmEnableDigitalCompareEvents(etpwmREG1, config1) + * + * This function enbales and configures the digital compare events. HTis function can + * also be used to disable digital compare events + */ +/* SourceId : ETPWM_SourceId_045 */ +/* DesignId : ETPWM_DesignId_045 */ +/* Requirements : CONQ_EPWM_SR41 */ +void etpwmEnableDigitalCompareEvents( etpwmBASE_t * etpwm, + etpwmDigitalCompareConfig_t digitalcompareconfig ) +{ + etpwm->DCTRIPSEL = ( ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAH_src << 0U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAL_src << 4U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBH_src << 8U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBL_src + << 12U ) ); + + etpwm->TZDCSEL = ( ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAEVT1_event << 0U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCAEVT2_event + << 3U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBEVT1_event + << 6U ) + | ( uint16 ) ( ( uint16 ) digitalcompareconfig.DCBEVT2_event + << 9U ) ); +} + +/** @fn void etpwm1GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_046 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm1GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM1_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM1_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM1_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM1_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM1_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM1_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM1_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM1_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM1_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM1_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM1_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM1_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM1_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM1_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM1_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM1_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM1_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM1_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM1_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM1_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM1_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM1_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM1_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM1_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG1->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG1->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG1->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG1->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG1->CMPA; + config_reg->CONFIG_CMPB = etpwmREG1->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG1->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG1->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG1->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG1->DBRED; + config_reg->CONFIG_DBFED = etpwmREG1->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG1->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG1->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG1->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG1->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG1->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG1->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG1->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG1->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG1->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG1->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG1->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG1->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG1->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG1->DCFWINDOWCNT; + } +} + +/** @fn void etpwm2GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_47 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm2GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM2_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM2_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM2_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM2_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM2_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM2_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM2_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM2_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM2_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM2_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM2_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM2_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM2_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM2_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM2_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM2_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM2_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM2_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM2_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM2_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM2_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM2_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM2_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM2_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM2_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG2->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG2->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG2->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG2->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG2->CMPA; + config_reg->CONFIG_CMPB = etpwmREG2->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG2->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG2->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG2->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG2->DBRED; + config_reg->CONFIG_DBFED = etpwmREG2->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG2->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG2->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG2->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG2->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG2->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG2->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG2->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG2->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG2->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG2->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG2->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG2->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG2->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG2->DCFWINDOWCNT; + } +} + +/** @fn void etpwm3GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_048 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm3GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM3_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM3_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM3_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM3_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM3_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM3_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM3_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM3_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM3_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM3_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM3_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM3_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM3_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM3_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM3_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM3_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM3_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM3_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM3_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM3_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM3_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM3_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM3_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM3_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM3_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG3->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG3->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG3->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG3->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG3->CMPA; + config_reg->CONFIG_CMPB = etpwmREG3->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG3->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG3->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG3->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG3->DBRED; + config_reg->CONFIG_DBFED = etpwmREG3->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG3->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG3->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG3->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG3->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG3->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG3->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG3->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG3->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG3->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG3->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG3->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG3->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG3->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG3->DCFWINDOWCNT; + } +} + +/** @fn void etpwm4GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_049 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm4GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM4_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM4_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM4_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM4_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM4_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM4_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM4_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM4_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM4_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM4_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM4_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM4_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM4_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM4_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM4_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM4_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM4_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM4_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM4_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM4_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM4_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM4_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM4_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM4_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM4_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG4->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG4->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG4->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG4->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG4->CMPA; + config_reg->CONFIG_CMPB = etpwmREG4->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG4->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG4->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG4->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG4->DBRED; + config_reg->CONFIG_DBFED = etpwmREG4->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG4->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG4->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG4->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG4->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG4->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG4->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG4->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG4->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG4->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG4->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG4->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG4->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG4->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG4->DCFWINDOWCNT; + } +} + +/** @fn void etpwm5GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_050 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm5GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM5_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM5_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM5_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM5_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM5_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM5_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM5_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM5_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM5_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM5_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM5_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM5_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM5_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM5_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM5_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM5_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM5_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM5_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM5_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM5_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM5_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM5_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM5_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM5_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM5_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG5->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG5->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG5->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG5->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG5->CMPA; + config_reg->CONFIG_CMPB = etpwmREG5->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG5->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG5->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG5->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG5->DBRED; + config_reg->CONFIG_DBFED = etpwmREG5->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG5->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG5->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG5->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG5->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG5->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG5->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG5->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG5->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG5->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG5->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG5->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG5->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG5->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG5->DCFWINDOWCNT; + } +} + +/** @fn void etpwm6GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_051 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm6GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM6_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM6_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM6_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM6_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM6_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM6_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM6_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM6_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM6_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM6_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM6_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM6_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM6_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM6_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM6_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM6_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM6_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM6_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM6_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM6_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM6_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM6_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM6_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM6_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM6_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG6->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG6->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG6->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG6->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG6->CMPA; + config_reg->CONFIG_CMPB = etpwmREG6->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG6->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG6->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG6->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG6->DBRED; + config_reg->CONFIG_DBFED = etpwmREG6->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG6->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG6->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG6->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG6->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG6->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG6->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG6->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG6->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG6->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG6->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG6->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG6->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG6->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG6->DCFWINDOWCNT; + } +} + +/** @fn void etpwm7GetConfigValue(etpwm_config_reg_t *config_reg, config_value_type_t + *type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : ETPWM_SourceId_052 */ +/* DesignId : ETPWM_DesignId_046 */ +/* Requirements : CONQ_EPWM_SR42 */ +void etpwm7GetConfigValue( etpwm_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_TBCTL = ETPWM1_TBCTL_CONFIGVALUE; + config_reg->CONFIG_TBPHS = ETPWM7_TBPHS_CONFIGVALUE; + config_reg->CONFIG_TBPRD = ETPWM7_TBPRD_CONFIGVALUE; + config_reg->CONFIG_CMPCTL = ETPWM7_CMPCTL_CONFIGVALUE; + config_reg->CONFIG_CMPA = ETPWM7_CMPA_CONFIGVALUE; + config_reg->CONFIG_CMPB = ETPWM7_CMPB_CONFIGVALUE; + config_reg->CONFIG_AQCTLA = ETPWM7_AQCTLA_CONFIGVALUE; + config_reg->CONFIG_AQCTLB = ETPWM7_AQCTLB_CONFIGVALUE; + config_reg->CONFIG_DBCTL = ETPWM7_DBCTL_CONFIGVALUE; + config_reg->CONFIG_DBRED = ETPWM7_DBRED_CONFIGVALUE; + config_reg->CONFIG_DBFED = ETPWM7_DBFED_CONFIGVALUE; + config_reg->CONFIG_TZSEL = ETPWM7_TZSEL_CONFIGVALUE; + config_reg->CONFIG_TZDCSEL = ETPWM7_TZDCSEL_CONFIGVALUE; + config_reg->CONFIG_TZCTL = ETPWM7_TZCTL_CONFIGVALUE; + config_reg->CONFIG_TZEINT = ETPWM7_TZEINT_CONFIGVALUE; + config_reg->CONFIG_ETSEL = ETPWM7_ETSEL_CONFIGVALUE; + config_reg->CONFIG_ETPS = ETPWM7_ETPS_CONFIGVALUE; + config_reg->CONFIG_PCCTL = ETPWM7_PCCTL_CONFIGVALUE; + config_reg->CONFIG_DCTRIPSEL = ETPWM7_DCTRIPSEL_CONFIGVALUE; + config_reg->CONFIG_DCACTL = ETPWM7_DCACTL_CONFIGVALUE; + config_reg->CONFIG_DCBCTL = ETPWM7_DCBCTL_CONFIGVALUE; + config_reg->CONFIG_DCFCTL = ETPWM7_DCFCTL_CONFIGVALUE; + config_reg->CONFIG_DCCAPCTL = ETPWM7_DCCAPCTL_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOW = ETPWM7_DCFWINDOW_CONFIGVALUE; + config_reg->CONFIG_DCFWINDOWCNT = ETPWM7_DCFWINDOWCNT_CONFIGVALUE; + } + else + { + config_reg->CONFIG_TBCTL = etpwmREG7->TBCTL; + config_reg->CONFIG_TBPHS = etpwmREG7->TBPHS; + config_reg->CONFIG_TBPRD = etpwmREG7->TBPRD; + config_reg->CONFIG_CMPCTL = etpwmREG7->CMPCTL; + config_reg->CONFIG_CMPA = etpwmREG7->CMPA; + config_reg->CONFIG_CMPB = etpwmREG7->CMPB; + config_reg->CONFIG_AQCTLA = etpwmREG7->AQCTLA; + config_reg->CONFIG_AQCTLB = etpwmREG7->AQCTLB; + config_reg->CONFIG_DBCTL = etpwmREG7->DBCTL; + config_reg->CONFIG_DBRED = etpwmREG7->DBRED; + config_reg->CONFIG_DBFED = etpwmREG7->DBFED; + config_reg->CONFIG_TZSEL = etpwmREG7->TZSEL; + config_reg->CONFIG_TZDCSEL = etpwmREG7->TZDCSEL; + config_reg->CONFIG_TZCTL = etpwmREG7->TZCTL; + config_reg->CONFIG_TZEINT = etpwmREG7->TZEINT; + config_reg->CONFIG_ETSEL = etpwmREG7->ETSEL; + config_reg->CONFIG_ETPS = etpwmREG7->ETPS; + config_reg->CONFIG_PCCTL = etpwmREG7->PCCTL; + config_reg->CONFIG_DCTRIPSEL = etpwmREG7->DCTRIPSEL; + config_reg->CONFIG_DCACTL = etpwmREG7->DCACTL; + config_reg->CONFIG_DCBCTL = etpwmREG7->DCBCTL; + config_reg->CONFIG_DCFCTL = etpwmREG7->DCFCTL; + config_reg->CONFIG_DCCAPCTL = etpwmREG7->DCCAPCTL; + config_reg->CONFIG_DCFWINDOW = etpwmREG7->DCFWINDOW; + config_reg->CONFIG_DCFWINDOWCNT = etpwmREG7->DCFWINDOWCNT; + } +} + +/* USER CODE BEGIN (31) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c new file mode 100644 index 00000000000..1ba9c6cabb9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/gio.c @@ -0,0 +1,505 @@ +/** @file gio.c + * @brief GIO Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "gio.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void gioInit(void) + * @brief Initializes the GIO Driver + * + * This function initializes the GIO module and set the GIO ports + * to the initial values. + */ +/* SourceId : GIO_SourceId_001 */ +/* DesignId : GIO_DesignId_001 */ +/* Requirements : CONQ_GIO_SR2 */ +void gioInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** bring GIO module out of reset */ + gioREG->GCR0 = 1U; + gioREG->ENACLR = 0xFFU; + gioREG->LVLCLR = 0xFFU; + + /** @b initialize @b Port @b A */ + + /** - Port A output values */ + gioPORTA->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A direction */ + gioPORTA->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A open drain enable */ + gioPORTA->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown selection */ + gioPORTA->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port A pullup / pulldown enable*/ + gioPORTA->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** @b initialize @b Port @b B */ + + /** - Port B output values */ + gioPORTB->DOUT = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B direction */ + gioPORTB->DIR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B open drain enable */ + gioPORTB->PDR = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown selection */ + gioPORTB->PSL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /** - Port B pullup / pulldown enable*/ + gioPORTB->PULDIS = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ); /* Bit 7 */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** @b initialize @b interrupts */ + + /** - interrupt polarity */ + gioREG->POL = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - interrupt level */ + gioREG->LVLSET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /** - clear all pending interrupts */ + gioREG->FLG = 0xFFU; + + /** - enable interrupts */ + gioREG->ENASET = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* Bit 0 */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Bit 1 */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Bit 2 */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Bit 3 */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Bit 4 */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Bit 5 */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Bit 6 */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* Bit 7 */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Bit 8 */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Bit 9 */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* Bit 10 */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* Bit 11 */ + | ( uint32 ) ( ( uint32 ) 0U << 12U ) /* Bit 12 */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* Bit 13 */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* Bit 14 */ + | ( uint32 ) ( ( uint32 ) 0U << 15U ); /* Bit 15 */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void gioSetDirection(gioPORT_t *port, uint32 dir) + * @brief Set Port Direction + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] dir value to write to DIR register + * + * Set the direction of GIO pins at runtime. + */ +/* SourceId : GIO_SourceId_002 */ +/* DesignId : GIO_DesignId_002 */ +/* Requirements : CONQ_GIO_SR3 */ +void gioSetDirection( gioPORT_t * port, uint32 dir ) +{ + port->DIR = dir; +} + +/** @fn void gioSetBit(gioPORT_t *port, uint32 bit, uint32 value) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * @param[in] value binary value to write to bit + * + * Writes a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_003 */ +/* DesignId : GIO_DesignId_003 */ +/* Requirements : CONQ_GIO_SR4 */ +void gioSetBit( gioPORT_t * port, uint32 bit, uint32 value ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( value != 0U ) + { + port->DSET = ( uint32 ) 1U << bit; + } + else + { + port->DCLR = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioSetPort(gioPORT_t *port, uint32 value) + * @brief Write Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] value value to write to port + * + * Writes a value to all pin of a given GIO port + */ +/* SourceId : GIO_SourceId_004 */ +/* DesignId : GIO_DesignId_004 */ +/* Requirements : CONQ_GIO_SR5 */ +void gioSetPort( gioPORT_t * port, uint32 value ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + port->DOUT = value; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn uint32 gioGetBit(gioPORT_t *port, uint32 bit) + * @brief Read Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Reads a the current value from the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_005 */ +/* DesignId : GIO_DesignId_005 */ +/* Requirements : CONQ_GIO_SR8 */ +uint32 gioGetBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return ( port->DIN >> bit ) & 1U; +} + +/** @fn uint32 gioGetPort(gioPORT_t *port) + * @brief Read Port Value + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * + * Reads a the current value of a given GIO port + */ +/* SourceId : GIO_SourceId_006 */ +/* DesignId : GIO_DesignId_006 */ +/* Requirements : CONQ_GIO_SR7 */ +uint32 gioGetPort( gioPORT_t * port ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return port->DIN; +} + +/** @fn void gioToggleBit(gioPORT_t *port, uint32 bit) + * @brief Write Bit + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit number 0-7 that specifies the bit to be written to. + * - 0: LSB + * - 7: MSB + * + * Toggle a value to the specified pin of the given GIO port + */ +/* SourceId : GIO_SourceId_007 */ +/* DesignId : GIO_DesignId_007 */ +/* Requirements : CONQ_GIO_SR6 */ +void gioToggleBit( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( port->DIN & ( uint32 ) ( ( uint32 ) 1U << bit ) ) != 0U ) + { + port->DCLR = ( uint32 ) 1U << bit; + } + else + { + port->DSET = ( uint32 ) 1U << bit; + } +} + +/** @fn void gioEnableNotification(uint32 bit) + * @brief Enable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Enables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_008 */ +/* DesignId : GIO_DesignId_008 */ +/* Requirements : CONQ_GIO_SR9 */ +void gioEnableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENASET = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENASET = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioDisableNotification(uint32 bit) + * @brief Disable Interrupt + * @param[in] port pointer to GIO port: + * - gioPORTA: PortA pointer + * - gioPORTB: PortB pointer + * @param[in] bit interrupt pin to enable + * - 0: LSB + * - 7: MSB + * + * Disables an interrupt pin of selected port + */ +/* SourceId : GIO_SourceId_009 */ +/* DesignId : GIO_DesignId_009 */ +/* Requirements : CONQ_GIO_SR10 */ +void gioDisableNotification( gioPORT_t * port, uint32 bit ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( port == gioPORTA ) + { + gioREG->ENACLR = ( uint32 ) 1U << bit; + } + else if( port == gioPORTB ) + { + gioREG->ENACLR = ( uint32 ) 1U << ( bit + 8U ); + } + else + { + /* Empty */ + } +} + +/** @fn void gioGetConfigValue(gio_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : GIO_SourceId_010 */ +/* DesignId : GIO_DesignId_010 */ +/* Requirements : CONQ_GIO_SR11 */ +void gioGetConfigValue( gio_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_INTDET = GIO_INTDET_CONFIGVALUE; + config_reg->CONFIG_POL = GIO_POL_CONFIGVALUE; + config_reg->CONFIG_INTENASET = GIO_INTENASET_CONFIGVALUE; + config_reg->CONFIG_LVLSET = GIO_LVLSET_CONFIGVALUE; + + config_reg->CONFIG_PORTADIR = GIO_PORTADIR_CONFIGVALUE; + config_reg->CONFIG_PORTAPDR = GIO_PORTAPDR_CONFIGVALUE; + config_reg->CONFIG_PORTAPSL = GIO_PORTAPSL_CONFIGVALUE; + config_reg->CONFIG_PORTAPULDIS = GIO_PORTAPULDIS_CONFIGVALUE; + + config_reg->CONFIG_PORTBDIR = GIO_PORTBDIR_CONFIGVALUE; + config_reg->CONFIG_PORTBPDR = GIO_PORTBPDR_CONFIGVALUE; + config_reg->CONFIG_PORTBPSL = GIO_PORTBPSL_CONFIGVALUE; + config_reg->CONFIG_PORTBPULDIS = GIO_PORTBPULDIS_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_INTDET = gioREG->INTDET; + config_reg->CONFIG_POL = gioREG->POL; + config_reg->CONFIG_INTENASET = gioREG->ENASET; + config_reg->CONFIG_LVLSET = gioREG->LVLSET; + + config_reg->CONFIG_PORTADIR = gioPORTA->DIR; + config_reg->CONFIG_PORTAPDR = gioPORTA->PDR; + config_reg->CONFIG_PORTAPSL = gioPORTA->PSL; + config_reg->CONFIG_PORTAPULDIS = gioPORTA->PULDIS; + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_PORTBDIR = gioPORTB->DIR; + config_reg->CONFIG_PORTBPDR = gioPORTB->PDR; + config_reg->CONFIG_PORTBPSL = gioPORTB->PSL; + config_reg->CONFIG_PORTBPULDIS = gioPORTB->PULDIS; + } +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c new file mode 100644 index 00000000000..8e835f9acf5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/het.c @@ -0,0 +1,2921 @@ +/** @file het.c + * @brief HET Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "het.h" +#include "sys_vim.h" +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/*----------------------------------------------------------------------------*/ +/* Global variables */ + +static const uint32 s_het1pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +static const uint32 s_het2pwmPolarity[ 8U ] = { + 3U, 3U, 3U, 3U, 3U, 3U, 3U, 3U, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het1PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het1PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/*----------------------------------------------------------------------------*/ +/* Default Program */ + +/** @var static const hetINSTRUCTION_t het2PROGRAM[58] + * @brief Default Program + * + * Het program running after initialization. + */ + +static const hetINSTRUCTION_t het2PROGRAM[ 58U ] = { + /* CNT: Timebase + * - Instruction = 0 + * - Next instruction = 1 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00002C80U, + /* Control */ + 0x01FFFFFFU, + /* Data */ + 0xFFFFFF80U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 0 -> Duty Cycle + * - Instruction = 1 + * - Next instruction = 2 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x000055C0U, + /* Control */ + ( 0x00004006U | ( uint32 ) ( ( uint32 ) 8U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 0 -> Period + * - Instruction = 2 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00007480U, + /* Control */ + 0x00052006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 1 -> Duty Cycle + * - Instruction = 3 + * - Next instruction = 4 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x000095C0U, + /* Control */ + ( 0x00008006U | ( uint32 ) ( ( uint32 ) 10U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 1 -> Period + * - Instruction = 4 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000B480U, + /* Control */ + 0x00056006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 2 -> Duty Cycle + * - Instruction = 5 + * - Next instruction = 6 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0000D5C0U, + /* Control */ + ( 0x0000C006U | ( uint32 ) ( ( uint32 ) 12U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 2 -> Period + * - Instruction = 6 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000F480U, + /* Control */ + 0x0005A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 3 -> Duty Cycle + * - Instruction = 7 + * - Next instruction = 8 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x000115C0U, + /* Control */ + ( 0x00010006U | ( uint32 ) ( ( uint32 ) 14U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 3 -> Period + * - Instruction = 8 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00013480U, + /* Control */ + 0x0005E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 4 -> Duty Cycle + * - Instruction = 9 + * - Next instruction = 10 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x000155C0U, + /* Control */ + ( 0x00014006U | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 4 -> Period + * - Instruction = 10 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x00017480U, + /* Control */ + 0x00062006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 5 -> Duty Cycle + * - Instruction = 11 + * - Next instruction = 12 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x000195C0U, + /* Control */ + ( 0x00018006U | ( uint32 ) ( ( uint32 ) 17U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 5 -> Period + * - Instruction = 12 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001B480U, + /* Control */ + 0x00066006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 6 -> Duty Cycle + * - Instruction = 13 + * - Next instruction = 14 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0001D5C0U, + /* Control */ + ( 0x0001C006U | ( uint32 ) ( ( uint32 ) 18U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 6 -> Period + * - Instruction = 14 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001F480U, + /* Control */ + 0x0006A006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PWCNT: PWM 7 -> Duty Cycle + * - Instruction = 15 + * - Next instruction = 16 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x000215C0U, + /* Control */ + ( 0x00020006U | ( uint32 ) ( ( uint32 ) 19U << 8U ) + | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* DJZ: PWM 7 -> Period + * - Instruction = 16 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00023480U, + /* Control */ + 0x0006E006U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 0 + * - Instruction = 17 + * - Next instruction = 18 + * - Conditional next instruction = 18 + * - Interrupt = 17 + * - Pin = 9 + */ + { /* Program */ + 0x00025440U, + /* Control */ + ( 0x00024007U | ( uint32 ) ( ( uint32 ) 9U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 1 + * - Instruction = 18 + * - Next instruction = 19 + * - Conditional next instruction = 19 + * - Interrupt = 18 + * - Pin = 11 + */ + { /* Program */ + 0x00027440U, + /* Control */ + ( 0x00026007U | ( uint32 ) ( ( uint32 ) 11U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 2 + * - Instruction = 19 + * - Next instruction = 20 + * - Conditional next instruction = 20 + * - Interrupt = 19 + * - Pin = 13 + */ + { /* Program */ + 0x00029440U, + /* Control */ + ( 0x00028007U | ( uint32 ) ( ( uint32 ) 13U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 3 + * - Instruction = 20 + * - Next instruction = 21 + * - Conditional next instruction = 21 + * - Interrupt = 20 + * - Pin = 15 + */ + { /* Program */ + 0x0002B440U, + /* Control */ + ( 0x0002A007U | ( uint32 ) ( ( uint32 ) 15U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 4 + * - Instruction = 21 + * - Next instruction = 22 + * - Conditional next instruction = 22 + * - Interrupt = 21 + * - Pin = 20 + */ + { /* Program */ + 0x0002D440U, + /* Control */ + ( 0x0002C007U | ( uint32 ) ( ( uint32 ) 20U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 5 + * - Instruction = 22 + * - Next instruction = 23 + * - Conditional next instruction = 23 + * - Interrupt = 22 + * - Pin = 21 + */ + { /* Program */ + 0x0002F440U, + /* Control */ + ( 0x0002E007U | ( uint32 ) ( ( uint32 ) 21U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 6 + * - Instruction = 23 + * - Next instruction = 24 + * - Conditional next instruction = 24 + * - Interrupt = 23 + * - Pin = 22 + */ + { /* Program */ + 0x00031440U, + /* Control */ + ( 0x00030007U | ( uint32 ) ( ( uint32 ) 22U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* ECNT: CCU Edge 7 + * - Instruction = 24 + * - Next instruction = 25 + * - Conditional next instruction = 25 + * - Interrupt = 24 + * - Pin = 23 + */ + { /* Program */ + 0x00033440U, + /* Control */ + ( 0x00032007U | ( uint32 ) ( ( uint32 ) 23U << 8U ) + | ( uint32 ) ( ( uint32 ) 1U << 4U ) ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 0 + * - Instruction = 25 + * - Next instruction = 26 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + */ + { /* Program */ + 0x00034E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 0U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 0 + * - Instruction = 26 + * - Next instruction = 27 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 0 + 1 + */ + { /* Program */ + 0x00036E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 0U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 1 + * - Instruction = 27 + * - Next instruction = 28 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + */ + { /* Program */ + 0x00038E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 2U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 1 + * - Instruction = 28 + * - Next instruction = 29 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 2 + 1 + */ + { /* Program */ + 0x0003AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 2U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 2 + * - Instruction = 29 + * - Next instruction = 30 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + */ + { /* Program */ + 0x0003CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 4U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 2 + * - Instruction = 30 + * - Next instruction = 31 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 4 + 1 + */ + { /* Program */ + 0x0003EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 4U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 3 + * - Instruction = 31 + * - Next instruction = 32 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + */ + { /* Program */ + 0x00040E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 6U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 3 + * - Instruction = 32 + * - Next instruction = 33 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 6 + 1 + */ + { /* Program */ + 0x00042E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 6U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 4 + * - Instruction = 33 + * - Next instruction = 34 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + */ + { /* Program */ + 0x00044E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 24U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 4 + * - Instruction = 34 + * - Next instruction = 35 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 24 + 1 + */ + { /* Program */ + 0x00046E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 24U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 5 + * - Instruction = 35 + * - Next instruction = 36 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + */ + { /* Program */ + 0x00048E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 26U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 5 + * - Instruction = 36 + * - Next instruction = 37 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 26 + 1 + */ + { /* Program */ + 0x0004AE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 26U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 6 + * - Instruction = 37 + * - Next instruction = 38 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + */ + { /* Program */ + 0x0004CE00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 28U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 6 + * - Instruction = 38 + * - Next instruction = 39 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 28 + 1 + */ + { /* Program */ + 0x0004EE80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 28U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Duty 7 + * - Instruction = 39 + * - Next instruction = 40 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + */ + { /* Program */ + 0x00050E00U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( 30U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* PCNT: Capture Period 7 + * - Instruction = 40 + * - Next instruction = 57 + * - Conditional next instruction = na + * - Interrupt = na + * - Pin = 30 + 1 + */ + { /* Program */ + 0x00072E80U | ( uint32 ) ( ( uint32 ) 0U << 6U ) | ( uint32 ) ( ( 30U ) + 1U ), + /* Control */ + 0x00000000U, + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Duty Cycle Update + * - Instruction = 41 + * - Next instruction = 42 + * - Conditional next instruction = 2 + * - Interrupt = 1 + * - Pin = 8 + */ + { /* Program */ + 0x00054201U, + /* Control */ + ( 0x00004007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 8U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 0 -> Period Update + * - Instruction = 42 + * - Next instruction = 3 + * - Conditional next instruction = 41 + * - Interrupt = 2 + * - Pin = na + */ + { /* Program */ + 0x00006202U, + /* Control */ + ( 0x00052007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Duty Cycle Update + * - Instruction = 43 + * - Next instruction = 44 + * - Conditional next instruction = 4 + * - Interrupt = 3 + * - Pin = 10 + */ + { /* Program */ + 0x00058203U, + /* Control */ + ( 0x00008007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 10U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 1 -> Period Update + * - Instruction = 44 + * - Next instruction = 5 + * - Conditional next instruction = 43 + * - Interrupt = 4 + * - Pin = na + */ + { /* Program */ + 0x0000A204U, + /* Control */ + ( 0x00056007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Duty Cycle Update + * - Instruction = 45 + * - Next instruction = 46 + * - Conditional next instruction = 6 + * - Interrupt = 5 + * - Pin = 12 + */ + { /* Program */ + 0x0005C205U, + /* Control */ + ( 0x0000C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 12U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 2 -> Period Update + * - Instruction = 46 + * - Next instruction = 7 + * - Conditional next instruction = 45 + * - Interrupt = 6 + * - Pin = na + */ + { /* Program */ + 0x0000E206U, + /* Control */ + ( 0x0005A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Duty Cycle Update + * - Instruction = 47 + * - Next instruction = 48 + * - Conditional next instruction = 8 + * - Interrupt = 7 + * - Pin = 14 + */ + { /* Program */ + 0x00060207U, + /* Control */ + ( 0x00010007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 14U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 3 -> Period Update + * - Instruction = 48 + * - Next instruction = 9 + * - Conditional next instruction = 47 + * - Interrupt = 8 + * - Pin = na + */ + { /* Program */ + 0x00012208U, + /* Control */ + ( 0x0005E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Duty Cycle Update + * - Instruction = 49 + * - Next instruction = 50 + * - Conditional next instruction = 10 + * - Interrupt = 9 + * - Pin = 16 + */ + { /* Program */ + 0x00064209U, + /* Control */ + ( 0x00014007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 4 -> Period Update + * - Instruction = 50 + * - Next instruction = 11 + * - Conditional next instruction = 49 + * - Interrupt = 10 + * - Pin = na + */ + { /* Program */ + 0x0001620AU, + /* Control */ + ( 0x00062007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Duty Cycle Update + * - Instruction = 51 + * - Next instruction = 52 + * - Conditional next instruction = 12 + * - Interrupt = 11 + * - Pin = 17 + */ + { /* Program */ + 0x0006820BU, + /* Control */ + ( 0x00018007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 17U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 5 -> Period Update + * - Instruction = 52 + * - Next instruction = 13 + * - Conditional next instruction = 51 + * - Interrupt = 12 + * - Pin = na + */ + { /* Program */ + 0x0001A20CU, + /* Control */ + ( 0x00066007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Duty Cycle Update + * - Instruction = 53 + * - Next instruction = 54 + * - Conditional next instruction = 14 + * - Interrupt = 13 + * - Pin = 18 + */ + { /* Program */ + 0x0006C20DU, + /* Control */ + ( 0x0001C007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 18U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 6 -> Period Update + * - Instruction = 54 + * - Next instruction = 15 + * - Conditional next instruction = 53 + * - Interrupt = 14 + * - Pin = na + */ + { /* Program */ + 0x0001E20EU, + /* Control */ + ( 0x0006A007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Duty Cycle Update + * - Instruction = 55 + * - Next instruction = 56 + * - Conditional next instruction = 16 + * - Interrupt = 15 + * - Pin = 19 + */ + { /* Program */ + 0x0007020FU, + /* Control */ + ( 0x00020007U | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 19U << 8U ) | ( uint32 ) ( ( uint32 ) 3U << 3U ) ), + /* Data */ + 75136U, + /* Reserved */ + 0x00000000U }, + /* MOV64: PWM 7 -> Period Update + * - Instruction = 56 + * - Next instruction = 17 + * - Conditional next instruction = 55 + * - Interrupt = 16 + * - Pin = na + */ + { /* Program */ + 0x00022210U, + /* Control */ + ( 0x0006E007U ), + /* Data */ + 149888U, + /* Reserved */ + 0x00000000U }, + /* WCAP: Capture timestamp + * - Instruction = 57 + * - Next instruction = 0 + * - Conditional next instruction = 0 + * - Interrupt = na + * - Pin = na + * - Reg = T + */ + { /* Program */ + 0x00001600U, + /* Control */ + ( 0x00000004U ), + /* Data */ + 0x00000000U, + /* Reserved */ + 0x00000000U }, +}; + +/** @fn void hetInit(void) + * @brief Initializes the het Driver + * + * This function initializes the het 1 module. + */ +/* SourceId : HET_SourceId_001 */ +/* DesignId : HET_DesignId_001 */ +/* Requirements : CONQ_HET_SR10 */ +void hetInit( void ) +{ + /** @b initialize @b HET */ + + /** - Set HET pins default output value */ + hetREG1 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG1->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG1->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG1->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG1->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG1->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG1->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG1->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG1->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG1->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM1, + ( const void * ) het1PROGRAM, + sizeof( het1PROGRAM ) ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG1->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG1->INTENAC = 0xFFFFFFFFU; + hetREG1->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG1->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @b initialize @b HET 2 */ + + /** - Set HET pins default output value */ + hetREG2 + ->DOUT = ( uint32 ) ( ( uint32 ) 0U << 31U ) | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) | ( uint32 ) ( ( uint32 ) 0U << 0U ); + + /** - Set HET pins direction */ + hetREG2->DIR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins open drain enable */ + hetREG2->PDR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down enable */ + hetREG2->PULDIS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins pullup/down select */ + hetREG2->PSL = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins high resolution share */ + hetREG2->HRSH = ( uint32 ) 0x00008000U | ( uint32 ) 0x00004000U + | ( uint32 ) 0x00002000U | ( uint32 ) 0x00001000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000008U | ( uint32 ) 0x00000004U + | ( uint32 ) 0x00000002U | ( uint32 ) 0x00000001U; + + /** - Set HET pins AND share */ + hetREG2->AND = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Set HET pins XOR share */ + hetREG2->XOR = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Parity control register + * - Enable/Disable Parity check + */ + hetREG2->PCR = ( uint32 ) 0x00000005U; + + /** - Fill HET RAM with opcodes and Data */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /** - Release from reset */ + /*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 "HET RAM Fill from the table - Allowed + * as per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + /*SAFETYMCUSW 95 S MR:11.1,11.4 "HET RAM Fill from the table - Allowed as + * per MISRA rule 11.2" */ + ( void ) memcpy( ( void * ) hetRAM2, + ( const void * ) het2PROGRAM, + sizeof( het2PROGRAM ) ); + + /** - Setup prescaler values + * - Loop resolution prescaler + * - High resolution prescaler + */ + hetREG2->PFR = ( uint32 ) ( ( uint32 ) 6U << 8U ) | ( ( uint32 ) 0U ); + + /** - Setup interrupt priority level + * - PWM 0 end of duty level + * - PWM 0 end of period level + * - PWM 1 end of duty level + * - PWM 1 end of period level + * - PWM 2 end of duty level + * - PWM 2 end of period level + * - PWM 3 end of duty level + * - PWM 3 end of period level + * - PWM 4 end of duty level + * - PWM 4 end of period level + * - PWM 5 end of duty level + * - PWM 5 end of period level + * - PWM 6 end of duty level + * - PWM 6 end of period level + * - PWM 7 end of duty level + * - PWM 7 end of period level + + * - CCU Edge Detection 0 level + * - CCU Edge Detection 1 level + * - CCU Edge Detection 2 level + * - CCU Edge Detection 3 level + * - CCU Edge Detection 4 level + * - CCU Edge Detection 5 level + * - CCU Edge Detection 6 level + * - CCU Edge Detection 7 level + */ + hetREG2->PRY = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Enable interrupts + * - PWM 0 end of duty + * - PWM 0 end of period + * - PWM 1 end of duty + * - PWM 1 end of period + * - PWM 2 end of duty + * - PWM 2 end of period + * - PWM 3 end of duty + * - PWM 3 end of period + * - PWM 4 end of duty + * - PWM 4 end of period + * - PWM 5 end of duty + * - PWM 5 end of period + * - PWM 6 end of duty + * - PWM 6 end of period + * - PWM 7 end of duty + * - PWM 7 end of period + * - CCU Edge Detection 0 + * - CCU Edge Detection 1 + * - CCU Edge Detection 2 + * - CCU Edge Detection 3 + * - CCU Edge Detection 4 + * - CCU Edge Detection 5 + * - CCU Edge Detection 6 + * - CCU Edge Detection 7 + */ + hetREG2->INTENAC = 0xFFFFFFFFU; + hetREG2->INTENAS = ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U; + + /** - Setup control register + * - Enable output buffers + * - Ignore software breakpoints + * - Master or Slave Clock Mode + * - Enable HET + */ + hetREG2->GCR = ( 0x00000001U | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ) | ( 0x00020000U ) ); + + /** @note This function has to be called before the driver can be used.\n + * This function has to be executed in privileged mode.\n + */ + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/** @fn void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Start pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Start the given pwm signal + */ +/* SourceId : HET_SourceId_002 */ +/* DesignId : HET_DesignId_002 */ +/* Requirements : CONQ_HET_SR11 */ +void pwmStart( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control |= 0x00400000U; +} + +/** @fn void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm) + * @brief Stop pwm signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * + * Stop the given pwm signal + */ +/* SourceId : HET_SourceId_003 */ +/* DesignId : HET_DesignId_003 */ +/* Requirements : CONQ_HET_SR12 */ +void pwmStop( hetRAMBASE_t * hetRAM, uint32 pwm ) +{ + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control &= ~( uint32 ) 0x00400000U; +} + +/** @fn void pwmSetDuty(hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty) + * @brief Set duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] pwmDuty duty cycle in %. + * + * Sets a new duty cycle on the given pwm signal + */ +/* SourceId : HET_SourceId_004 */ +/* DesignId : HET_DesignId_004 */ +/* Requirements : CONQ_HET_SR13 */ +void pwmSetDuty( hetRAMBASE_t * hetRAM, uint32 pwm, uint32 pwmDuty ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + uint32 pwmPeriod = hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U; + pwmPeriod = pwmPeriod >> 7U; + + if( hetRAM == hetRAM1 ) + { + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + if( pwmDuty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( pwmDuty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data = ( ( ( pwmPeriod * pwmDuty ) / 100U ) + << 7U ) + + 128U; +} + +/** @fn void pwmSetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) +* @brief Set period +* @param[in] hetRAM Pointer to HET RAM: +* - hetRAM1: HET1 RAM pointer +* - hetRAM2: HET2 RAM pointer +* @param[in] pwm Pwm signal: +* - pwm0: Pwm 0 +* - pwm1: Pwm 1 +* - pwm2: Pwm 2 +* - pwm3: Pwm 3 +* - pwm4: Pwm 4 +* - pwm5: Pwm 5 +* - pwm6: Pwm 6 +* - pwm7: Pwm 7 +* @param[in] signal signal + - duty cycle in %. +* - period period in us. +* +* Sets a new pwm signal +*/ +/* SourceId : HET_SourceId_005 */ +/* DesignId : HET_DesignId_005 */ +/* Requirements : CONQ_HET_SR14 */ +void pwmSetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal ) +{ + uint32 action; + uint32 pwmPolarity = 0U; + float64 pwmPeriod = 0.0F; + + if( hetRAM == hetRAM1 ) + { + pwmPeriod = ( signal.period * 1000.0F ) / 853.333F; + pwmPolarity = s_het1pwmPolarity[ pwm ]; + } + else + { + pwmPeriod = ( signal.period * 1000.0F ) / 853.333F; + pwmPolarity = s_het2pwmPolarity[ pwm ]; + } + if( signal.duty == 0U ) + { + action = ( pwmPolarity == 3U ) ? 0U : 2U; + } + else if( signal.duty >= 100U ) + { + action = ( pwmPolarity == 3U ) ? 2U : 0U; + } + else + { + action = pwmPolarity; + } + + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Control = ( ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Control ) + & ( ~( uint32 ) ( 0x00000018U ) ) ) + | ( action << 3U ); + hetRAM->Instruction[ ( pwm << 1U ) + 41U ] + .Data = ( ( ( ( uint32 ) pwmPeriod * signal.duty ) / 100U ) << 7U ) + 128U; + hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data = ( ( uint32 ) pwmPeriod << 7U ) + - 128U; +} + +/** @fn void pwmGetSignal(hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t signal) + * @brief Get duty cycle + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given pwm signal. + */ +/* SourceId : HET_SourceId_006 */ +/* DesignId : HET_DesignId_006 */ +/* Requirements : CONQ_HET_SR15 */ +void pwmGetSignal( hetRAMBASE_t * hetRAM, uint32 pwm, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( pwm << 1U ) + 41U ].Data - 128U ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( pwm << 1U ) + 42U ].Data + 128U ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } +} + +/** @fn void pwmEnableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_007 */ +/* DesignId : HET_DesignId_007 */ +/* Requirements : CONQ_HET_SR16 */ +void pwmEnableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->FLG = notification << ( pwm << 1U ); + hetREG->INTENAS = notification << ( pwm << 1U ); +} + +/** @fn void pwmDisableNotification(hetBASE_t * hetREG, uint32 pwm, uint32 notification) + * @brief Enable pwm notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] pwm Pwm signal: + * - pwm0: Pwm 0 + * - pwm1: Pwm 1 + * - pwm2: Pwm 2 + * - pwm3: Pwm 3 + * - pwm4: Pwm 4 + * - pwm5: Pwm 5 + * - pwm6: Pwm 6 + * - pwm7: Pwm 7 + * @param[in] notification Pwm notification: + * - pwmEND_OF_DUTY: Notification on end of duty + * - pwmEND_OF_PERIOD: Notification on end of end period + * - pwmEND_OF_BOTH: Notification on end of both duty and period + */ +/* SourceId : HET_SourceId_008 */ +/* DesignId : HET_DesignId_008 */ +/* Requirements : CONQ_HET_SR17 */ +void pwmDisableNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + hetREG->INTENAC = notification << ( pwm << 1U ); +} + +/** @fn void edgeResetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Resets edge counter to 0 + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Reset edge counter to 0. + */ +/* SourceId : HET_SourceId_009 */ +/* DesignId : HET_DesignId_009 */ +/* Requirements : CONQ_HET_SR19 */ +void edgeResetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + hetRAM->Instruction[ edge + 17U ].Data = 0U; +} + +/** @fn uint32 edgeGetCounter(hetRAMBASE_t * hetRAM, uint32 edge) + * @brief Get current edge counter value + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + * + * Gets current edge counter value. + */ +/* SourceId : HET_SourceId_010 */ +/* DesignId : HET_DesignId_010 */ +/* Requirements : CONQ_HET_SR20 */ +uint32 edgeGetCounter( hetRAMBASE_t * hetRAM, uint32 edge ) +{ + return hetRAM->Instruction[ edge + 17U ].Data >> 7U; +} + +/** @fn void edgeEnableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_011 */ +/* DesignId : HET_DesignId_011 */ +/* Requirements : CONQ_HET_SR21 */ +void edgeEnableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->FLG = ( uint32 ) 0x20000U << edge; + hetREG->INTENAS = ( uint32 ) 0x20000U << edge; +} + +/** @fn void edgeDisableNotification(hetBASE_t * hetREG, uint32 edge) + * @brief Enable edge notification + * @param[in] hetREG Pointer to HET Module: + * - hetREG1: HET1 Module pointer + * - hetREG2: HET2 Module pointer + * @param[in] edge Edge signal: + * - edge0: Edge 0 + * - edge1: Edge 1 + * - edge2: Edge 2 + * - edge3: Edge 3 + * - edge4: Edge 4 + * - edge5: Edge 5 + * - edge6: Edge 6 + * - edge7: Edge 7 + */ +/* SourceId : HET_SourceId_012 */ +/* DesignId : HET_DesignId_012 */ +/* Requirements : CONQ_HET_SR22 */ +void edgeDisableNotification( hetBASE_t * hetREG, uint32 edge ) +{ + hetREG->INTENAC = ( uint32 ) 0x20000U << edge; +} + +/** @fn void capGetSignal(hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t signal) + * @brief Get capture signal + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * @param[in] cap captured signal: + * - cap0: Captured signal 0 + * - cap1: Captured signal 1 + * - cap2: Captured signal 2 + * - cap3: Captured signal 3 + * - cap4: Captured signal 4 + * - cap5: Captured signal 5 + * - cap6: Captured signal 6 + * - cap7: Captured signal 7 + * @param[in] signal signal + * - duty cycle in %. + * - period period in us. + * + * Gets current signal of the given capture signal. + */ +/* SourceId : HET_SourceId_013 */ +/* DesignId : HET_DesignId_013 */ +/* Requirements : CONQ_HET_SR24 */ +void capGetSignal( hetRAMBASE_t * hetRAM, uint32 cap, hetSIGNAL_t * signal ) +{ + uint32 pwmDuty = ( hetRAM->Instruction[ ( cap << 1U ) + 25U ].Data ) >> 7U; + uint32 pwmPeriod = ( hetRAM->Instruction[ ( cap << 1U ) + 26U ].Data ) >> 7U; + + signal->duty = ( pwmDuty * 100U ) / pwmPeriod; + + if( hetRAM == hetRAM1 ) + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } + else + { + signal->period = ( ( float64 ) pwmPeriod * 853.333F ) / 1000.0F; + } +} + +/** @fn void hetResetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Resets timestamp + * @param[in] hetRAM Pointer to HET RAM: + * - hetRAM1: HET1 RAM pointer + * - hetRAM2: HET2 RAM pointer + * + * Resets loop count based timestamp. + */ +/* SourceId : HET_SourceId_014 */ +/* DesignId : HET_DesignId_014 */ +/* Requirements : CONQ_HET_SR25 */ +void hetResetTimestamp( hetRAMBASE_t * hetRAM ) +{ + hetRAM->Instruction[ 0U ].Data = 0U; +} + +/** @fn uint32 hetGetTimestamp(hetRAMBASE_t *hetRAM) + * @brief Returns timestamp + * + * Returns loop count based timestamp. + */ +/* SourceId : HET_SourceId_015 */ +/* DesignId : HET_DesignId_015 */ +/* Requirements : CONQ_HET_SR26 */ +uint32 hetGetTimestamp( hetRAMBASE_t * hetRAM ) +{ + return hetRAM->Instruction[ 57U ].Data; +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ + +/** @fn void het1GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_016 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : CONQ_HET_SR29 */ +void het1GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET1_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET1_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET1_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET1_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET1_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET1_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET1_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET1_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET1_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET1_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET1_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET1_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET1_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG1->GCR; + config_reg->CONFIG_PFR = hetREG1->PFR; + config_reg->CONFIG_INTENAS = hetREG1->INTENAS; + config_reg->CONFIG_INTENAC = hetREG1->INTENAC; + config_reg->CONFIG_PRY = hetREG1->PRY; + config_reg->CONFIG_AND = hetREG1->AND; + config_reg->CONFIG_HRSH = hetREG1->HRSH; + config_reg->CONFIG_XOR = hetREG1->XOR; + config_reg->CONFIG_DIR = hetREG1->DIR; + config_reg->CONFIG_PDR = hetREG1->PDR; + config_reg->CONFIG_PULDIS = hetREG1->PULDIS; + config_reg->CONFIG_PSL = hetREG1->PSL; + config_reg->CONFIG_PCR = hetREG1->PCR; + } +} + +/** @fn void het2GetConfigValue(het_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the HET2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +/* SourceId : HET_SourceId_017 */ +/* DesignId : HET_DesignId_016 */ +/* Requirements : CONQ_HET_SR29 */ +void het2GetConfigValue( het_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR = HET2_GCR_CONFIGVALUE; + config_reg->CONFIG_PFR = HET2_PFR_CONFIGVALUE; + config_reg->CONFIG_INTENAS = HET2_INTENAS_CONFIGVALUE; + config_reg->CONFIG_INTENAC = HET2_INTENAC_CONFIGVALUE; + config_reg->CONFIG_PRY = HET2_PRY_CONFIGVALUE; + config_reg->CONFIG_AND = HET2_AND_CONFIGVALUE; + config_reg->CONFIG_HRSH = HET2_HRSH_CONFIGVALUE; + config_reg->CONFIG_XOR = HET2_XOR_CONFIGVALUE; + config_reg->CONFIG_DIR = HET2_DIR_CONFIGVALUE; + config_reg->CONFIG_PDR = HET2_PDR_CONFIGVALUE; + config_reg->CONFIG_PULDIS = HET2_PULDIS_CONFIGVALUE; + config_reg->CONFIG_PSL = HET2_PSL_CONFIGVALUE; + config_reg->CONFIG_PCR = HET2_PCR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_GCR = hetREG2->GCR; + config_reg->CONFIG_PFR = hetREG2->PFR; + config_reg->CONFIG_INTENAS = hetREG2->INTENAS; + config_reg->CONFIG_INTENAC = hetREG2->INTENAC; + config_reg->CONFIG_PRY = hetREG2->PRY; + config_reg->CONFIG_AND = hetREG2->AND; + config_reg->CONFIG_HRSH = hetREG2->HRSH; + config_reg->CONFIG_XOR = hetREG2->XOR; + config_reg->CONFIG_DIR = hetREG2->DIR; + config_reg->CONFIG_PDR = hetREG2->PDR; + config_reg->CONFIG_PULDIS = hetREG2->PULDIS; + config_reg->CONFIG_PSL = hetREG2->PSL; + config_reg->CONFIG_PCR = hetREG2->PCR; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c new file mode 100644 index 00000000000..fb2de140c7b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/i2c.c @@ -0,0 +1,1005 @@ +/** @file i2c.c + * @brief I2C Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "i2c.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_i2CTransfer + * @brief Interrupt mode globals + * + */ +static struct g_i2cTransfer +{ + uint32 mode; + uint32 length; + uint8 * data; +} g_i2cTransfer_t[ 2U ]; + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* SourceId : I2C_SourceId_001 */ +/* DesignId : I2C_DesignId_001 */ +/* Requirements : CONQ_I2C_SR5 */ +/** @fn void i2cInit(void) + * @brief Initializes the i2c Driver + * + * This function initializes the i2c module. + */ +void i2cInit( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + /** @b initialize @b I2C1 */ + + /** - i2c Enter reset */ + i2cREG1->MDR = ( uint32 ) ( ( uint32 ) 0U << 5U ); + + /** - set i2c mode */ + i2cREG1->MDR = ( uint32 ) ( ( uint32 ) 0U << 15U ) /* nack mode */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* free running */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* start condition - master mode + only */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* stop condition */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* Master/Slave mode */ + | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) /* Transmitter/receiver */ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) /* xpanded address */ + | ( uint32 ) ( ( uint32 ) 0U << 7U ) /* repeat mode */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* digital loopback */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* start byte - master only */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* free data format */ + | ( uint32 ) ( ( uint32 ) I2C_8_BIT ); /* bit count */ + + /** - set i2c extended mode */ + i2cREG1->EMDR = ( uint32 ) 0U << 1U; /* Ignore Nack Enable/Disable */ + + /** - set i2c Backward Compatibility mode */ + i2cREG1->EMDR |= 0U; + + /** - Disable DMA */ + i2cREG1->DMACR = 0x00U; + + /** - set i2c data count */ + i2cREG1->CNT = 8U; + + /** - disable all interrupts */ + i2cREG1->IMR = 0x00U; + + /** - set prescale */ + i2cREG1->PSC = 8U; + + /** - set clock rate */ + i2cREG1->CKH = 37U; + i2cREG1->CKL = 37U; + + /** - set i2c pins functional mode */ + i2cREG1->PFNC = ( 0U ); + + /** - set i2c pins default output value */ + i2cREG1->DOUT = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG1->DIR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG1->PDR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG1->PDIS = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG1->PSEL = ( uint32 ) ( ( uint32 ) 1U << 1U ) /* sda pin */ + | ( uint32 ) ( 1U ); /* scl pin */ + + /** - set interrupt enable */ + i2cREG1->IMR = ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Address as slave interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Stop Condition detect interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Transmit data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Receive data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Register Access ready interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* No Acknowledgment interrupt */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Arbitration Lost interrupt */ + + i2cREG1->MDR |= ( uint32 ) I2C_RESET_OUT; /* i2c out of reset */ + + /** - initialize global transfer variables */ + g_i2cTransfer_t[ 0U ].mode = ( uint32 ) 0U << 4U; + g_i2cTransfer_t[ 0U ].length = 0U; + + /** @b initialize @b I2C2 */ + + /** - i2c Enter reset */ + i2cREG2->MDR = ( uint32 ) ( ( uint32 ) 0U << 5U ); + + /** - set i2c mode */ + i2cREG2->MDR = ( uint32 ) ( ( uint32 ) 0U << 15U ) /* nack mode */ + | ( uint32 ) ( ( uint32 ) 0U << 14U ) /* free running */ + | ( uint32 ) ( ( uint32 ) 0U << 13U ) /* start condition - master mode + only */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* stop condition */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* Master/Slave mode */ + | ( uint32 ) ( ( uint32 ) I2C_TRANSMITTER ) /* Transmitter/receiver */ + | ( uint32 ) ( ( uint32 ) I2C_7BIT_AMODE ) /* Expanded address */ + | ( uint32 ) ( ( uint32 ) 0 << 7U ) /* repeat mode */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* digital loopback */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* start byte - master only */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* free data format */ + | ( uint32 ) ( I2C_2_BIT ); /* bit count */ + + /** - set i2c extended mode */ + i2cREG2->EMDR = ( uint32 ) 0U << 1U; /* Ignore Nack Enable/Disable */ + + /** - set i2c Backward Compatibility mode */ + i2cREG2->EMDR |= 0U; + + /** - Disable DMA */ + i2cREG2->DMACR = 0x00U; + + /** - set i2c data count */ + i2cREG2->CNT = 8U; + + /** - disable all interrupts */ + i2cREG2->IMR = 0x00U; + + /** - set prescale */ + i2cREG2->PSC = 8U; + + /** - set clock rate */ + i2cREG2->CKH = 37U; + i2cREG2->CKL = 37U; + + /** - set i2c pins functional mode */ + i2cREG2->PFNC = ( 0U ); + + /** - set i2c pins default output value */ + i2cREG2->DOUT = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins output direction */ + i2cREG2->DIR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins open drain enable */ + i2cREG2->PDR = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown enable */ + i2cREG2->PDIS = ( uint32 ) ( ( uint32 ) 0U << 1U ) /* sda pin */ + | ( uint32 ) ( 0U ); /* scl pin */ + + /** - set i2c pins pullup/pulldown select */ + i2cREG2->PSEL = ( uint32 ) ( ( uint32 ) 1U << 1U ) /* sda pin */ + | ( uint32 ) ( 1U ); /* scl pin */ + + /** - set interrupt enable */ + i2cREG2->IMR = ( uint32 ) ( ( uint32 ) 0U << 6U ) /* Address as slave interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* Stop Condition detect interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* Transmit data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* Receive data ready interrupt */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* Register Access ready interrupt + */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* No Acknowledgment interrupt */ + | ( uint32 ) ( 0U ); /* Arbitration Lost interrupt */ + + i2cREG2->MDR |= ( uint32 ) I2C_RESET_OUT; /* i2c out of reset */ + + /** - initialize global transfer variables */ + g_i2cTransfer_t[ 1U ].mode = ( uint32 ) 0U << 4U; + g_i2cTransfer_t[ 1U ].length = 0U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_002 */ +/* DesignId : I2C_DesignId_002 */ +/* Requirements : CONQ_I2C_SR6 */ +/** @fn void i2cSetOwnAdd(i2cBASE_t *i2c, uint32 oadd) + * @brief Set I2C Own Address + * @param[in] oadd - I2C Own address (7-bit or 10 -bit address) + * @param[in] i2c - i2c module base address + * Set the Own address of the I2C module. + */ +void i2cSetOwnAdd( i2cBASE_t * i2c, uint32 oadd ) +{ + i2c->OAR = oadd; /* set own address */ +} + +/* SourceId : I2C_SourceId_003 */ +/* DesignId : I2C_DesignId_003 */ +/* Requirements : CONQ_I2C_SR7 */ +/** @fn void i2cSetSlaveAdd(i2cBASE_t *i2c, uint32 sadd) + * @brief Set Port Direction + * @param[in] sadd - I2C Slave address + * @param[in] i2c - i2c module base address + * Set the Slave address to communicate which is must in Master mode. + */ +void i2cSetSlaveAdd( i2cBASE_t * i2c, uint32 sadd ) +{ + i2c->SAR = sadd; /* set slave address */ +} + +/* SourceId : I2C_SourceId_004 */ +/* DesignId : I2C_DesignId_004 */ +/* Requirements : CONQ_I2C_SR8 */ +/** @fn void i2cSetBaudrate(i2cBASE_t *i2c, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] i2c - i2c module base address + * @param[in] baud - baudrate in KHz + * + * Change the i2c baudrate at runtime. The I2C module needs to be taken to reset( nIRS=0 + * in I2CMDR) in order to change baud rate. + */ +void i2cSetBaudrate( i2cBASE_t * i2c, uint32 baud ) +{ + uint32 prescale; + uint32 d; + uint32 ck; + float64 vclk = 75.000F * 1000000.0F; + float64 divider = 0.0F; + uint32 temp = 0U; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + divider = vclk / 8000000.0F; + prescale = ( uint32 ) divider - 1U; + + if( prescale >= 2U ) + { + d = 5U; + } + else + { + d = ( prescale != 0U ) ? 6U : 7U; + } + + temp = 2U * baud * 1000U * ( prescale + 1U ); + divider = vclk / ( ( float64 ) temp ); + ck = ( uint32 ) divider - d; + + i2c->PSC = prescale; + i2c->CKH = ck; + i2c->CKL = ck; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_005 */ +/* DesignId : I2C_DesignId_015 */ +/* Requirements : CONQ_I2C_SR20 */ +/** @fn void i2cSetStart(i2cBASE_t *i2c) + * @brief Set i2c start condition + * @param[in] i2c - i2c module base address + * Set i2c to generate a start bit (Only in Master mode) + */ +void i2cSetStart( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + i2c->MDR |= ( uint32 ) I2C_START_COND; /* set start condition */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_006 */ +/* DesignId : I2C_DesignId_016 */ +/* Requirements : CONQ_I2C_SR21 */ +/** @fn void i2cSetStop(i2cBASE_t *i2c) + * @brief Set i2c stop condition + * @param[in] i2c - i2c module base address + * Set i2c to generate a stop bit (Only in Master mode) + */ +void i2cSetStop( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + i2c->MDR |= ( uint32 ) I2C_STOP_COND; /* generate stop condition */ + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_007 */ +/* DesignId : I2C_DesignId_017 */ +/* Requirements : CONQ_I2C_SR22 */ +/** @fn void i2cSetCount(i2cBASE_t *i2c,uint32 cnt) + * @brief Set i2c data count + * @param[in] i2c - i2c module base address + * @param[in] cnt - data count + * Set i2c count to a transfer value after which the stop condition needs to be + * generated. (Only in Master Mode) + */ +void i2cSetCount( i2cBASE_t * i2c, uint32 cnt ) +{ + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + i2c->CNT = cnt; /* set i2c count */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_008 */ +/* DesignId : I2C_DesignId_005 */ +/* Requirements : CONQ_I2C_SR9 */ +/** @fn uint32 i2cIsTxReady(i2cBASE_t *i2c) + * @brief Check if Tx buffer empty + * @param[in] i2c - i2c module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 i2cIsTxReady( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return i2c->STR & ( uint32 ) I2C_TX_INT; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_009 */ +/* DesignId : I2C_DesignId_006 */ +/* Requirements : CONQ_I2C_SR10 */ +/** @fn void i2cSendByte(i2cBASE_t *i2c, uint8 byte) + * @brief Send Byte + * @param[in] i2c - i2c module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use i2cIsTxReady to check for Tx buffer empty + * before calling i2cSendByte to avoid waiting. + */ +void i2cSendByte( i2cBASE_t * i2c, uint8 byte ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_TX_INT ) == 0U ) + { + } /* Wait */ + i2c->DXR = ( uint32 ) byte; + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_010 */ +/* DesignId : I2C_DesignId_007 */ +/* Requirements : CONQ_I2C_SR11 */ +/** @fn void i2cSend(i2cBASE_t *i2c, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] i2c - i2c module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, i2cSend must not be called again until the + * transfer is complete, when the i2cNotification callback will + * be called. In polling mode, i2cSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +void i2cSend( i2cBASE_t * i2c, uint32 length, uint8 * data ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( g_i2cTransfer_t[ index ].mode & ( uint32 ) I2C_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + i2c->DXR = ( uint32 ) *g_i2cTransfer_t[ index ].data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data++; + /* Length -1 since one data is written already */ + g_i2cTransfer_t[ index ].length = ( length - 1U ); + /* Enable Transmit Interrupt */ + i2c->IMR |= ( uint32 ) I2C_TX_INT; + } + else + { + /* send the data */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in + * Transmit/Receive polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_TX_INT ) == 0U ) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + i2c->DXR = ( uint32 ) *data; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; + length--; + } + } + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_011 */ +/* DesignId : I2C_DesignId_008 */ +/* Requirements : CONQ_I2C_SR12 */ +/** @fn uint32 i2cIsRxReady(i2cBASE_t *i2c) + * @brief Check if Rx buffer full + * @param[in] i2c - i2c module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 i2cIsRxReady( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return i2c->STR & ( uint32 ) I2C_RX_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_012 */ +/* DesignId : I2C_DesignId_023 */ +/* Requirements : CONQ_I2C_SR13 */ +/** @fn uint32 i2cIsStopDetected(i2cBASE_t *i2c) + * @brief Check if Stop Condition Detected + * @param[in] i2c - i2c module base address + * + * @return The Stop Condition Detected flag + * + * Checks to see if the Stop Condition Detected flag is set, + * returns 0 if flags not set otherwise will return the Stop + * Condition Detected flag itself. + */ +uint32 i2cIsStopDetected( i2cBASE_t * i2c ) +{ + return i2c->STR & ( uint32 ) I2C_SCD_INT; +} + +/* SourceId : I2C_SourceId_013 */ +/* DesignId : I2C_DesignId_010 */ +/* Requirements : CONQ_I2C_SR15 */ +/** @fn uint32 i2cRxError(i2cBASE_t *i2c) + * @brief Return Rx Error flags + * @param[in] i2c - i2c module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +uint32 i2cRxError( i2cBASE_t * i2c ) +{ + uint32 status = i2c->STR & ( ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + i2c->STR = ( uint32 ) ( ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : I2C_SourceId_014 */ +/* DesignId : I2C_DesignId_009 */ +/* Requirements : CONQ_I2C_SR14 */ +/** @fn void i2cClearSCD(i2cBASE_t *i2c) + * @brief Clears the Stop condition detect flags. + * @param[in] i2c - i2c module base address + * + * This function is called to clear the Stop condition detect(SCD) flag + */ +void i2cClearSCD( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + i2c->STR = ( uint32 ) I2C_SCD_INT; + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_015 */ +/* DesignId : I2C_DesignId_011 */ +/* Requirements : CONQ_I2C_SR16 */ +/** @fn uint8 i2cReceiveByte(i2cBASE_t *i2c) + * @brief Receive Byte + * @param[in] i2c - i2c module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use i2cIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +uint8 i2cReceiveByte( i2cBASE_t * i2c ) +{ + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_RX_INT ) == 0U ) + { + } /* Wait */ + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + return ( ( uint8 ) i2c->DRR ); +} + +/* SourceId : I2C_SourceId_016 */ +/* DesignId : I2C_DesignId_012 */ +/* Requirements : CONQ_I2C_SR17 */ +/** @fn void i2cReceive(i2cBASE_t *i2c, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] i2c - i2c module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, i2cReceive must not be called + * again until the transfer is complete, when the i2cNotification + * callback will be called. In polling mode, i2cReceive will not + * return until the transfer is complete. + */ +void i2cReceive( i2cBASE_t * i2c, uint32 length, uint8 * data ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + if( ( i2c->IMR & ( uint32 ) I2C_RX_INT ) != 0U ) + { + /* we are in interrupt mode */ + /* clear error flags */ + i2c->STR = ( uint32 ) I2C_AL_INT | ( uint32 ) I2C_NACK_INT; + + g_i2cTransfer_t[ index ].length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_i2cTransfer_t[ index ].data = data; + } + else + { /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in Transmit/Receive + polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( i2c->STR & ( uint32 ) I2C_RX_INT ) == 0U ) + { + } /* Wait */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( ( uint8 ) i2c->DRR ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_017 */ +/* DesignId : I2C_DesignId_018 */ +/* Requirements : CONQ_I2C_SR24 */ +/** @fn void i2cEnableLoopback(i2cBASE_t *i2c) + * @brief Enable Loopback mode for self test + * @param[in] i2c - i2c module base address + * + * This function enables the Loopback mode for self test. + */ +void i2cEnableLoopback( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + /* enable digital loopback */ + i2c->MDR |= ( ( uint32 ) 1U << 6U ); + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_018 */ +/* DesignId : I2C_DesignId_019 */ +/* Requirements : CONQ_I2C_SR25 */ +/** @fn void i2cDisableLoopback(i2cBASE_t *i2c) + * @brief Enable Loopback mode for self test + * @param[in] i2c - i2c module base address + * + * This function disable the Loopback mode. + */ +void i2cDisableLoopback( i2cBASE_t * i2c ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + i2c->MDR &= 0xFFFFFFBFU; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_019 */ +/* DesignId : I2C_DesignId_013 */ +/* Requirements : CONQ_I2C_SR18 */ +/** @fn i2cEnableNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Enable interrupts + * @param[in] i2c - i2c module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * i2c_FE_INT - framing error, + * i2c_OE_INT - overrun error, + * i2c_PE_INT - parity error, + * i2c_RX_INT - receive buffer ready, + * i2c_TX_INT - transmit buffer ready, + * i2c_WAKE_INT - wakeup, + * i2c_BREAK_INT - break detect + */ +void i2cEnableNotification( i2cBASE_t * i2c, uint32 flags ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + g_i2cTransfer_t[ index ].mode |= ( flags & ( uint32 ) I2C_TX_INT ); + i2c->IMR = ( flags & ( uint32 ) ( ~( uint32 ) I2C_TX_INT ) ); +} + +/* SourceId : I2C_SourceId_020 */ +/* DesignId : I2C_DesignId_014 */ +/* Requirements : CONQ_I2C_SR19 */ +/** @fn i2cDisableNotification(i2cBASE_t *i2c, uint32 flags) + * @brief Disable interrupts + * @param[in] i2c - i2c module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * i2c_FE_INT - framing error, + * i2c_OE_INT - overrun error, + * i2c_PE_INT - parity error, + * i2c_RX_INT - receive buffer ready, + * i2c_TX_INT - transmit buffer ready, + * i2c_WAKE_INT - wakeup, + * i2c_BREAK_INT - break detect + */ +void i2cDisableNotification( i2cBASE_t * i2c, uint32 flags ) +{ + uint32 index = i2c == i2cREG1 ? 0U : 1U; + uint32 int_mask; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + g_i2cTransfer_t[ index ].mode &= ( uint32 ) ~( flags & ( uint32 ) I2C_TX_INT ); + int_mask = i2c->IMR & ( uint32 ) ( ~( uint32 ) ( flags | ( uint32 ) I2C_TX_INT ) ); + i2c->IMR = int_mask; +} + +/* SourceId : I2C_SourceId_021 */ +/* DesignId : I2C_DesignId_020 */ +/* Requirements : CONQ_I2C_SR23 */ +/** @fn i2cSetMode(i2cBASE_t *i2c, uint32 mode) + * @brief Sets Master or Slave mode. + * @param[in] i2c - i2c module base address + * @param[in] mode - Mode can be either: + * I2C_MASTER - Master Mode, + * I2C_SLAVE - Slave Mode + */ +void i2cSetMode( i2cBASE_t * i2c, uint32 mode ) +{ + uint32 temp_mdr; + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* set Master or Slave Mode */ + temp_mdr = ( i2c->MDR & ( ~I2C_MASTER ) ); + i2c->MDR = ( temp_mdr | mode ); + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/* SourceId : I2C_SourceId_022 */ +/* DesignId : I2C_DesignId_021 */ +/* Requirements : CONQ_I2C_SR28 */ +/** @fn void i2c1GetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the I2C1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void i2c1GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OAR = I2C1_OAR_CONFIGVALUE; + config_reg->CONFIG_IMR = I2C1_IMR_CONFIGVALUE; + config_reg->CONFIG_CLKL = I2C1_CLKL_CONFIGVALUE; + config_reg->CONFIG_CLKH = I2C1_CLKH_CONFIGVALUE; + config_reg->CONFIG_CNT = I2C1_CNT_CONFIGVALUE; + config_reg->CONFIG_SAR = I2C1_SAR_CONFIGVALUE; + config_reg->CONFIG_MDR = I2C1_MDR_CONFIGVALUE; + config_reg->CONFIG_EMDR = I2C1_EMDR_CONFIGVALUE; + config_reg->CONFIG_PSC = I2C1_PSC_CONFIGVALUE; + config_reg->CONFIG_DMAC = I2C1_DMAC_CONFIGVALUE; + config_reg->CONFIG_FUN = I2C1_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = I2C1_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = I2C1_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = I2C1_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = I2C1_PSL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_OAR = i2cREG1->OAR; + config_reg->CONFIG_IMR = i2cREG1->IMR; + config_reg->CONFIG_CLKL = i2cREG1->CKL; + config_reg->CONFIG_CLKH = i2cREG1->CKH; + config_reg->CONFIG_CNT = i2cREG1->CNT; + config_reg->CONFIG_SAR = i2cREG1->SAR; + config_reg->CONFIG_MDR = i2cREG1->MDR; + config_reg->CONFIG_EMDR = i2cREG1->EMDR; + config_reg->CONFIG_PSC = i2cREG1->PSC; + config_reg->CONFIG_DMAC = i2cREG1->DMACR; + config_reg->CONFIG_FUN = i2cREG1->PFNC; + config_reg->CONFIG_DIR = i2cREG1->DIR; + config_reg->CONFIG_ODR = i2cREG1->PDR; + config_reg->CONFIG_PD = i2cREG1->PDIS; + config_reg->CONFIG_PSL = i2cREG1->PSEL; + } +} + +/* SourceId : I2C_SourceId_023 */ +/* DesignId : I2C_DesignId_021 */ +/* Requirements : CONQ_I2C_SR29 */ +/** @fn void i2c2GetConfigValue(i2c_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the I2C1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + * be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void i2c2GetConfigValue( i2c_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_OAR = I2C2_OAR_CONFIGVALUE; + config_reg->CONFIG_IMR = I2C2_IMR_CONFIGVALUE; + config_reg->CONFIG_CLKL = I2C2_CLKL_CONFIGVALUE; + config_reg->CONFIG_CLKH = I2C2_CLKH_CONFIGVALUE; + config_reg->CONFIG_CNT = I2C2_CNT_CONFIGVALUE; + config_reg->CONFIG_SAR = I2C2_SAR_CONFIGVALUE; + config_reg->CONFIG_MDR = I2C2_MDR_CONFIGVALUE; + config_reg->CONFIG_EMDR = I2C2_EMDR_CONFIGVALUE; + config_reg->CONFIG_PSC = I2C2_PSC_CONFIGVALUE; + config_reg->CONFIG_DMAC = I2C2_DMAC_CONFIGVALUE; + config_reg->CONFIG_FUN = I2C2_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = I2C2_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = I2C2_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = I2C2_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = I2C2_PSL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_OAR = i2cREG2->OAR; + config_reg->CONFIG_IMR = i2cREG2->IMR; + config_reg->CONFIG_CLKL = i2cREG2->CKL; + config_reg->CONFIG_CLKH = i2cREG2->CKH; + config_reg->CONFIG_CNT = i2cREG2->CNT; + config_reg->CONFIG_SAR = i2cREG2->SAR; + config_reg->CONFIG_MDR = i2cREG2->MDR; + config_reg->CONFIG_EMDR = i2cREG2->EMDR; + config_reg->CONFIG_PSC = i2cREG2->PSC; + config_reg->CONFIG_DMAC = i2cREG2->DMACR; + config_reg->CONFIG_FUN = i2cREG2->PFNC; + config_reg->CONFIG_DIR = i2cREG2->DIR; + config_reg->CONFIG_ODR = i2cREG2->PDR; + config_reg->CONFIG_PD = i2cREG2->PDIS; + config_reg->CONFIG_PSL = i2cREG2->PSEL; + } +} + +/** @fn i2cSetDirection(i2cBASE_t *i2c, uint32 dir) + * @brief Sets I2C as transmitter or receiver. + * @param[in] i2c - i2c module base address + * @param[in] dir - This can be one of the following: + * I2C_TRANSMITTER - Transmit Mode, + * I2C_RECEIVER - Receive Mode + */ +/* SourceId : I2C_SourceId_026 */ +/* DesignId : */ +/* Requirements : */ +void i2cSetDirection( i2cBASE_t * i2c, uint32 dir ) +{ + /* USER CODE BEGIN (58) */ + /* USER CODE END */ + + /* set Transmit/Receive mode */ + i2c->MDR &= ~I2C_TRANSMITTER; + i2c->MDR |= dir; + + /* USER CODE BEGIN (59) */ + /* USER CODE END */ +} + +/** @fn i2cIsMasterReady(i2cBASE_t *i2c) + * @brief Indicates whether MST bit is set or cleared to indicate that stop + * condition was generated. This API should be called after Master Tx or Rx + * to check if the transaction is complete. + * @param[in] i2c - i2c module base address + * @return boolean value to indicate whether MST bit is cleared after STOP bit is + * generated. + * - TRUE, if MST bit is cleared. + * - FALSE, if MST bit is set. + */ +/* SourceId : I2C_SourceId_027 */ +/* DesignId : */ +/* Requirements : */ +bool i2cIsMasterReady( i2cBASE_t * i2c ) +{ + bool retVal = 0U; + /* USER CODE BEGIN (60) */ + /* USER CODE END */ + + /* check if MST bit is cleared. */ + if( ( i2c->MDR & I2C_MASTER ) == 0 ) + { + retVal = true; + } + else + { + retVal = false; + } + return retVal; + + /* USER CODE BEGIN (61) */ + /* USER CODE END */ +} + +/** @fn i2cIsBusBusy(i2cBASE_t *i2c) + * @brief Returns the state of the bus busy flag. True if it is set and false otherwise. + * @param[in] i2c - i2c module base address + * @return boolean value to indicate whether BB bit is set in the status register. + * - TRUE, if BB bit is set. + * - FALSE, if BB bit is cleared. + */ +/* SourceId : I2C_SourceId_028 */ +/* DesignId : */ +/* Requirements : */ +bool i2cIsBusBusy( i2cBASE_t * i2c ) +{ + bool retVal = 0U; + /* USER CODE BEGIN (62) */ + /* USER CODE END */ + + /* check if BB bit is set. */ + if( ( i2c->STR & I2C_BUSBUSY ) == I2C_BUSBUSY ) + { + retVal = true; + } + else + { + retVal = false; + } + return retVal; + + /* USER CODE BEGIN (63) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c new file mode 100644 index 00000000000..265d2415ba0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/lin.c @@ -0,0 +1,943 @@ +/** @file lin.c + * @brief LIN Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "lin.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : LIN_SourceId_001 */ +/* DesignId : LIN_DesignId_001 */ +/* Requirements : CONQ_LIN_SR5 */ +/** @fn void linInit(void) + * @brief Initializes the lin Driver + * + * This function initializes the lin module. + */ +void linInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG1->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG1->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG1->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module either as master/salve + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG1->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG1->MBRSR = ( uint32 ) 3370U; + + /** - Setup baud rate prescaler */ + linREG1->BRS = ( uint32 ) 233U; + + /** - Setup RX and TX reception masks */ + linREG1->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG1->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG1->FORMAT = ( ( linREG1->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG1->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG1->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG1->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG1->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG1->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG1->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG1->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG1->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG1->GCR1 |= 0x00000080U; + + /** @b initialize @b LIN */ + + /** - Release from reset */ + linREG2->GCR0 = 1U; + + /** - Start LIN configuration + * - Keep state machine in software reset + */ + linREG2->GCR1 = 0U; + + /** - Enable LIN Mode */ + linREG2->GCR1 = 0x40U; + + /** - Setup control register 1 + * - Enable transmitter + * - Enable receiver + * - Stop when debug mode is entered + * - Disable Loopback mode + * - Disable / Enable HGENCTRL (Mask filtering with ID-Byte) + * - Use enhance checksum + * - Enable multi buffer mode + * - Disable automatic baudrate adjustment + * - Disable sleep mode + * - Set LIN module either as master/salve + * - Enable/Disable parity + * - Disable data length control in ID4 and ID5 + */ + linREG2->GCR1 |= 0x03000C40U | ( uint32 ) ( ( uint32 ) 1U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 1U << 5U ); + + /** - Setup maximum baud rate prescaler */ + linREG2->MBRSR = ( uint32 ) 3370U; + + /** - Setup baud rate prescaler */ + linREG2->BRS = ( uint32 ) 233U; + + /** - Setup RX and TX reception masks */ + linREG2->MASK = ( ( uint32 ) ( ( uint32 ) 0xFFU << 16U ) | ( uint32 ) 0xFFU ); + + /** - Setup compare + * - Sync delimiter + * - Sync break extension + */ + linREG2->COMP = ( ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( ( uint32 ) 13U - 13U ) ); + + /** - Setup response length */ + linREG2->FORMAT = ( ( linREG2->FORMAT & 0xFFF8FFFFU ) + | ( uint32 ) ( ( ( uint32 ) 8U - 1U ) << 16U ) ); + + /** - Set LIN pins functional mode + * - TX + * - RX + * - CLK + */ + linREG2->PIO0 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 0U ); + + /** - Set LIN pins default output value + * - TX + * - RX + * - CLK + */ + linREG2->PIO3 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins output direction + * - TX + * - RX + * - CLK + */ + linREG2->PIO1 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins open drain enable + * - TX + * - RX + * - CLK + */ + linREG2->PIO6 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown enable + * - TX + * - RX + * - CLK + */ + linREG2->PIO7 = ( ( uint32 ) 0U | ( uint32 ) 0U | ( uint32 ) 0U ); + + /** - Set LIN pins pullup/pulldown select + * - TX + * - RX + * - CLK + */ + linREG2->PIO8 = ( ( uint32 ) 4U | ( uint32 ) 2U | ( uint32 ) 1U ); + + /** - Set interrupt level + * - Bit error level + * - Physical bus error level + * - Checksum error level + * - Inconsistent sync field error level + * - No response error level + * - Framing error level + * - Overrun error level + * - Parity error level + * - Identifier level + * - RX level + * - TX level + * - Timeout after 3 wakeup signals level + * - Timeout after wakeup signal level + * - Timeout level + * - Wakeup level + * - Break detect level + */ + linREG2->SETINTLVL = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Set interrupt enable + * - Enable/Disable bit error + * - Enable/Disable physical bus error level + * - Enable/Disable checksum error level + * - Enable/Disable inconsistent sync field error level + * - Enable/Disable no response error level + * - Enable/Disable framing error level + * - Enable/Disable overrun error level + * - Enable/Disable parity error level + * - Enable/Disable identifier level + * - Enable/Disable RX level + * - Enable/Disable TX level + * - Enable/Disable timeout after 3 wakeup signals level + * - Enable/Disable timeout after wakeup signal level + * - Enable/Disable timeout level + * - Enable/Disable wakeup level + * - Enable/Disable break detect level + */ + linREG2->SETINT = ( ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U + | ( uint32 ) 0x00000000U | ( uint32 ) 0x00000000U ); + + /** - Finaly start LIN */ + linREG2->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_002 */ +/* DesignId : LIN_DesignId_002 */ +/* Requirements : CONQ_LIN_SR6 */ +/** @fn void linSetFunctional(linBASE_t *lin, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] lin - lin module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCFUN register at runtime, this allows to + * dynamically change the functionality of the LIN pins between functional + * and GIO mode. + */ +void linSetFunctional( linBASE_t * lin, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + lin->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_003 */ +/* DesignId : LIN_DesignId_003 */ +/* Requirements : CONQ_LIN_SR7 */ +/** @fn void linSendHeader(linBASE_t *lin, uint8 identifier) + * @brief Send lin header. + * @param[in] lin - lin module base address + * @param[in] identifier - lin header id + * + * Send lin header including sync break field, sync field and identifier. + */ +void linSendHeader( linBASE_t * lin, uint8 identifier ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + lin->ID = ( ( lin->ID & 0xFFFFFF00U ) | ( uint32 ) identifier ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_004 */ +/* DesignId : LIN_DesignId_004 */ +/* Requirements : CONQ_LIN_SR8 */ +/** @fn void linSendWakupSignal(linBASE_t *lin) + * @brief Send lin wakeup signal. + * @param[in] lin - lin module base address + * + * Send lin wakeup signal to terminate the sleep mode of any lin node connected to the + * BUS. + */ +void linSendWakupSignal( linBASE_t * lin ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + lin->TDx[ 0U ] = 0xF0U; + lin->GCR2 |= 0x00000100U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_005 */ +/* DesignId : LIN_DesignId_005 */ +/* Requirements : CONQ_LIN_SR9 */ +/** @fn void linEnterSleep(linBASE_t *lin) + * @brief Take Module to Sleep. + * @param[in] lin - lin module base address + * + * Application must call this function to take Module to Sleep when Sleep command is + * received. This function can also be called to forcefully enter Sleep when no activity + * on BUS. + */ +void linEnterSleep( linBASE_t * lin ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + lin->GCR2 |= 0x00000001U; + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_006 */ +/* DesignId : LIN_DesignId_006 */ +/* Requirements : CONQ_LIN_SR10 */ +/** @fn void linSoftwareReset(linBASE_t *lin) + * @brief Perform software reset. + * @param[in] lin - lin module base address + * + * Perform software reset of lin module. + * This function will reset the lin state machine and clear all pending flags. + * It is required to call this function after a wakeup signal has been sent. + */ +void linSoftwareReset( linBASE_t * lin ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + lin->GCR1 &= ~( uint32 ) ( 0x00000080U ); + lin->GCR1 |= 0x00000080U; + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_007 */ +/* DesignId : LIN_DesignId_007 */ +/* Requirements : CONQ_LIN_SR11 */ +/** @fn uint32 linIsTxReady(linBASE_t *lin) + * @brief Check if Tx buffer empty + * @param[in] lin - lin module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 linIsTxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return lin->FLR & LIN_TX_READY; +} + +/* SourceId : LIN_SourceId_008 */ +/* DesignId : LIN_DesignId_008 */ +/* Requirements : CONQ_LIN_SR12 */ +/** @fn void linSetLength(linBASE_t *lin, uint32 length) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] length - number of data words in bytes. Range: 1-8. + * + * Send data response length in bytes. + */ +void linSetLength( linBASE_t * lin, uint32 length ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + lin->FORMAT = ( ( lin->FORMAT & 0xFFF8FFFFU ) | ( ( length - 1U ) << 16U ) ); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_009 */ +/* DesignId : LIN_DesignId_009 */ +/* Requirements : CONQ_LIN_SR13 */ +/** @fn void linSend(linBASE_t *lin, uint8 * data) + * @brief Send Data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data'. + * The number of data to transmit must be set with 'linSetLength' before. + */ +void linSend( linBASE_t * lin, uint8 * data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + uint8 * pData = data + length; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + lin->TDx[ length - i ] = *pData; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + pData--; + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_010 */ +/* DesignId : LIN_DesignId_010 */ +/* Requirements : CONQ_LIN_SR14 */ +/** @fn uint32 linIsRxReady(linBASE_t *lin) + * @brief Check if Rx buffer full + * @param[in] lin - lin module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 linIsRxReady( linBASE_t * lin ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return lin->FLR & LIN_RX_INT; +} + +/* SourceId : LIN_SourceId_011 */ +/* DesignId : LIN_DesignId_011 */ +/* Requirements : CONQ_LIN_SR15 */ +/** @fn uint32 linTxRxError(linBASE_t *lin) + * @brief Return Tx and Rx Error flags + * @param[in] lin - lin module base address + * + * @return The Tx and Rx error flags + * + * Returns the bit, physical bus, checksum, inconsistent sync field, + * no response, framing, overrun, parity and timeout error flags. + * It also clears the error flags before returning. + */ +uint32 linTxRxError( linBASE_t * lin ) +{ + uint32 status = lin->FLR + & ( LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT + | LIN_TOAWUS_INT | LIN_TO_INT ); + + lin->FLR = LIN_BE_INT | LIN_PBE_INT | LIN_CE_INT | LIN_ISFE_INT | LIN_NRE_INT + | LIN_FE_INT | LIN_OE_INT | LIN_PE_INT | LIN_TOA3WUS_INT | LIN_TOAWUS_INT + | LIN_TO_INT; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : LIN_SourceId_012 */ +/* DesignId : LIN_DesignId_012 */ +/* Requirements : CONQ_LIN_SR16 */ +/** @fn uint32 linGetIdentifier(linBASE_t *lin) + * @brief Get last received identifier + * @param[in] lin - lin module base address + * + * @return Identifier + * + * Read last received identifier. + */ +uint32 linGetIdentifier( linBASE_t * lin ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + return ( uint32 ) ( ( uint32 ) ( lin->ID & 0x00FF0000U ) >> 16U ); +} + +/* SourceId : LIN_SourceId_013 */ +/* DesignId : LIN_DesignId_013 */ +/* Requirements : CONQ_LIN_SR17 */ +/** @fn void linGetData(linBASE_t *lin, uint8 * const data) + * @brief Read received data + * @param[in] lin - lin module base address + * @param[in] data - pointer to data buffer + * + * Read a block of bytes and place it into the data buffer pointed to by 'data'. + */ +void linGetData( linBASE_t * lin, uint8 * const data ) +{ + uint32 i; + uint32 length = ( uint32 ) ( ( uint32 ) ( lin->FORMAT & 0x00070000U ) >> 16U ); + uint8 * pData = data; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + for( i = 0U; i <= length; i++ ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *pData = lin->RDx[ i ]; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + pData++; + } + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_014 */ +/* DesignId : LIN_DesignId_016 */ +/* Requirements : CONQ_LIN_SR20 */ +/** @fn void linEnableLoopback(linBASE_t *lin, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void linEnableLoopback( linBASE_t * lin, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + lin->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + lin->IODFTCTRL = ( ( uint32 ) ( 0x00000A00U ) + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_015 */ +/* DesignId : LIN_DesignId_017 */ +/* Requirements : CONQ_LIN_SR21 */ +/** @fn void linDisableLoopback(linBASE_t *lin) + * @brief Enable Loopback mode for self test + * @param[in] lin - lin module base address + * + * This function disable the Loopback mode. + */ +void linDisableLoopback( linBASE_t * lin ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + lin->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_016 */ +/* DesignId : LIN_DesignId_014 */ +/* Requirements : CONQ_LIN_SR18 */ +/** @fn linEnableNotification(linBASE_t *lin, uint32 flags) + * @brief Enable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +void linEnableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + lin->SETINT = flags; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_017 */ +/* DesignId : LIN_DesignId_015 */ +/* Requirements : CONQ_LIN_SR19 */ +/** @fn linDisableNotification(linBASE_t *lin, uint32 flags) + * @brief Disable interrupts + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect + */ +void linDisableNotification( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + lin->CLEARINT = flags; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/* SourceId : LIN_SourceId_018 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : CONQ_LIN_SR25 */ +/** @fn void lin1GetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN1 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void lin1GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN1_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN1_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN1_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN1_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN1_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN1_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN1_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN1_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN1_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN1_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN1_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN1_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN1_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN1_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN1_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = linREG1->GCR0; + config_reg->CONFIG_GCR1 = linREG1->GCR1; + config_reg->CONFIG_GCR2 = linREG1->GCR2; + config_reg->CONFIG_SETINT = linREG1->SETINT; + config_reg->CONFIG_SETINTLVL = linREG1->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG1->FORMAT; + config_reg->CONFIG_BRSR = linREG1->BRS; + config_reg->CONFIG_FUN = linREG1->PIO0; + config_reg->CONFIG_DIR = linREG1->PIO1; + config_reg->CONFIG_ODR = linREG1->PIO6; + config_reg->CONFIG_PD = linREG1->PIO7; + config_reg->CONFIG_PSL = linREG1->PIO8; + config_reg->CONFIG_COMP = linREG1->COMP; + config_reg->CONFIG_MASK = linREG1->MASK; + config_reg->CONFIG_MBRSR = linREG1->MBRSR; + } +} + +/* SourceId : LIN_SourceId_019 */ +/* DesignId : LIN_DesignId_018 */ +/* Requirements : CONQ_LIN_SR26 */ +/** @fn void lin2GetConfigValue(lin_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the LIN2 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void lin2GetConfigValue( lin_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = LIN2_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = LIN2_GCR1_CONFIGVALUE; + config_reg->CONFIG_GCR2 = LIN2_GCR2_CONFIGVALUE; + config_reg->CONFIG_SETINT = LIN2_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = LIN2_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = LIN2_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRSR = LIN2_BRSR_CONFIGVALUE; + config_reg->CONFIG_FUN = LIN2_FUN_CONFIGVALUE; + config_reg->CONFIG_DIR = LIN2_DIR_CONFIGVALUE; + config_reg->CONFIG_ODR = LIN2_ODR_CONFIGVALUE; + config_reg->CONFIG_PD = LIN2_PD_CONFIGVALUE; + config_reg->CONFIG_PSL = LIN2_PSL_CONFIGVALUE; + config_reg->CONFIG_COMP = LIN2_COMP_CONFIGVALUE; + config_reg->CONFIG_MASK = LIN2_MASK_CONFIGVALUE; + config_reg->CONFIG_MBRSR = LIN2_MBRSR_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = linREG2->GCR0; + config_reg->CONFIG_GCR1 = linREG2->GCR1; + config_reg->CONFIG_GCR2 = linREG2->GCR2; + config_reg->CONFIG_SETINT = linREG2->SETINT; + config_reg->CONFIG_SETINTLVL = linREG2->SETINTLVL; + config_reg->CONFIG_FORMAT = linREG2->FORMAT; + config_reg->CONFIG_BRSR = linREG2->BRS; + config_reg->CONFIG_FUN = linREG2->PIO0; + config_reg->CONFIG_DIR = linREG2->PIO1; + config_reg->CONFIG_ODR = linREG2->PIO6; + config_reg->CONFIG_PD = linREG2->PIO7; + config_reg->CONFIG_PSL = linREG2->PIO8; + config_reg->CONFIG_COMP = linREG2->COMP; + config_reg->CONFIG_MASK = linREG2->MASK; + config_reg->CONFIG_MBRSR = linREG2->MBRSR; + } +} + +/* SourceId : LIN_SourceId_024 */ +/* DesignId : */ +/* Requirements : */ +/** @fn uint32 linGetStatusFlag(linBASE_t *lin) + * @brief Get LIN status register value + * @param[in] lin - lin module base address + * + * @return Status Flag register content + * + * Read current Status Flag register. + */ +uint32 linGetStatusFlag( linBASE_t * lin ) +{ + return lin->FLR; +} + +/* SourceId : LIN_SourceId_025 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void linClearStatusFlag(linBASE_t *lin, uint32 flags) + * @brief Clear LIN status register + * @param[in] lin - lin module base address + * @param[in] flags - Interrupts to be disabled, can be or'ed value of: + * LIN_BE_INT - bit error, + * LIN_PBE_INT - physical bus error, + * LIN_CE_INT - checksum error, + * LIN_ISFE_INT - inconsistent sync field error, + * LIN_NRE_INT - no response error, + * LIN_FE_INT - framing error, + * LIN_OE_INT - overrun error, + * LIN_PE_INT - parity error, + * LIN_ID_INT - received matching identifier, + * LIN_RX_INT - receive buffer ready, + * LIN_TOA3WUS_INT - time out after 3 wakeup signals, + * LIN_TOAWUS_INT - time out after wakeup signal, + * LIN_TO_INT - time out signal, + * LIN_WAKEUP_INT - wakeup, + * LIN_BREAK_INT - break detect, + * LIN_BUSY_FLAG - Bus Busy Flag, + * LIN_TXEMPTY_INT - Transmit Empty Flag + * + * Clear Status Flags passed as parameter. + */ +void linClearStatusFlag( linBASE_t * lin, uint32 flags ) +{ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ + lin->FLR = flags; + /* USER CODE BEGIN (45) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c new file mode 100644 index 00000000000..958a14a5cad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mdio.c @@ -0,0 +1,251 @@ +/** + * \file mdio.c + * + * \brief MDIO APIs. + * + * This file contains the device abstraction layer APIs for MDIO. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "hw_reg_access.h" +#include "mdio.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * INTERNAL MACRO DEFINITIONS + *******************************************************************************/ +#define PHY_REG_MASK ( 0x1FU ) +#define PHY_ADDR_MASK ( 0x1FU ) +#define PHY_DATA_MASK ( 0xFFFFU ) +#define PHY_REG_SHIFT ( 21U ) +#define PHY_ADDR_SHIFT ( 16U ) + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ + +/** + * \brief Reads a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param dataPtr Pointer where the read value shall be written. + * + * \return status of the read \n + * TRUE - read is successful.\n + * FALSE - read is not acknowledged properly. + * + **/ +/* SourceId : ETH_SourceId_059 */ +/* DesignId : ETH_DesignId_059*/ +/* Requirements : CONQ_EMAC_SR62 */ +boolean MDIOPhyRegRead( uint32 baseAddr, + uint32 phyAddr, + uint32 regNum, + volatile uint16 * dataPtr ) +{ + boolean retVal = FALSE; + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( ( ( uint32 ) MDIO_USERACCESS0_READ ) + | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) ); + + /* wait for command completion */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + /* Store the data if the read is acknowledged */ + if( ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) & MDIO_USERACCESS0_ACK ) + == MDIO_USERACCESS0_ACK ) + { + /*SAFETYMCUSW 439 S MR:11.3 "Output is a 16 bit Value to be stored - + * Advisory as per MISRA" */ + *dataPtr = ( uint16 ) ( ( HWREG( baseAddr + MDIO_USERACCESS0 ) ) + & PHY_DATA_MASK ); + retVal = TRUE; + } + + return retVal; +} + +/** + * \brief Writes a PHY register using MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Address. + * \param regNum Register Number to be read. + * \param RegVal Value to be written. + * + * \return None + * + **/ +/* SourceId : ETH_SourceId_058 */ +/* DesignId : ETH_DesignId_058*/ +/* Requirements : CONQ_EMAC_SR63 */ +void MDIOPhyRegWrite( uint32 baseAddr, uint32 phyAddr, uint32 regNum, uint16 RegVal ) +{ + /* Wait till transaction completion if any */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ + + HWREG( baseAddr + + MDIO_USERACCESS0 ) = ( MDIO_USERACCESS0_WRITE | MDIO_USERACCESS0_GO + | ( ( regNum & PHY_REG_MASK ) << PHY_REG_SHIFT ) + | ( ( phyAddr & PHY_ADDR_MASK ) << PHY_ADDR_SHIFT ) + | RegVal ); + + /* wait for command completion*/ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( HWREG( baseAddr + MDIO_USERACCESS0 ) & MDIO_USERACCESS0_GO ) + == MDIO_USERACCESS0_GO ) + { + } /* Wait */ +} +/** + * \brief Reads the alive status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * is alive. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO alive register state + * + **/ +/* SourceId : ETH_SourceId_062 */ +/* DesignId : ETH_DesignId_062*/ +/* Requirements : CONQ_EMAC_SR64 */ +uint32 MDIOPhyAliveStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_ALIVE ) ); +} + +/** + * \brief Reads the link status of all PHY connected to the MDIO. + * The bit corresponding to the PHY address will be set if the PHY + * link is active. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return MDIO link register state + * + **/ +/* SourceId : ETH_SourceId_061 */ +/* DesignId : ETH_DesignId_061*/ +/* Requirements : CONQ_EMAC_SR67 */ +uint32 MDIOPhyLinkStatusGet( uint32 baseAddr ) +{ + return ( HWREG( baseAddr + MDIO_LINK ) ); +} + +/** + * \brief Initializes the MDIO peripheral. This enables the MDIO state + * machine, uses standard pre-amble and set the clock divider value. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * \param mdioInputFreq The clock input to the MDIO module + * \param mdioOutputFreq The clock output required on the MDIO bus + * \return None + * + **/ +/* SourceId : ETH_SourceId_060 */ +/* DesignId : ETH_DesignId_060*/ +/* Requirements : CONQ_EMAC_SR59 */ +void MDIOInit( uint32 baseAddr, uint32 mdioInputFreq, uint32 mdioOutputFreq ) +{ + uint32 clkDiv = ( mdioInputFreq / mdioOutputFreq ) - 1U; + HWREG( baseAddr + MDIO_CONTROL ) = ( ( clkDiv & MDIO_CONTROL_CLKDIV ) + | MDIO_CONTROL_ENABLE | MDIO_CONTROL_PREAMBLE + | MDIO_CONTROL_FAULTENB ); +} + +/** + * \brief Function to enable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_056 */ +/* DesignId : ETH_DesignId_056*/ +/* Requirements : CONQ_EMAC_SR60 */ +void MDIOEnable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + | MDIO_CONTROL_ENABLE; +} + +/** + * \brief Function to disable MDIO. + * + * \param baseAddr Base Address of the MDIO Module Registers. + * + * \return none + * + **/ +/* SourceId : ETH_SourceId_057 */ +/* DesignId : ETH_DesignId_057*/ +/* Requirements : CONQ_EMAC_SR61 */ +void MDIODisable( uint32 baseAddr ) +{ + HWREG( baseAddr + MDIO_CONTROL ) = HWREG( baseAddr + MDIO_CONTROL ) + & ( ~MDIO_CONTROL_ENABLE ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/***************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c new file mode 100644 index 00000000000..cca2730f813 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/mibspi.c @@ -0,0 +1,3408 @@ +/** @file mibspi.c + * @brief MIBSPI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "mibspi.h" +#include "sys_vim.h" +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* SourceId : MIBSPI_SourceId_001 */ +/* DesignId : MIBSPI_DesignId_001 */ +/* Requirements : CONQ_MIBSPI_SR9 */ +/** @fn void mibspiInit(void) + * @brief Initializes the MIBSPI Driver + * + * This function initializes the MIBSPI module. + */ +void mibspiInit( void ) +{ + uint32 i; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b MIBSPI1 */ + + /** bring MIBSPI out of reset */ + mibspiREG1->GCR0 = 0U; + mibspiREG1->GCR0 = 1U; + + /** enable MIBSPI1 multibuffered mode and enable buffer RAM */ + mibspiREG1->MIBSPIE = ( mibspiREG1->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI1 master mode and clock configuration */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI1 enable pin configuration */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG1->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG1->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG1->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG1->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG1->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG1->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG1->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG1->PAR_ECC_CTRL = ( mibspiREG1->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG1->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG1->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG1->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG1->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG1->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG1->LTGPEND = ( mibspiREG1->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( uint32 ) ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM1->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG1->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG1->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG1->INT0 = ( mibspiREG1->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI1 @b Port */ + + /** - MIBSPI1 Port output values */ + mibspiREG1->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port direction */ + mibspiREG1->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port open drain enable */ + mibspiREG1->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown selection */ + mibspiREG1->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - MIBSPI1 Port pullup / pulldown enable*/ + mibspiREG1->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ); /* SOMI[1] */ + + /* MIBSPI1 set all pins to functional */ + mibspiREG1->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ); /* SOMI[1] */ + + /** - Finally start MIBSPI1 */ + mibspiREG1->GCR1 = ( mibspiREG1->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI2 */ + + /** bring MIBSPI out of reset */ + mibspiREG2->GCR0 = 0U; + mibspiREG2->GCR0 = 1U; + + /** enable MIBSPI2 multibuffered mode and enable buffer RAM */ + mibspiREG2->MIBSPIE = ( mibspiREG2->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI2 master mode and clock configuration */ + mibspiREG2->GCR1 = ( mibspiREG2->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI2 enable pin configuration */ + mibspiREG2->INT0 = ( mibspiREG2->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG2->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG2->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG2->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG2->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG2->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG2->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG2->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG2->PAR_ECC_CTRL = ( mibspiREG2->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG2->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG2->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG2->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG2->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG2->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG2->LTGPEND = ( mibspiREG2->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM2->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG2->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG2->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG2->INT0 = ( mibspiREG2->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI2 @b Port */ + + /** - MIBSPI2 Port output values */ + mibspiREG2->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port direction */ + mibspiREG2->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port open drain enable */ + mibspiREG2->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port pullup / pulldown selection */ + mibspiREG2->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI2 Port pullup / pulldown enable*/ + mibspiREG2->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI2 set all pins to functional */ + mibspiREG2->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI2 */ + mibspiREG2->GCR1 = ( mibspiREG2->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI3 */ + + /** bring MIBSPI out of reset */ + mibspiREG3->GCR0 = 0U; + mibspiREG3->GCR0 = 1U; + + /** enable MIBSPI3 multibuffered mode and enable buffer RAM */ + mibspiREG3->MIBSPIE = ( mibspiREG3->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI3 master mode and clock configuration */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI3 enable pin configuration */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG3->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG3->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG3->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG3->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG3->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG3->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG3->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG3->PAR_ECC_CTRL = ( mibspiREG3->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG3->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG3->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG3->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG3->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG3->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG3->LTGPEND = ( mibspiREG3->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM3->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG3->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG3->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG3->INT0 = ( mibspiREG3->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI3 @b Port */ + + /** - MIBSPI3 Port output values */ + mibspiREG3->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port direction */ + mibspiREG3->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port open drain enable */ + mibspiREG3->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown selection */ + mibspiREG3->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI3 Port pullup / pulldown enable*/ + mibspiREG3->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI3 set all pins to functional */ + mibspiREG3->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI3 */ + mibspiREG3->GCR1 = ( mibspiREG3->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI4 */ + + /** bring MIBSPI out of reset */ + mibspiREG4->GCR0 = 0U; + mibspiREG4->GCR0 = 1U; + + /** enable MIBSPI4 multibuffered mode and enable buffer RAM */ + mibspiREG4->MIBSPIE = ( mibspiREG4->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI4 master mode and clock configuration */ + mibspiREG4->GCR1 = ( mibspiREG4->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI4 enable pin configuration */ + mibspiREG4->INT0 = ( mibspiREG4->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG4->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG4->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG4->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG4->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG4->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG4->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG4->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG4->PAR_ECC_CTRL = ( mibspiREG4->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG4->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG4->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG4->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG4->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG4->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG4->LTGPEND = ( mibspiREG4->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM4->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG4->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG4->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG4->INT0 = ( mibspiREG4->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI4 @b Port */ + + /** - MIBSPI4 Port output values */ + mibspiREG4->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port direction */ + mibspiREG4->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port open drain enable */ + mibspiREG4->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port pullup / pulldown selection */ + mibspiREG4->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - MIBSPI4 Port pullup / pulldown enable*/ + mibspiREG4->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* SOMI */ + + /* MIBSPI4 set all pins to functional */ + mibspiREG4->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* SCS[4] */ + | ( uint32 ) ( ( uint32 ) 0U << 5U ) /* SCS[5] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ); /* SOMI */ + + /** - Finally start MIBSPI4 */ + mibspiREG4->GCR1 = ( mibspiREG4->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /** @b initialize @b MIBSPI5 */ + + /** bring MIBSPI out of reset */ + mibspiREG5->GCR0 = 0U; + mibspiREG5->GCR0 = 1U; + + /** enable MIBSPI5 multibuffered mode and enable buffer RAM */ + mibspiREG5->MIBSPIE = ( mibspiREG5->MIBSPIE & 0xFFFFFFFEU ) | 1U; + + /** MIBSPI5 master mode and clock configuration */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFFFFFFFCU ) + | ( ( uint32 ) ( ( uint32 ) 1U << 1U ) /* CLOKMOD */ + | 1U ); /* MASTER */ + + /** MIBSPI5 enable pin configuration */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFEFFFFFFU ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ); /* ENABLE + HIGHZ + */ + + /** - Delays */ + mibspiREG5->DELAY = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* C2TDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* T2CDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* T2EDELAY */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* C2EDELAY */ + + /** - Data Format 0 */ + mibspiREG5->FMT0 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 1 */ + mibspiREG5->FMT1 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 2 */ + mibspiREG5->FMT2 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Data Format 3 */ + mibspiREG5->FMT3 = ( uint32 ) ( ( uint32 ) 0U << 24U ) /* wdelay */ + | ( uint32 ) ( ( uint32 ) 0U << 23U ) /* parity Polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 22U ) /* parity enable */ + | ( uint32 ) ( ( uint32 ) 0U << 21U ) /* wait on enable */ + | ( uint32 ) ( ( uint32 ) 0U << 20U ) /* shift direction */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* clock polarity */ + | ( uint32 ) ( ( uint32 ) 0U << 16U ) /* clock phase */ + | ( uint32 ) ( ( uint32 ) 74U << 8U ) /* baudrate prescale */ + | ( uint32 ) ( ( uint32 ) 16U << 0U ); /* data word length */ + + /** - Default Chip Select */ + mibspiREG5->DEF = ( uint32 ) ( 0xFFU ); + + /** - wait for buffer initialization complete before accessing MibSPI registers */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( mibspiREG5->FLG & 0x01000000U ) != 0U ) + { + } /* Wait */ + + /** enable MIBSPI RAM Parity */ + mibspiREG5->PAR_ECC_CTRL = ( mibspiREG5->PAR_ECC_CTRL & 0xFFFFFFF0U ) + | ( 0x00000005U ); + + /** - initialize transfer groups */ + mibspiREG5->TGCTRL[ 0U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 1U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) 8U << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 2U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U ) << 8U ); /* start + buffer */ + + mibspiREG5->TGCTRL[ 3U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 4U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 5U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer */ + + mibspiREG5->TGCTRL[ 6U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start buffer + */ + + mibspiREG5->TGCTRL[ 7U ] = ( uint32 ) ( ( uint32 ) 1U << 30U ) /* oneshot */ + | ( uint32 ) ( ( uint32 ) 0U << 29U ) /* pcurrent reset */ + | ( uint32 ) ( ( uint32 ) TRG_ALWAYS << 20U ) /* trigger + event */ + | ( uint32 ) ( ( uint32 ) TRG_DISABLED << 16U ) /* trigger + source */ + | ( uint32 ) ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) + << 8U ); /* start + buffer + */ + + mibspiREG5->TGCTRL[ 8U ] = ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) << 8U; + + mibspiREG5->LTGPEND = ( mibspiREG5->LTGPEND & 0xFFFF00FFU ) + | ( uint32 ) ( ( ( uint32 ) ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + + 0U ) + - 1U ) + << 8U ); + + /** - initialize buffer ram */ + { + i = 0U; + +#if( 8U > 0U ) + { + #if( 8U > 1U ) + + while( i < ( 8U - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_0 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_1 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_2 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_3 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_4 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_5 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_6 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } +#endif + +#if( 0U > 0U ) + { + #if( 0U > 1U ) + + while( i < ( ( 8U + 0U + 0U + 0U + 0U + 0U + 0U + 0U ) - 1U ) ) + { + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 11U ) /* lock transmission */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + + i++; + } + #endif + mibspiRAM5->tx[ i ] + .control = ( uint16 ) ( ( uint16 ) 4U << 13U ) /* buffer mode */ + | ( uint16 ) ( ( uint16 ) 0U << 12U ) /* chip select hold */ + | ( uint16 ) ( ( uint16 ) 0U << 10U ) /* enable WDELAY */ + | ( uint16 ) ( ( uint16 ) 0U << 8U ) /* data format */ + | ( ( uint16 ) ( ~( ( uint16 ) 0xFFU ^ ( uint16 ) CS_7 ) ) + & ( uint16 ) 0x00FFU ); /* chip select */ + i++; + } +#endif + } + + /** - set interrupt levels */ + mibspiREG5->LVL = ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** - clear any pending interrupts */ + mibspiREG5->FLG |= 0xFFFFU; + + /** - enable interrupts */ + mibspiREG5->INT0 = ( mibspiREG5->INT0 & 0xFFFF0000U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* TXINT + */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* RXINT */ + | ( uint32 ) ( ( uint32 ) 0U << 6U ) /* OVRNINT */ + | ( uint32 ) ( ( uint32 ) 0U << 4U ) /* BITERR */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* DESYNC */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* PARERR */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* TIMEOUT */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* DLENERR */ + + /** @b initialize @b MIBSPI5 @b Port */ + + /** - MIBSPI5 Port output values */ + mibspiREG5->PC3 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port direction */ + mibspiREG5->PC1 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port open drain enable */ + mibspiREG5->PC6 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown selection */ + mibspiREG5->PC8 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - MIBSPI5 Port pullup / pulldown enable*/ + mibspiREG5->PC7 = ( uint32 ) ( ( uint32 ) 0U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 27U ); /* SOMI[3] */ + + /* MIBSPI5 set all pins to functional */ + mibspiREG5->PC0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) /* SCS[0] */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* SCS[1] */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* SCS[2] */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* SCS[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* ENA */ + | ( uint32 ) ( ( uint32 ) 1U << 9U ) /* CLK */ + | ( uint32 ) ( ( uint32 ) 1U << 10U ) /* SIMO[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 11U ) /* SOMI[0] */ + | ( uint32 ) ( ( uint32 ) 1U << 17U ) /* SIMO[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 18U ) /* SIMO[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 19U ) /* SIMO[3] */ + | ( uint32 ) ( ( uint32 ) 1U << 25U ) /* SOMI[1] */ + | ( uint32 ) ( ( uint32 ) 1U << 26U ) /* SOMI[2] */ + | ( uint32 ) ( ( uint32 ) 1U << 27U ); /* SOMI[3] */ + + /** - Finally start MIBSPI5 */ + mibspiREG5->GCR1 = ( mibspiREG5->GCR1 & 0xFEFFFFFFU ) | 0x01000000U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_002 */ +/* DesignId : */ +/* Requirements : */ +/** @fn boolean mibspiIsBuffInitialized(mibspiBASE_t *mibspi) + * @brief Checks if Mibspi buffer is initialized. + * @param[in] mibspi - Mibspi module base address + * + * This function brings Mibspi module out of reset. + */ +boolean mibspiIsBuffInitialized( mibspiBASE_t * mibspi ) +{ + volatile boolean status; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + if( ( mibspi->FLG & 0x01000000U ) != 0x01000000U ) + { + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + return ( status ); +} + +/* SourceId : MIBSPI_SourceId_003 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void mibspiOutofReset(mibspiBASE_t *mibspi) + * @brief Bring Mibspi Module Out of Reset + * @param[in] mibspi - Mibspi module base address + * + * This function brings Mibspi module out of reset. + */ +void mibspiOutofReset( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + mibspi->GCR0 |= 0x1U; + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_004 */ +/* DesignId : */ +/* Requirements : */ +/** @fn void mibspiReset(mibspiBASE_t *mibspi) + * @brief Take Mibspi Module to Reset + * @param[in] mibspi - Mibspi module base address + * + * This function takes Mibspi module to reset. + */ +void mibspiReset( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + mibspi->GCR0 = 0x0U; + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_005 */ +/* DesignId : MIBSPI_DesignId_002 */ +/* Requirements : CONQ_MIBSPI_SR10 */ +/** @fn void mibspiSetFunctional(mibspiBASE_t *mibspi, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] mibspi - mibspi module base address + * @param[in] port - Value to write to PC0 register + * + * Change the value of the PC0 register at runtime, this allows to + * dynamically change the functionality of the MIBSPI pins between functional + * and GIO mode. + */ +void mibspiSetFunctional( mibspiBASE_t * mibspi, uint32 port ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + mibspi->PC0 = port; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_006 */ +/* DesignId : MIBSPI_DesignId_003 */ +/* Requirements : CONQ_MIBSPI_SR11 */ +/** @fn void mibspiSetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Set Buffer Data + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] data - new data for transfer group + * + * This function updates the data for the specified transfer group, + * the length of the data must match the length of the transfer group. + */ +void mibspiSetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + mibspiRAM_t * ram = mibspi == mibspiREG1 + ? mibspiRAM1 + : ( mibspi == mibspiREG2 + ? mibspiRAM2 + : ( mibspi == mibspiREG3 + ? mibspiRAM3 + : ( mibspi == mibspiREG4 ? mibspiRAM4 + : mibspiRAM5 ) ) ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + ram->tx[ start ].data = *data; + data++; + start++; + } + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_007 */ +/* DesignId : MIBSPI_DesignId_004 */ +/* Requirements : CONQ_MIBSPI_SR12 */ +/** @fn void mibspiGetData(mibspiBASE_t *mibspi, uint32 group, uint16 * data) + * @brief Retrieves Buffer Data from receive buffer + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[out] data - pointer to data array + * + * @return error flags from data buffer, if there was a receive error on + * one of the buffers this will be reflected in the return value. + * + * This function transfers the data from the specified transfer group receive + * buffers to the data array, the length of the data must match the length + * of the transfer group. + */ +uint32 mibspiGetData( mibspiBASE_t * mibspi, uint32 group, uint16 * data ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + mibspiRAM_t * ram = mibspi == mibspiREG1 + ? mibspiRAM1 + : ( mibspi == mibspiREG2 + ? mibspiRAM2 + : ( mibspi == mibspiREG3 + ? mibspiRAM3 + : ( mibspi == mibspiREG4 ? mibspiRAM4 + : mibspiRAM5 ) ) ); + uint32 start = ( mibspi->TGCTRL[ group ] >> 8U ) & 0xFFU; + uint32 end = ( group == 7U ) ? ( ( ( mibspi->LTGPEND & 0x00007F00U ) >> 8U ) + 1U ) + : ( ( mibspi->TGCTRL[ group + 1U ] >> 8U ) & 0xFFU ); + uint16 mibspiFlags = 0U; + uint32 ret; + if( end == 0U ) + { + end = 128U; + } + + while( start < end ) + { + mibspiFlags |= ram->rx[ start ].flags; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + *data = ram->rx[ start ].data; + data++; + start++; + } + + ret = ( ( uint32 ) mibspiFlags >> 8U ) & 0x5FU; + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + return ret; +} + +/* SourceId : MIBSPI_SourceId_008 */ +/* DesignId : MIBSPI_DesignId_005 */ +/* Requirements : CONQ_MIBSPI_SR13 */ +/** @fn void mibspiTransfer(mibspiBASE_t *mibspi, uint32 group) + * @brief Transmit Transfer Group + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * Initiates a transfer for the specified transfer group. + */ +void mibspiTransfer( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + mibspi->TGCTRL[ group ] |= 0x80000000U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_009 */ +/* DesignId : MIBSPI_DesignId_006 */ +/* Requirements : CONQ_MIBSPI_SR14 */ +/** @fn boolean mibspiIsTransferComplete(mibspiBASE_t *mibspi, uint32 group) + * @brief Check for Transfer Group Ready + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * @return TRUE is transfer complete, otherwise FALSE. + * + * Checks to see if the transfer for the specified transfer group + * has finished. + */ +boolean mibspiIsTransferComplete( mibspiBASE_t * mibspi, uint32 group ) +{ + boolean status; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( ( ( ( ( mibspi->TGINTFLG & 0xFFFF0000U ) >> 16U ) >> group ) & 1U ) == 1U ) + { + mibspi->TGINTFLG = ( mibspi->TGINTFLG & 0x0000FFFFU ) + | ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + status = TRUE; + } + else + { + status = FALSE; + } + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + return ( status ); +} + +/* SourceId : MIBSPI_SourceId_010 */ +/* DesignId : MIBSPI_DesignId_009 */ +/* Requirements : CONQ_MIBSPI_SR17 */ +/** @fn void mibspiEnableLoopback(mibspiBASE_t *mibspi, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void mibspiEnableLoopback( mibspiBASE_t * mibspi, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + mibspi->IOLPKTSTCR = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + mibspi->IOLPKTSTCR = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_011 */ +/* DesignId : MIBSPI_DesignId_010 */ +/* Requirements : CONQ_MIBSPI_SR18 */ +/** @fn void mibspiDisableLoopback(mibspiBASE_t *mibspi) + * @brief Enable Loopback mode for self test + * @param[in] mibspi - Mibspi module base address + * + * This function disable the Loopback mode. + */ +void mibspiDisableLoopback( mibspiBASE_t * mibspi ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + mibspi->IOLPKTSTCR = 0x00000500U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_012 */ +/* DesignId : MIBSPI_DesignId_011 */ +/* Requirements : CONQ_MIBSPI_SR21 */ +/** @fn void mibspiPmodeSet(mibspiBASE_t *mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT) + * @brief Set the Pmode for the selected Data Format register + * @param[in] mibspi - Mibspi module base address + * @param[in] Pmode - Mibspi Parellel mode + * PMODE_NORMAL + * PMODE_2_DATALINE + * PMODE_4_DATALINE + * PMODE_8_DATALINE + * @param[in] DFMT - Mibspi Data Format register + * DATA_FORMAT0 + * DATA_FORMAT1 + * DATA_FORMAT2 + * DATA_FORMAT3 + * + * This function sets the Pmode for the selected Data Format register. + */ +void mibspiPmodeSet( mibspiBASE_t * mibspi, mibspiPmode_t Pmode, mibspiDFMT_t DFMT ) +{ + uint32 pmctrl_reg; + /* Set the Pmode for the selected Data Format register */ + pmctrl_reg = ( mibspi->PMCTRL + & ( ~( uint32 ) ( ( uint32 ) 0xFFU << ( 8U * DFMT ) ) ) ); + mibspi->PMCTRL = ( pmctrl_reg + | ( uint32 ) ( ( uint32 ) Pmode << ( ( 8U * DFMT ) ) ) ); +} + +/* SourceId : MIBSPI_SourceId_013 */ +/* DesignId : MIBSPI_DesignId_007 */ +/* Requirements : CONQ_MIBSPI_SR15 */ +/** @fn void mibspiEnableGroupNotification(mibspiBASE_t *mibspi, uint32 group, uint32 + * level) + * @brief Enable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * @param[in] level - Interrupt level + * + * This function enables the transfer group finished interrupt. + */ +void mibspiEnableGroupNotification( mibspiBASE_t * mibspi, uint32 group, uint32 level ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + if( level != 0U ) + { + mibspi->TGITLVST = ( mibspi->TGITLVST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + else + { + mibspi->TGITLVCR = ( mibspi->TGITLVCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + } + mibspi->TGITENST = ( mibspi->TGITENST & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_014 */ +/* DesignId : MIBSPI_DesignId_008 */ +/* Requirements : CONQ_MIBSPI_SR16 */ +/** @fn void mibspiDisableGroupNotification(mibspiBASE_t *mibspi, uint32 group) + * @brief Disable Transfer Group interrupt + * @param[in] mibspi - Spi module base address + * @param[in] group - Transfer group (0..7) + * + * This function disables the transfer group finished interrupt. + */ +void mibspiDisableGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + mibspi->TGITENCR = ( mibspi->TGITENCR & 0x0000FFFFU ) + | ( uint32 ) ( ( uint32 ) ( ( uint32 ) 1U << group ) << 16U ); + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/* SourceId : MIBSPI_SourceId_015 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR22 */ +/** @fn void mibspi1GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi1GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI1_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI1_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI1_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI1_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI1_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI1_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI1_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI1_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI1_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI1_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI1_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI1_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI1_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI1_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI1_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI1_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI1_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI1_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI1_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI1_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI1_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI1_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI1_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI1_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG1->GCR1; + config_reg->CONFIG_INT0 = mibspiREG1->INT0; + config_reg->CONFIG_LVL = mibspiREG1->LVL; + config_reg->CONFIG_PCFUN = mibspiREG1->PC0; + config_reg->CONFIG_PCDIR = mibspiREG1->PC1; + config_reg->CONFIG_PCPDR = mibspiREG1->PC6; + config_reg->CONFIG_PCDIS = mibspiREG1->PC7; + config_reg->CONFIG_PCPSL = mibspiREG1->PC8; + config_reg->CONFIG_DELAY = mibspiREG1->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG1->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG1->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG1->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG1->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG1->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG1->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG1->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG1->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG1->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG1->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG1->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG1->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG1->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG1->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG1->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_016 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR23 */ +/** @fn void mibspi2GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi2GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI2_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI2_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI2_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI2_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI2_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI2_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI2_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI2_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI2_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI2_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI2_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI2_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI2_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI2_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI2_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI2_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI2_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI2_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI2_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI2_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI2_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI2_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI2_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI2_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG2->GCR1; + config_reg->CONFIG_INT0 = mibspiREG2->INT0; + config_reg->CONFIG_LVL = mibspiREG2->LVL; + config_reg->CONFIG_PCFUN = mibspiREG2->PC0; + config_reg->CONFIG_PCDIR = mibspiREG2->PC1; + config_reg->CONFIG_PCPDR = mibspiREG2->PC6; + config_reg->CONFIG_PCDIS = mibspiREG2->PC7; + config_reg->CONFIG_PCPSL = mibspiREG2->PC8; + config_reg->CONFIG_DELAY = mibspiREG2->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG2->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG2->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG2->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG2->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG2->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG2->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG2->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG2->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG2->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG2->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG2->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG2->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG2->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG2->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG2->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_017 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR24 */ +/** @fn void mibspi3GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi3GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI3_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI3_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI3_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI3_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI3_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI3_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI3_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI3_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI3_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI3_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI3_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI3_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI3_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI3_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI3_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI3_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI3_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI3_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI3_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI3_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI3_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI3_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI3_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG3->GCR1; + config_reg->CONFIG_INT0 = mibspiREG3->INT0; + config_reg->CONFIG_LVL = mibspiREG3->LVL; + config_reg->CONFIG_PCFUN = mibspiREG3->PC0; + config_reg->CONFIG_PCDIR = mibspiREG3->PC1; + config_reg->CONFIG_PCPDR = mibspiREG3->PC6; + config_reg->CONFIG_PCDIS = mibspiREG3->PC7; + config_reg->CONFIG_PCPSL = mibspiREG3->PC8; + config_reg->CONFIG_DELAY = mibspiREG3->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG3->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG3->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG3->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG3->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG3->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG3->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG3->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG3->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG3->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG3->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG3->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG3->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG3->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG3->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG3->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_018 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR25 */ +/** @fn void mibspi4GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi4GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI4_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI4_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI4_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI4_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI4_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI4_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI4_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI4_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI4_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI4_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI4_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI4_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI4_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI4_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI4_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI4_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI4_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI4_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI4_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI4_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI4_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI4_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI4_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG4->GCR1; + config_reg->CONFIG_INT0 = mibspiREG4->INT0; + config_reg->CONFIG_LVL = mibspiREG4->LVL; + config_reg->CONFIG_PCFUN = mibspiREG4->PC0; + config_reg->CONFIG_PCDIR = mibspiREG4->PC1; + config_reg->CONFIG_PCPDR = mibspiREG4->PC6; + config_reg->CONFIG_PCDIS = mibspiREG4->PC7; + config_reg->CONFIG_PCPSL = mibspiREG4->PC8; + config_reg->CONFIG_DELAY = mibspiREG4->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG4->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG4->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG4->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG4->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG4->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG4->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG4->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG4->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG4->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG4->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG4->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG4->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG4->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG4->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG4->PAR_ECC_CTRL; + } +} + +/* SourceId : MIBSPI_SourceId_019 */ +/* DesignId : MIBSPI_DesignId_012 */ +/* Requirements : CONQ_MIBSPI_SR26 */ +/** @fn void mibspi5GetConfigValue(mibspi_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ +void mibspi5GetConfigValue( mibspi_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR1 = MIBSPI5_GCR1_CONFIGVALUE; + config_reg->CONFIG_INT0 = MIBSPI5_INT0_CONFIGVALUE; + config_reg->CONFIG_LVL = MIBSPI5_LVL_CONFIGVALUE; + config_reg->CONFIG_PCFUN = MIBSPI5_PCFUN_CONFIGVALUE; + config_reg->CONFIG_PCDIR = MIBSPI5_PCDIR_CONFIGVALUE; + config_reg->CONFIG_PCPDR = MIBSPI5_PCPDR_CONFIGVALUE; + config_reg->CONFIG_PCDIS = MIBSPI5_PCDIS_CONFIGVALUE; + config_reg->CONFIG_PCPSL = MIBSPI5_PCPSL_CONFIGVALUE; + config_reg->CONFIG_DELAY = MIBSPI5_DELAY_CONFIGVALUE; + config_reg->CONFIG_FMT0 = MIBSPI5_FMT0_CONFIGVALUE; + config_reg->CONFIG_FMT1 = MIBSPI5_FMT1_CONFIGVALUE; + config_reg->CONFIG_FMT2 = MIBSPI5_FMT2_CONFIGVALUE; + config_reg->CONFIG_FMT3 = MIBSPI5_FMT3_CONFIGVALUE; + config_reg->CONFIG_MIBSPIE = MIBSPI5_MIBSPIE_CONFIGVALUE; + config_reg->CONFIG_LTGPEND = MIBSPI5_LTGPEND_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 0U ] = MIBSPI5_TGCTRL0_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 1U ] = MIBSPI5_TGCTRL1_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 2U ] = MIBSPI5_TGCTRL2_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 3U ] = MIBSPI5_TGCTRL3_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 4U ] = MIBSPI5_TGCTRL4_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 5U ] = MIBSPI5_TGCTRL5_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 6U ] = MIBSPI5_TGCTRL6_CONFIGVALUE; + config_reg->CONFIG_TGCTRL[ 7U ] = MIBSPI5_TGCTRL7_CONFIGVALUE; + config_reg->CONFIG_PAR_ECC_CTRL = MIBSPI5_PAR_ECC_CTRL_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR1 = mibspiREG5->GCR1; + config_reg->CONFIG_INT0 = mibspiREG5->INT0; + config_reg->CONFIG_LVL = mibspiREG5->LVL; + config_reg->CONFIG_PCFUN = mibspiREG5->PC0; + config_reg->CONFIG_PCDIR = mibspiREG5->PC1; + config_reg->CONFIG_PCPDR = mibspiREG5->PC6; + config_reg->CONFIG_PCDIS = mibspiREG5->PC7; + config_reg->CONFIG_PCPSL = mibspiREG5->PC8; + config_reg->CONFIG_DELAY = mibspiREG5->DELAY; + config_reg->CONFIG_FMT0 = mibspiREG5->FMT0; + config_reg->CONFIG_FMT1 = mibspiREG5->FMT1; + config_reg->CONFIG_FMT2 = mibspiREG5->FMT2; + config_reg->CONFIG_FMT3 = mibspiREG5->FMT3; + config_reg->CONFIG_MIBSPIE = mibspiREG5->MIBSPIE; + config_reg->CONFIG_LTGPEND = mibspiREG5->LTGPEND; + config_reg->CONFIG_TGCTRL[ 0U ] = mibspiREG5->TGCTRL[ 0U ]; + config_reg->CONFIG_TGCTRL[ 1U ] = mibspiREG5->TGCTRL[ 1U ]; + config_reg->CONFIG_TGCTRL[ 2U ] = mibspiREG5->TGCTRL[ 2U ]; + config_reg->CONFIG_TGCTRL[ 3U ] = mibspiREG5->TGCTRL[ 3U ]; + config_reg->CONFIG_TGCTRL[ 4U ] = mibspiREG5->TGCTRL[ 4U ]; + config_reg->CONFIG_TGCTRL[ 5U ] = mibspiREG5->TGCTRL[ 5U ]; + config_reg->CONFIG_TGCTRL[ 6U ] = mibspiREG5->TGCTRL[ 6U ]; + config_reg->CONFIG_TGCTRL[ 7U ] = mibspiREG5->TGCTRL[ 7U ]; + config_reg->CONFIG_PAR_ECC_CTRL = mibspiREG5->PAR_ECC_CTRL; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c new file mode 100644 index 00000000000..786f8d6871a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/nmpu.c @@ -0,0 +1,403 @@ +/** @file nmpu.c + * @brief NMPU Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the NMPU driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "nmpu.h" + +/** @fn void nmpuEnable(nmpuBASE_t * nmpu) + * @brief Enable memory protection + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function enables memory protection + */ +/* SourceId : NMPU_SourceId_001 */ +/* DesignId : NMPU_DesignId_001 */ +/* Requirements : CONQ_NMPU_SR1 */ +void nmpuEnable( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL1 = 0xAU; /* Enable Memory Protection */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void nmpuDisable(nmpuBASE_t * nmpu) + * @brief Disable memory protection + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function disables memory protection + */ +/* SourceId : NMPU_SourceId_002 */ +/* DesignId : NMPU_DesignId_002 */ +/* Requirements : CONQ_NMPU_SR2 */ +void nmpuDisable( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL1 = 0x5U; /* Disable Memory Protection */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void nmpuEnableErrorGen(nmpuBASE_t * nmpu) + * @brief Enable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function enables error pulse output to ESM + */ +/* SourceId : NMPU_SourceId_003 */ +/* DesignId : NMPU_DesignId_003 */ +/* Requirements : CONQ_NMPU_SR3 */ +void nmpuEnableErrorGen( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL2 = 0xAU; /* Enable Error pulse output to ESM */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void nmpuDisableErrorGen(nmpuBASE_t * nmpu) + * @brief Disable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function disables error pulse output to ESM + */ +/* SourceId : NMPU_SourceId_004 */ +/* DesignId : NMPU_DesignId_004 */ +/* Requirements : CONQ_NMPU_SR4 */ +void nmpuDisableErrorGen( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + nmpu->MPULOCK = 0xAU; /* Allow MPU register writes */ + nmpu->MPUCTRL2 = 0x5U; /* Disable Error pulse output to ESM */ + nmpu->MPULOCK = 0x5U; /* Block MPU register writes */ + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn boolean nmpuEnableRegion(nmpuBASE_t * nmpu, uint32 region, nmpuRegionAttributes_t +config) +* @brief Enable NMPU region +* +* @param[in] nmpu NMPU module instance +* - nmpu_emacREG : EMAC-NMPU (2 regions) +* - nmpu_dmaREG : DMA-NMPU (8 regions) +* - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 +regions) +* @param[in] region region number (NMPU_REGION0..NMPU_REGION7) +* @param[in] config struct containing the following elements: + - baseaddr : 32-bit vase address (must be multiple of +region size) + - regionsize : Region size (Refer enum nmpuRegionSize) + - accesspermission : Access Permission (Refer enum +nmpuAccessPermission) +* @return Returns TRUE if the input parameters are valid. +* +* This function enables an NMPU region. This function will not enable the NMPU module. +Application must call the routine nmpuEnable to so the same. +*/ +/* SourceId : NMPU_SourceId_005 */ +/* DesignId : NMPU_DesignId_005 */ +/* Requirements : CONQ_NMPU_SR5 */ +boolean nmpuEnableRegion( nmpuBASE_t * nmpu, + nmpuReg_t region, + nmpuRegionAttributes_t config ) +{ + boolean status = TRUE; + uint32 addrMask; + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + if( ( uint32 ) region >= ( nmpu->MPUTYPE >> 8U ) ) + { + /* Invalid region */ + status = FALSE; + } + + addrMask = ( uint32 ) 2U << ( config.regionsize ); + addrMask = addrMask - 1U; + if( ( config.baseaddr & addrMask ) != 0U ) + { + /* Invalid Baseaddress - Not a multiple of region size */ + status = FALSE; + } + + if( status == TRUE ) + { + /* Set the region attributes */ + nmpu->MPULOCK = 0xAU; + nmpu->MPUREGNUM = region; + nmpu->MPUREGBASE = ( ( uint32 ) ( config.baseaddr ) ); + nmpu->MPUREGSENA = ( ( uint32 ) ( config.regionsize ) << 1U ) | 1U; + nmpu->MPUREGACR = ( ( uint32 ) ( config.accesspermission ) << 8U ); + nmpu->MPULOCK = 0x5U; + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuDisableRegion(nmpuBASE_t * nmpu, uint32 region) + * @brief Disable error pulse output to ESM + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @param[in] region region number (NMPU_REGION0..NMPU_REGION7) + * @return Returns TRUE if the input parameters are valid. + * + * This function disables an NMPU region. + */ +/* SourceId : NMPU_SourceId_006 */ +/* DesignId : NMPU_DesignId_006 */ +/* Requirements : CONQ_NMPU_SR6 */ +boolean nmpuDisableRegion( nmpuBASE_t * nmpu, nmpuReg_t region ) +{ + boolean status; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( ( uint32 ) region >= ( nmpu->MPUTYPE >> 8U ) ) + { + /* Invalid region */ + status = FALSE; + } + else + { + nmpu->MPULOCK = 0xAU; + nmpu->MPUREGNUM = region; + nmpu->MPUREGSENA = 0U; + nmpu->MPULOCK = 0x5U; + status = TRUE; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuErr_t nmpuGetErrorStatus(nmpuBASE_t * nmpu) + * @brief Get the error status + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Returns any of the following: + * - NMPU_ERROR_NONE : No error + * - NMPU_ERROR_AP_READ : Access permission Read Error + * - NMPU_ERROR_AP_WRITE : Access permission Write Error + * - NMPU_ERROR_BG_READ : Backgroung Read Error + * - NMPU_ERROR_BG_WRITE : Backgroung Write Error + * + * This function returns the status of NMPU error + */ +/* SourceId : NMPU_SourceId_007 */ +/* DesignId : NMPU_DesignId_007 */ +/* Requirements : CONQ_NMPU_SR7 */ +nmpuErr_t nmpuGetErrorStatus( nmpuBASE_t * nmpu ) +{ + nmpuErr_t status; + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + if( ( nmpu->MPUERRSTAT & 0x1U ) == 0x1U ) + { + if( ( nmpu->MPUERRSTAT & 0x02000000U ) == 0x02000000U ) + { + if( ( nmpu->MPUERRSTAT & 0x10000000U ) == 0x10000000U ) + { + status = NMPU_ERROR_AP_READ; + } + else + { + status = NMPU_ERROR_AP_WRITE; + } + } + else + { + if( ( nmpu->MPUERRSTAT & 0x10000000U ) == 0x10000000U ) + { + status = NMPU_ERROR_BG_READ; + } + else + { + status = NMPU_ERROR_BG_WRITE; + } + } + } + else + { + status = NMPU_ERROR_NONE; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return status; +} + +/** @fn nmpuReg_t nmpuGetErrorRegion(nmpuBASE_t * nmpu) + * @brief Get the region for which an access permission error was detected + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Region where access permission error was detected + * + * This function returns the region for which an access permission error was detected + */ +/* SourceId : NMPU_SourceId_008 */ +/* DesignId : NMPU_DesignId_008 */ +/* Requirements : CONQ_NMPU_SR9 */ +nmpuReg_t nmpuGetErrorRegion( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return ( nmpuReg_t ) ( ( nmpu->MPUERRSTAT & 0x70000U ) >> 16U ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn uint32 nmpuGetErrorAddress(nmpuBASE_t * nmpu) + * @brief Get the address for MPU compare fail + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * @return Address for MPU compare fail + * + * This function returns the address for MPU compare fail + */ +/* SourceId : NMPU_SourceId_009 */ +/* DesignId : NMPU_DesignId_009 */ +/* Requirements : CONQ_NMPU_SR8 */ +uint32 nmpuGetErrorAddress( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + return ( nmpu->MPUERRADDR ); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void nmpuClearErrorStatus(nmpuBASE_t * nmpu) + * @brief Clear error status + * + * @param[in] nmpu NMPU module instance + * - nmpu_emacREG : EMAC-NMPU (2 regions) + * - nmpu_dmaREG : DMA-NMPU (8 regions) + * - nmpu_ps_scr_sREG : Peripheral Interconnect Subsystem-NMPU (8 + * regions) + * + * This function clears the error status flags + */ +/* SourceId : NMPU_SourceId_010 */ +/* DesignId : NMPU_DesignId_010 */ +/* Requirements : CONQ_NMPU_SR10 */ +void nmpuClearErrorStatus( nmpuBASE_t * nmpu ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + nmpu->MPUERRSTAT = 1U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c new file mode 100644 index 00000000000..ea9e93c4b16 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/notification.c @@ -0,0 +1,330 @@ +/** @file notification.c + * @brief User Notification Definition File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file defines empty notification routines to avoid + * linker errors, Driver expects user to define the notification. + * The user needs to either remove this file and use their custom + * notification function or place their code sequence in this file + * between the provided USER CODE BEGIN and USER CODE END. + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include +#include "esm.h" +#include "can.h" +#include "gio.h" +#include "lin.h" +#include "mibspi.h" +#include "sci.h" +#include "het.h" +#include "dcc.h" +#include "i2c.h" +#include "crc.h" +#include "etpwm.h" +#include "eqep.h" +#include "ecap.h" +#include "epc.h" +#include "emac.h" +#include "sys_dma.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ +void esmGroup1Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +void esmGroup2Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (4) */ +/* USER CODE END */ +void esmGroup3Notification( esmBASE_t * esm, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + for( ;; ) + { + } /* Wait */ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (7) */ +/* USER CODE END */ + +void dmaGroupANotification( dmaInterrupt_t inttype, uint32 channel ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/* USER CODE BEGIN (11) */ +/* USER CODE END */ +void adcNotification( adcBASE_t * adc, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (15) */ +/* USER CODE END */ +void canErrorNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ +} + +void canStatusChangeNotification( canBASE_t * node, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +void canMessageNotification( canBASE_t * node, uint32 messageBox ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (19) */ +/* USER CODE END */ +void dccNotification( dccBASE_t * dcc, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (21) */ +/* USER CODE END */ +void gioNotification( gioPORT_t * port, uint32 bit ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (23) */ +/* USER CODE END */ +void i2cNotification( i2cBASE_t * i2c, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ +void linNotification( linBASE_t * lin, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (27) */ +/* USER CODE END */ +void mibspiNotification( mibspiBASE_t * mibspi, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ +void mibspiGroupNotification( mibspiBASE_t * mibspi, uint32 group ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (30) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (31) */ +/* USER CODE END */ + +void sciNotification( sciBASE_t * sci, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (33) */ +/* USER CODE END */ + +void pwmNotification( hetBASE_t * hetREG, uint32 pwm, uint32 notification ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (39) */ +/* USER CODE END */ +void edgeNotification( hetBASE_t * hetREG, uint32 edge ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (40) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (41) */ +/* USER CODE END */ +void hetNotification( hetBASE_t * het, uint32 offset ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (43) */ +/* USER CODE END */ + +void crcNotification( crcBASE_t * crc, uint32 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (44) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (45) */ +/* USER CODE END */ + +/* USER CODE BEGIN (46) */ +/* USER CODE END */ + +void etpwmNotification( etpwmBASE_t * node ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (47) */ + /* USER CODE END */ +} +void etpwmTripNotification( etpwmBASE_t * node, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (48) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (49) */ +/* USER CODE END */ + +/* USER CODE BEGIN (50) */ +/* USER CODE END */ + +void eqepNotification( eqepBASE_t * eqep, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (51) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (52) */ +/* USER CODE END */ + +/* USER CODE BEGIN (53) */ +/* USER CODE END */ + +void ecapNotification( ecapBASE_t * ecap, uint16 flags ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (54) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (55) */ +/* USER CODE END */ + +/* USER CODE BEGIN (56) */ +/* USER CODE END */ + +void epcCAMFullNotification( void ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (57) */ + /* USER CODE END */ +} +void epcFIFOFullNotification( uint32 epcFIFOStatus ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (58) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (59) */ +/* USER CODE END */ + +void emacTxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (60) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (61) */ +/* USER CODE END */ +void emacRxNotification( hdkif_t * hdkif ) +{ + /* enter user code between the USER CODE BEGIN and USER CODE END. */ + /* USER CODE BEGIN (62) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (63) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c new file mode 100644 index 00000000000..e5a51eee03b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_dp83640.c @@ -0,0 +1,433 @@ +/** + * \file phy_dp83640.c + * + * \brief APIs for configuring DP83640. + * + * This file contains the device abstraction APIs for PHY DP83640. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_dp83640.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : CONQ_EMAC_SR69 */ +uint32 Dp83640IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : CONQ_EMAC_SR67 */ +boolean Dp83640LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * DP83640_100BTX - 100BaseTX + * DP83640_100BTX_FD - Full duplex capabilty for 100BaseTX + * DP83640_10BT - 10BaseT + * DP83640_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : CONQ_EMAC_SR66 */ +boolean Dp83640AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : CONQ_EMAC_SR68 */ +boolean Dp83640PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : CONQ_EMAC_SR65 */ +void Dp83640Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint16 regVal = 0U; + uint16 * regPtr = ®Val; + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_SOFTRESET ); + + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, regPtr ); + /* : This bit is self-clearing and returns 1 until the reset process is complete. */ + while( ( regVal & PHY_SOFTRESET ) != 0U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_BCR, regPtr ); + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : CONQ_EMAC_SR72 */ +void Dp83640EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + uint16 * regPtr = ®Val; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regPtr ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : CONQ_EMAC_SR73 */ +void Dp83640DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + uint16 * regPtr = ®Val; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regPtr ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : CONQ_EMAC_SR75 */ +uint64 Dp83640GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Dp83640PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c new file mode 100644 index 00000000000..d6954591150 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/phy_tlk111.c @@ -0,0 +1,401 @@ +/** + * \file phy_Tlk111.c + * + * \brief APIs for configuring Tlk111. + * + * This file contains the device abstraction APIs for PHY Tlk111. + */ + +/* Copyright (C) 2010 Texas Instruments Incorporated - www.ti.com + * ALL RIGHTS RESERVED + */ + +#include "sys_common.h" +#include "mdio.h" +#include "phy_tlk111.h" + +/******************************************************************************* + * API FUNCTION DEFINITIONS + *******************************************************************************/ +/** + * \brief Reads the PHY ID. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return 32 bit PHY ID (ID1:ID2) + * + **/ +/* SourceId : ETH_SourceId_063 */ +/* DesignId : ETH_DesignId_063*/ +/* Requirements : ETH_SR49 */ +uint32 Tlk111IDGet( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 id = 0U; + uint16 data = 0U; + + /* read the ID1 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID1, &data ); + + /* update the ID1 value */ + id = ( uint32 ) data; + id = ( uint32 ) ( ( uint32 ) id << PHY_ID_SHIFT ); + + /* read the ID2 register */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_ID2, &data ); + + /* update the ID2 value */ + id |= data; + + /* return the ID in ID1:ID2 format */ + return id; +} + +void Tlk111SwStrap( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR1, Tlk111_SWSCR1_Val ); + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR2, Tlk111_SWSCR2_Val ); + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_SWSCR3, Tlk111_SWSCR3_Val ); + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_SWSCR1, + ( Tlk111_SWSCR1_Val | Tlk111_SWStrapDone ) ); +} + +/** + * \brief Reads the link status of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param retries The number of retries before indicating down status + * + * \return link status after reading \n + * TRUE if link is up + * FALSE if link is down \n + * + * \note This reads both the basic status register of the PHY and the + * link register of MDIO for double check + **/ +/* SourceId : ETH_SourceId_067 */ +/* DesignId : ETH_DesignId_067*/ +/* Requirements : ETH_SR47 */ +boolean Tlk111LinkStatusGet( uint32 mdioBaseAddr, + uint32 phyAddr, + volatile uint32 retries ) +{ + volatile uint16 linkStatus = 0U; + boolean retVal = TRUE; + + while( retVal == TRUE ) + { + /* First read the BSR of the PHY */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &linkStatus ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & PHY_LINK_STATUS ) != 0U ) + { + /* Check if MDIO LINK register is updated */ + linkStatus = ( uint16 ) MDIOPhyLinkStatusGet( mdioBaseAddr ); + + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( linkStatus & ( uint16 ) ( ( uint16 ) 1U << phyAddr ) ) != 0U ) + { + break; + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + else + { + /*SAFETYMCUSW 9 S MR:12.2 "Ternary Operator Expression" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( retries != 0U ) + { + retries--; + } + else + { + retVal = FALSE; + } + } + } + + return retVal; +} + +/** + * \brief This function does Autonegotiates with the EMAC device connected + * to the PHY. It will wait till the autonegotiation completes. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param advVal Autonegotiation advertisement value + * advVal can take the following any OR combination of the values \n + * Tlk111_100BTX - 100BaseTX + * Tlk111_100BTX_FD - Full duplex capabilty for 100BaseTX + * Tlk111_10BT - 10BaseT + * Tlk111_10BT_FD - Full duplex capability for 10BaseT + * + * \return status after autonegotiation \n + * TRUE if autonegotiation successful + * FALSE if autonegotiation failed + * + **/ +/* SourceId : ETH_SourceId_065 */ +/* DesignId : ETH_DesignId_065*/ +/* Requirements : ETH_SR46 */ +boolean Tlk111AutoNegotiate( uint32 mdioBaseAddr, uint32 phyAddr, uint16 advVal ) +{ + volatile uint16 data = 0U, anar = 0U; + boolean retVal = TRUE; + uint32 phyNegTries = 0xFFFFU; + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + data |= PHY_AUTONEG_ENABLE; + + /* Enable Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Write Auto Negotiation capabilities */ + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_AUTONEG_ADV, &anar ); + anar &= ( uint16 ) ( ~0xff10U ); + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + MDIOPhyRegWrite( mdioBaseAddr, + phyAddr, + ( uint32 ) PHY_AUTONEG_ADV, + ( anar | advVal ) ); + + data |= PHY_AUTONEG_RESTART; + + /* Start Auto Negotiation */ + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, data ); + + /* Get the auto negotiation status*/ + if( MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ) != TRUE ) + { + retVal = FALSE; + } + + /* Wait till auto negotiation is complete */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( ( ( uint16 ) ( PHY_AUTONEG_INCOMPLETE ) ) + == ( data & ( uint16 ) ( PHY_AUTONEG_STATUS ) ) ) + && ( retVal == TRUE ) && ( phyNegTries > 0U ) ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BSR, &data ); + phyNegTries--; + } + + /* Check if the PHY is able to perform auto negotiation */ + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + if( ( data & PHY_AUTONEG_ABLE ) != 0U ) + { + retVal = TRUE; + } + else + { + retVal = FALSE; + } + + return retVal; +} + +/** + * \brief Reads the Link Partner Ability register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +/* SourceId : ETH_SourceId_066 */ +/* DesignId : ETH_DesignId_066*/ +/* Requirements : ETH_SR48 */ +boolean Tlk111PartnerAbilityGet( uint32 mdioBaseAddr, + uint32 phyAddr, + uint16 * ptnerAblty ) +{ + return ( + MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_ABLTY, ptnerAblty ) ); +} + +/** + * \brief Resets the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_064 */ +/* DesignId : ETH_DesignId_064*/ +/* Requirements : ETH_SR44 */ +void Tlk111Reset( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, PHY_BCR, PHY_LPBK_ENABLE ); + /* A wait of 3us is required before allowing further operation. */ + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Enables PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_069 */ +/* DesignId : ETH_DesignId_069*/ +/* Requirements : ETH_SR51 */ +void Tlk111EnableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + /* Disabling Auto Negotiate. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_AUTONEG_ENABLE ) ); + /* Enabling Loopback. */ + regVal |= PHY_LPBK_ENABLE; + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} + +/** + * \brief Disable PHY Loopback. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * + * \return No return value. + **/ +/* SourceId : ETH_SourceId_070 */ +/* DesignId : ETH_DesignId_070*/ +/* Requirements : ETH_SR51 */ +void Tlk111DisableLoopback( uint32 mdioBaseAddr, uint32 phyAddr ) +{ + uint32 delay = 0x1FFFU; + uint16 regVal = 0x0000U; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, ®Val ); + + /* Enabling Loopback. */ + /*SAFETYMCUSW 334 S MR:10.5 "Only unsigned short values are used." */ + regVal &= ( uint16 ) ( ~( ( uint16 ) PHY_LPBK_ENABLE ) ); + + MDIOPhyRegWrite( mdioBaseAddr, phyAddr, ( uint32 ) PHY_BCR, regVal ); + + while( delay > 0U ) + { + delay--; + } +} +/** + * \brief Reads the Transmit/Receive Timestamp + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param type 1- Transmit Timetamp + * 2- Receive Timestamp + * \param timestamp The read value that is returned to the user. + * + * \return The timestamp is returned in 4 16-bit reads. They are stored in the following + *order: Timestamp_ns [63:49] Overflow_cnt[48:47], Timestamp_ns[46:33] + * Timestamp_sec[32:16] + * Timestamp_sec[15:0] + * This is returned as a 64 bit value. + * + **/ +/* SourceId : ETH_SourceId_068 */ +/* DesignId : ETH_DesignId_068*/ +/* Requirements : ETH_SR53 */ +uint64 Tlk111GetTimeStamp( uint32 mdioBaseAddr, uint32 phyAddr, phyTimeStamp_t type ) +{ + uint16 ts = 0U; + /* (MISRA-C:2004 10.1/R) MISRA error reported with Code Composer Studio MISRA checker + * (due to use of & ?) */ + uint16 * tsptr = &ts; + uint64 timeStamp = 0u; + if( type == 1U ) + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_TXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + else + { + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + ( void ) MDIOPhyRegRead( mdioBaseAddr, phyAddr, ( uint32 ) PHY_RXTS, tsptr ); + timeStamp = timeStamp << 16U; + timeStamp |= ( uint64 ) ts; + } + + return timeStamp; +} + +/** + * \brief Reads the Speed info from Status register of the PHY. + * + * \param mdioBaseAddr Base Address of the MDIO Module Registers. + * \param phyAddr PHY Adress. + * \param ptnerAblty The partner abilities of the EMAC + * + * \return status after reading \n + * TRUE if reading successful + * FALSE if reading failed + **/ +boolean Tlk111PartnerSpdGet( uint32 mdioBaseAddr, uint32 phyAddr, uint16 * ptnerAblty ) +{ + return ( MDIOPhyRegRead( mdioBaseAddr, phyAddr, PHY_LINK_PARTNER_SPD, ptnerAblty ) ); +} + +/**************************** End Of File ***********************************/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c new file mode 100644 index 00000000000..a8bca743bfa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pinmux.c @@ -0,0 +1,559 @@ +/** @file pinmux.c + * @brief PINMUX Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* Include Files */ + +#include "pinmux.h" + +#define PINMUX_GIOB_DISABLE_HET2_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 179 ] = ( pinMuxReg->PINMUX[ 179 ] \ + & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +#define PINMUX_GIOA_DISABLE_HET1_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 179 ] = ( pinMuxReg->PINMUX[ 179 ] \ + & PINMUX_GIOB_DISABLE_HET2_MASK ) \ + | ( PINMUX_GIOB_DISABLE_HET2_##state ) ) + +#define PINMUX_ETHERNET_SELECT( interface ) \ + ( pinMuxReg->PINMUX[ 160 ] = ( pinMuxReg->PINMUX[ 160 ] & PINMUX_ETHERNET_MASK ) \ + | ( PINMUX_ETHERNET_##interface ) ) + +#define PINMUX_ETPWM1_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM1_MASK ) \ + | ( PINMUX_ETPWM1_##interface ) ) + +#define PINMUX_ETPWM2_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM2_MASK ) \ + | ( PINMUX_ETPWM2_##interface ) ) + +#define PINMUX_ETPWM3_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM3_MASK ) \ + | ( PINMUX_ETPWM3_##interface ) ) + +#define PINMUX_ETPWM4_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 167 ] = ( pinMuxReg->PINMUX[ 167 ] & PINMUX_ETPWM4_MASK ) \ + | ( PINMUX_ETPWM4_##interface ) ) + +#define PINMUX_ETPWM5_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM5_MASK ) \ + | ( PINMUX_ETPWM5_##interface ) ) + +#define PINMUX_ETPWM6_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM6_MASK ) \ + | ( PINMUX_ETPWM6_##interface ) ) + +#define PINMUX_ETPWM7_EQEPERR_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 168 ] = ( pinMuxReg->PINMUX[ 168 ] & PINMUX_ETPWM7_MASK ) \ + | ( PINMUX_ETPWM7_##interface ) ) + +#define PINMUX_ETPWM_TZ1_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] & PINMUX_TZ1_MASK ) \ + | ( PINMUX_TZ1_##interface ) ) + +#define PINMUX_ETPWM_TZ2_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] & PINMUX_TZ2_MASK ) \ + | ( PINMUX_TZ2_##interface ) ) + +#define PINMUX_ETPWM_TZ3_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TZ3_MASK ) \ + | ( PINMUX_TZ3_##interface ) ) + +#define PINMUX_ETPWM_EPWM1SYNCI_ENABLE( interface ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_EPWM1SYNCI_MASK ) \ + | ( PINMUX_EPWM1SYNCI_##interface ) ) + +#define PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 165 ] \ + & PINMUX_ETPWM_TIME_BASE_SYNC_MASK ) \ + | ( PINMUX_ETPWM_TIME_BASE_SYNC_##state ) ) + +#define PINMUX_ETPWM_SOC1A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC1A_MASK ) \ + | ( PINMUX_ETPWM_SOC1A_##state ) ) + +#define PINMUX_ETPWM_SOC2A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC2A_MASK ) \ + | ( PINMUX_ETPWM_SOC2A_##state ) ) + +#define PINMUX_ETPWM_SOC3A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC3A_MASK ) \ + | ( PINMUX_ETPWM_SOC3A_##state ) ) + +#define PINMUX_ETPWM_SOC4A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 164 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC4A_MASK ) \ + | ( PINMUX_ETPWM_SOC4A_##state ) ) + +#define PINMUX_ETPWM_SOC5A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC5A_MASK ) \ + | ( PINMUX_ETPWM_SOC5A_##state ) ) + +#define PINMUX_ETPWM_SOC6A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC6A_MASK ) \ + | ( PINMUX_ETPWM_SOC6A_##state ) ) + +#define PINMUX_ETPWM_SOC7A_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 165 ] = ( pinMuxReg->PINMUX[ 164 ] & PINMUX_ETPWM_SOC7A_MASK ) \ + | ( PINMUX_ETPWM_SOC7A_##state ) ) + +#define PINMUX_GATE_EMIF_CLK_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 9 ] = ( pinMuxReg->PINMUX[ 9 ] & PINMUX_GATE_EMIF_CLK_MASK ) \ + | ( PINMUX_GATE_EMIF_CLK_##state ) ) + +#define PINMUX_ALT_ADC_TRIGGER_SELECT( num ) \ + ( pinMuxReg->PINMUX[ 161 ] = ( pinMuxReg->PINMUX[ 161 ] \ + & PINMUX_ALT_ADC_TRIGGER_MASK ) \ + | ( PINMUX_ALT_ADC_TRIGGER_##num ) ) + +#define PINMUX_EMIF_OUTPUT_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 174 ] = ( pinMuxReg->PINMUX[ 174 ] \ + & PINMUX_EMIF_OUTPUT_ENABLE_MASK ) \ + | ( PINMUX_EMIF_OUTPUT_ENABLE_##state ) ) + +#define PINMUX_EQEP1A_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] \ + & PINMUX_EQEP1A_FILTER_MASK ) \ + | ( PINMUX_EQEP1A_FILTER_##state ) ) + +#define PINMUX_EQEP1B_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] \ + & PINMUX_EQEP1B_FILTER_MASK ) \ + | ( PINMUX_EQEP1B_FILTER_##state ) ) + +#define PINMUX_EQEP1I_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP1I_FILTER_MASK ) \ + | ( PINMUX_EQEP1I_FILTER_##state ) ) + +#define PINMUX_EQEP1S_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP1S_FILTER_MASK ) \ + | ( PINMUX_EQEP1S_FILTER_##state ) ) + +#define PINMUX_EQEP2A_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP2A_FILTER_MASK ) \ + | ( PINMUX_EQEP2A_FILTER_##state ) ) + +#define PINMUX_EQEP2B_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 171 ] = ( pinMuxReg->PINMUX[ 171 ] \ + & PINMUX_EQEP2B_FILTER_MASK ) \ + | ( PINMUX_EQEP2B_FILTER_##state ) ) + +#define PINMUX_EQEP2I_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] \ + & PINMUX_EQEP2I_FILTER_MASK ) \ + | ( PINMUX_EQEP2I_FILTER_##state ) ) + +#define PINMUX_EQEP2S_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 172 ] = ( pinMuxReg->PINMUX[ 172 ] \ + & PINMUX_EQEP2S_FILTER_MASK ) \ + | ( PINMUX_EQEP2S_FILTER_##state ) ) + +#define PINMUX_ECAP1_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP1_FILTER_MASK ) \ + | ( PINMUX_ECAP1_FILTER_##state ) ) + +#define PINMUX_ECAP2_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP2_FILTER_MASK ) \ + | ( PINMUX_ECAP2_FILTER_##state ) ) + +#define PINMUX_ECAP3_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP3_FILTER_MASK ) \ + | ( PINMUX_ECAP3_FILTER_##state ) ) + +#define PINMUX_ECAP4_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 169 ] = ( pinMuxReg->PINMUX[ 169 ] & PINMUX_ECAP4_FILTER_MASK ) \ + | ( PINMUX_ECAP4_FILTER_##state ) ) + +#define PINMUX_ECAP5_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] & PINMUX_ECAP5_FILTER_MASK ) \ + | ( PINMUX_ECAP5_FILTER_##state ) ) + +#define PINMUX_ECAP6_FILTER_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 170 ] = ( pinMuxReg->PINMUX[ 170 ] & PINMUX_ECAP6_FILTER_MASK ) \ + | ( PINMUX_ECAP6_FILTER_##state ) ) + +#define PINMUX_GIOA0_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA0_DMA_MASK ) \ + | ( PINMUX_GIOA0_DMA_##state ) ) + +#define PINMUX_GIOA1_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA1_DMA_MASK ) \ + | ( PINMUX_GIOA1_DMA_##state ) ) + +#define PINMUX_GIOA2_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA2_DMA_MASK ) \ + | ( PINMUX_GIOA2_DMA_##state ) ) + +#define PINMUX_GIOA3_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 175 ] = ( pinMuxReg->PINMUX[ 175 ] & PINMUX_GIOA3_DMA_MASK ) \ + | ( PINMUX_GIOA3_DMA_##state ) ) + +#define PINMUX_GIOA4_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA4_DMA_MASK ) \ + | ( PINMUX_GIOA4_DMA_##state ) ) + +#define PINMUX_GIOA5_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA5_DMA_MASK ) \ + | ( PINMUX_GIOA5_DMA_##state ) ) + +#define PINMUX_GIOA6_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA6_DMA_MASK ) \ + | ( PINMUX_GIOA6_DMA_##state ) ) + +#define PINMUX_GIOA7_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 176 ] = ( pinMuxReg->PINMUX[ 176 ] & PINMUX_GIOA7_DMA_MASK ) \ + | ( PINMUX_GIOA7_DMA_##state ) ) + +#define PINMUX_GIOB0_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB0_DMA_MASK ) \ + | ( PINMUX_GIOB0_DMA_##state ) ) + +#define PINMUX_GIOB1_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB1_DMA_MASK ) \ + | ( PINMUX_GIOB1_DMA_##state ) ) + +#define PINMUX_GIOB2_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB2_DMA_MASK ) \ + | ( PINMUX_GIOB2_DMA_##state ) ) + +#define PINMUX_GIOB3_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 177 ] = ( pinMuxReg->PINMUX[ 177 ] & PINMUX_GIOB3_DMA_MASK ) \ + | ( PINMUX_GIOB3_DMA_##state ) ) + +#define PINMUX_GIOB4_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB4_DMA_MASK ) \ + | ( PINMUX_GIOB4_DMA_##state ) ) + +#define PINMUX_GIOB5_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB5_DMA_MASK ) \ + | ( PINMUX_GIOB5_DMA_##state ) ) + +#define PINMUX_GIOB6_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB6_DMA_MASK ) \ + | ( PINMUX_GIOB6_DMA_##state ) ) + +#define PINMUX_GIOB7_DMA_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 178 ] = ( pinMuxReg->PINMUX[ 178 ] & PINMUX_GIOB7_DMA_MASK ) \ + | ( PINMUX_GIOB7_DMA_##state ) ) + +#define PINMUX_TEMP1_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TEMP1_ENABLE_MASK ) \ + | ( PINMUX_TEMP1_ENABLE_##state ) ) + +#define PINMUX_TEMP2_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 173 ] = ( pinMuxReg->PINMUX[ 173 ] & PINMUX_TEMP2_ENABLE_MASK ) \ + | ( PINMUX_TEMP2_ENABLE_##state ) ) + +#define PINMUX_TEMP3_ENABLE( state ) \ + ( pinMuxReg->PINMUX[ 174 ] = ( pinMuxReg->PINMUX[ 174 ] & PINMUX_TEMP3_ENABLE_MASK ) \ + | ( PINMUX_TEMP3_ENABLE_##state ) ) + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +void muxInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable Pin Muxing */ + pinMuxReg->KICKER0 = 0x83E70B13U; + pinMuxReg->KICKER1 = 0x95A4F1E0U; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + pinMuxReg->PINMUX[ 0 ] = PINMUX_BALL_N19_AD1EVT | PINMUX_BALL_D4_EMIF_ADDR_00 + | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06; + + pinMuxReg->PINMUX[ 1 ] = PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 + | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10; + + pinMuxReg->PINMUX[ 2 ] = PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 + | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14; + + pinMuxReg->PINMUX[ 3 ] = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 + | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18; + + pinMuxReg->PINMUX[ 4 ] = PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 + | PINMUX_BALL_C17_EMIF_ADDR_21; + + pinMuxReg->PINMUX[ 5 ] = 0U; + + pinMuxReg->PINMUX[ 6 ] = 0U; + + pinMuxReg->PINMUX[ 7 ] = 0U; + + pinMuxReg->PINMUX[ 8 ] = PINMUX_BALL_D16_EMIF_BA_1; + + pinMuxReg->PINMUX[ 9 ] = PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 + | PINMUX_BALL_L17_EMIF_nCS_2; + + pinMuxReg->PINMUX[ 10 ] = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 + | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT; + + pinMuxReg->PINMUX[ 11 ] = PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_ETMDATA_08 + | PINMUX_BALL_E8_ETMDATA_09 | PINMUX_BALL_E7_ETMDATA_10; + + pinMuxReg->PINMUX[ 12 ] = PINMUX_BALL_E6_ETMDATA_11 | PINMUX_BALL_E13_ETMDATA_12 + | PINMUX_BALL_E12_ETMDATA_13 | PINMUX_BALL_E11_ETMDATA_14; + + pinMuxReg->PINMUX[ 13 ] = PINMUX_BALL_E10_ETMDATA_15 | PINMUX_BALL_K15_ETMDATA_16 + | PINMUX_BALL_L15_ETMDATA_17 | PINMUX_BALL_M15_ETMDATA_18; + + pinMuxReg->PINMUX[ 14 ] = PINMUX_BALL_N15_ETMDATA_19 | PINMUX_BALL_E5_ETMDATA_20 + | PINMUX_BALL_F5_ETMDATA_21 | PINMUX_BALL_G5_ETMDATA_22; + + pinMuxReg->PINMUX[ 15 ] = PINMUX_BALL_K5_ETMDATA_23 | PINMUX_BALL_L5_ETMDATA_24 + | PINMUX_BALL_M5_ETMDATA_25 | PINMUX_BALL_N5_ETMDATA_26; + + pinMuxReg->PINMUX[ 16 ] = PINMUX_BALL_P5_ETMDATA_27 | PINMUX_BALL_R5_ETMDATA_28 + | PINMUX_BALL_R6_ETMDATA_29 | PINMUX_BALL_R7_ETMDATA_30; + + pinMuxReg->PINMUX[ 17 ] = PINMUX_BALL_R8_ETMDATA_31 | PINMUX_BALL_R9_ETMTRACECLKIN + | PINMUX_BALL_R10_ETMTRACECLKOUT + | PINMUX_BALL_R11_ETMTRACECTL; + + pinMuxReg->PINMUX[ 18 ] = PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 + | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2; + + pinMuxReg->PINMUX[ 19 ] = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 + | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6; + + pinMuxReg->PINMUX[ 20 ] = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 + | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6; + + pinMuxReg->PINMUX[ 21 ] = PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MIBSPI1NCS_0 + | PINMUX_BALL_F3_MIBSPI1NCS_1 | PINMUX_BALL_G3_MIBSPI1NCS_2; + + pinMuxReg->PINMUX[ 22 ] = PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MIBSPI1NENA + | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0; + + pinMuxReg->PINMUX[ 23 ] = PINMUX_BALL_V5_MIBSPI3NCS_1 | PINMUX_BALL_B2_MIBSPI3NCS_2 + | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA; + + pinMuxReg->PINMUX[ 24 ] = PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI + | PINMUX_BALL_H19_MIBSPI5CLK | PINMUX_BALL_E19_MIBSPI5NCS_0; + + pinMuxReg->PINMUX[ 25 ] = PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 + | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MIBSPI5NENA; + + pinMuxReg->PINMUX[ 26 ] = PINMUX_BALL_J19_MIBSPI5SIMO_0 + | PINMUX_BALL_E16_MIBSPI5SIMO_1 + | PINMUX_BALL_H17_MIBSPI5SIMO_2 + | PINMUX_BALL_G17_MIBSPI5SIMO_3; + + pinMuxReg->PINMUX[ 27 ] = PINMUX_BALL_J18_MIBSPI5SOMI_0 + | PINMUX_BALL_E17_MIBSPI5SOMI_1 + | PINMUX_BALL_H16_MIBSPI5SOMI_2 + | PINMUX_BALL_G16_MIBSPI5SOMI_3; + + pinMuxReg->PINMUX[ 28 ] = PINMUX_BALL_K18_N2HET1_00 | PINMUX_BALL_V2_N2HET1_01 + | PINMUX_BALL_W5_N2HET1_02 | PINMUX_BALL_U1_N2HET1_03; + + pinMuxReg->PINMUX[ 29 ] = PINMUX_BALL_B12_N2HET1_04 | PINMUX_BALL_V6_N2HET1_05 + | PINMUX_BALL_W3_N2HET1_06 | PINMUX_BALL_T1_N2HET1_07; + + pinMuxReg->PINMUX[ 30 ] = PINMUX_BALL_E18_N2HET1_08 | PINMUX_BALL_V7_N2HET1_09 + | PINMUX_BALL_D19_N2HET1_10 | PINMUX_BALL_E3_N2HET1_11; + + pinMuxReg->PINMUX[ 31 ] = PINMUX_BALL_B4_N2HET1_12 | PINMUX_BALL_N2_N2HET1_13 + | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16; + + pinMuxReg->PINMUX[ 32 ] = PINMUX_BALL_A13_N2HET1_17 | PINMUX_BALL_J1_N2HET1_18 + | PINMUX_BALL_B13_N2HET1_19 | PINMUX_BALL_P2_N2HET1_20; + + pinMuxReg->PINMUX[ 33 ] = PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 + | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_N2HET1_24; + + pinMuxReg->PINMUX[ 34 ] = PINMUX_BALL_A14_N2HET1_26 | PINMUX_BALL_K19_N2HET1_28 + | PINMUX_BALL_B11_N2HET1_30 | PINMUX_BALL_D8_N2HET2_01; + + pinMuxReg->PINMUX[ 35 ] = PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_N2HET2_12 + | PINMUX_BALL_D2_N2HET2_13 | PINMUX_BALL_D1_N2HET2_14; + + pinMuxReg->PINMUX[ 36 ] = PINMUX_BALL_P4_N2HET2_19 | PINMUX_BALL_T5_N2HET2_20 + | PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK; + + pinMuxReg->PINMUX[ 37 ] = PINMUX_BALL_E2_N2HET2_03 | PINMUX_BALL_N3_N2HET2_07; + + pinMuxReg->PINMUX[ 80 ] = ( SIGNAL_AD2EVT_T10 | 0x02020200U ); + + pinMuxReg->PINMUX[ 81 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 82 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 83 ] = ( SIGNAL_GIOA_0_A5 | 0x00020202U ); + + pinMuxReg->PINMUX[ 84 ] = SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 + | SIGNAL_GIOA_4_A6; + + pinMuxReg->PINMUX[ 85 ] = SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 + | SIGNAL_GIOB_0_M2; + + pinMuxReg->PINMUX[ 86 ] = SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_F2 | SIGNAL_GIOB_3_W10 + | SIGNAL_GIOB_4_G1; + + pinMuxReg->PINMUX[ 87 ] = SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 + | SIGNAL_MDIO_F4; + + pinMuxReg->PINMUX[ 88 ] = ( SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9 + | 0x00020000U ); + + pinMuxReg->PINMUX[ 89 ] = SIGNAL_MII_COL_W4 | SIGNAL_MII_CRS_V4; + + pinMuxReg->PINMUX[ 90 ] = SIGNAL_MII_RX_DV_U6 | SIGNAL_MII_RX_ER_U5 + | SIGNAL_MII_RXCLK_T4 | SIGNAL_MII_RXD_0_U4; + + pinMuxReg->PINMUX[ 91 ] = SIGNAL_MII_RXD_1_T3 | SIGNAL_MII_RXD_2_U3 + | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_U7; + + pinMuxReg->PINMUX[ 92 ] = SIGNAL_N2HET1_17_A13 | SIGNAL_N2HET1_19_B13 + | SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4; + + pinMuxReg->PINMUX[ 93 ] = SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 + | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17; + + pinMuxReg->PINMUX[ 94 ] = SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 + | SIGNAL_N2HET2_02_D7 | SIGNAL_N2HET2_03_E2; + + pinMuxReg->PINMUX[ 95 ] = SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 + | SIGNAL_N2HET2_06_D11 | SIGNAL_N2HET2_07_N3; + + pinMuxReg->PINMUX[ 96 ] = SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 + | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16; + + pinMuxReg->PINMUX[ 97 ] = SIGNAL_N2HET2_12_D3 | SIGNAL_N2HET2_13_D2 + | SIGNAL_N2HET2_14_D1 | SIGNAL_N2HET2_15_K4; + + pinMuxReg->PINMUX[ 98 ] = SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 + | SIGNAL_N2HET2_20_T5 | SIGNAL_N2HET2_22_T7; + + pinMuxReg->PINMUX[ 99 ] = SIGNAL_nTZ1_1_N19 | SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3; + + pinMuxReg->PINMUX[ 161 ] = 0x02020200U; + + pinMuxReg->PINMUX[ 162 ] = 0x02020202U; + + pinMuxReg->PINMUX[ 163 ] = 0x00020202U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + PINMUX_GATE_EMIF_CLK_ENABLE( OFF ); + PINMUX_EMIF_OUTPUT_ENABLE( OFF ); + PINMUX_GIOA_DISABLE_HET1_ENABLE( OFF ); + PINMUX_GIOB_DISABLE_HET2_ENABLE( OFF ); + PINMUX_ETHERNET_SELECT( MII ); + PINMUX_ALT_ADC_TRIGGER_SELECT( 1 ); + + PINMUX_ETPWM1_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM2_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM3_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM4_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM5_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM6_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM7_EQEPERR_ENABLE( EQEPERR12 ); + PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE( OFF ); + PINMUX_ETPWM_TZ1_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ2_ENABLE( ASYNC ); + PINMUX_ETPWM_TZ3_ENABLE( ASYNC ); + PINMUX_ETPWM_EPWM1SYNCI_ENABLE( ASYNC ); + + PINMUX_ETPWM_SOC1A_ENABLE( ON ); + PINMUX_ETPWM_SOC2A_ENABLE( ON ); + PINMUX_ETPWM_SOC3A_ENABLE( ON ); + PINMUX_ETPWM_SOC4A_ENABLE( ON ); + PINMUX_ETPWM_SOC5A_ENABLE( ON ); + PINMUX_ETPWM_SOC6A_ENABLE( ON ); + PINMUX_ETPWM_SOC7A_ENABLE( ON ); + + PINMUX_EQEP1A_FILTER_ENABLE( OFF ); + PINMUX_EQEP1B_FILTER_ENABLE( OFF ); + PINMUX_EQEP1I_FILTER_ENABLE( OFF ); + PINMUX_EQEP1S_FILTER_ENABLE( OFF ); + PINMUX_EQEP2A_FILTER_ENABLE( OFF ); + PINMUX_EQEP2B_FILTER_ENABLE( OFF ); + PINMUX_EQEP2I_FILTER_ENABLE( OFF ); + PINMUX_EQEP2S_FILTER_ENABLE( OFF ); + + PINMUX_ECAP1_FILTER_ENABLE( OFF ); + PINMUX_ECAP2_FILTER_ENABLE( OFF ); + PINMUX_ECAP3_FILTER_ENABLE( OFF ); + PINMUX_ECAP4_FILTER_ENABLE( OFF ); + PINMUX_ECAP5_FILTER_ENABLE( OFF ); + PINMUX_ECAP6_FILTER_ENABLE( OFF ); + + PINMUX_GIOA0_DMA_ENABLE( OFF ); + PINMUX_GIOA1_DMA_ENABLE( OFF ); + PINMUX_GIOA2_DMA_ENABLE( OFF ); + PINMUX_GIOA3_DMA_ENABLE( OFF ); + PINMUX_GIOA4_DMA_ENABLE( OFF ); + PINMUX_GIOA5_DMA_ENABLE( OFF ); + PINMUX_GIOA6_DMA_ENABLE( OFF ); + PINMUX_GIOA7_DMA_ENABLE( OFF ); + PINMUX_GIOB0_DMA_ENABLE( OFF ); + PINMUX_GIOB1_DMA_ENABLE( OFF ); + PINMUX_GIOB2_DMA_ENABLE( OFF ); + PINMUX_GIOB3_DMA_ENABLE( OFF ); + PINMUX_GIOB4_DMA_ENABLE( OFF ); + PINMUX_GIOB5_DMA_ENABLE( OFF ); + PINMUX_GIOB6_DMA_ENABLE( OFF ); + PINMUX_GIOB7_DMA_ENABLE( OFF ); + + pinMuxReg->PINMUX[ 174 ] |= ( uint32 ) ( ~( 0XFEFFFFFFU ) ); + + PINMUX_TEMP1_ENABLE( OFF ); + PINMUX_TEMP2_ENABLE( OFF ); + PINMUX_TEMP3_ENABLE( OFF ); + + /* Disable Pin Muxing */ + pinMuxReg->KICKER0 = 0x00000000U; + pinMuxReg->KICKER1 = 0x00000000U; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (5) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c new file mode 100644 index 00000000000..3813fc4b809 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/pom.c @@ -0,0 +1,354 @@ +/** @file pom.c + * @brief POM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +#include "pom.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void POM_Region_Config(REGION_CONFIG_t *Reg_Config_Ptr,REGION_t Region_Num) + * @brief set the prog start address,overlay address,and size in the respective register + * for specified region number. + * @param[in] Reg_Config_Ptr - this will have the prog start address and overlay + * addresses and size which have to be set in the registers + * @param[in] Region_Num - Region number is used to access registers(for the specified + * region number) + * + */ +/* SourceId : POM_SourceId_001 */ +/* DesignId : POM_DesignId_001 */ +/* Requirements : CONQ_POM_SR3 */ +void POM_Region_Config( REGION_CONFIG_t * Reg_Config_Ptr, REGION_t Region_Num ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + pomREG->POMRGNCONF_ST[ Region_Num ].POMPROGSTART = Reg_Config_Ptr->Prog_Reg_Sta_Addr; + pomREG->POMRGNCONF_ST[ Region_Num ].POMOVLSTART = Reg_Config_Ptr->Ovly_Reg_Sta_Addr; + pomREG->POMRGNCONF_ST[ Region_Num ].POMREGSIZE = Reg_Config_Ptr->Reg_Size; + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void POM_Reset(void) + * @brief Reset POM module. + */ +/* SourceId : POM_SourceId_002 */ +/* DesignId : POM_DesignId_002 */ +/* Requirements : CONQ_POM_SR4 */ +void POM_Reset( void ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = 0x5U; + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void void POM_Init(void) + * @brief Initializes the POM driver + * + * This function initializes the POM driver single function handles all the + * regions,timeouts are also handled. POM_Enable() function must be called after + * POM_Init() function. + */ +/* SourceId : POM_SourceId_003 */ +/* DesignId : POM_DesignId_003 */ +/* Requirements : CONQ_POM_SR2 */ +void POM_Init( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = INTERNAL_RAM | 0x00000005U; + + /* Configure region 1 */ + pomREG->POMRGNCONF_ST[ 0U ].POMPROGSTART = 0x00000000U; + pomREG->POMRGNCONF_ST[ 0U ].POMOVLSTART = 0x00000000U; + pomREG->POMRGNCONF_ST[ 0U ].POMREGSIZE = ( uint32 ) SIZE_64BYTES; + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void POM_Enable(void) + * @brief Enable POM module. + */ +/* SourceId : POM_SourceId_004 */ +/* DesignId : POM_DesignId_004 */ +/* Requirements : CONQ_POM_SR5 */ +void POM_Enable( void ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + pomREG->POMGLBCTRL = ( ( pomREG->POMGLBCTRL & 0xFFFFFFF0U ) + | ( uint32 ) 0x0000000AU ); + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/** @fn void pomGetConfigValue(pom_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the POM configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + *need to be stored + * - InitialValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers will + *be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + *'type') of the configuration registers to the struct pointed by config_reg + * + */ + +/* SourceId : POM_SourceId_005 */ +/* DesignId : POM_DesignId_005 */ +/* Requirements : CONQ_POM_SR6 */ +void pomGetConfigValue( pom_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_POMGLBCTRL = POM_POMGLBCTRL_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART0 = POM_POMPROGSTART0_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART0 = POM_POMOVLSTART0_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE0 = POM_POMREGSIZE0_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART1 = POM_POMPROGSTART1_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART1 = POM_POMOVLSTART1_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE1 = POM_POMREGSIZE1_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART2 = POM_POMPROGSTART2_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART2 = POM_POMOVLSTART2_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE2 = POM_POMREGSIZE2_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART3 = POM_POMPROGSTART3_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART3 = POM_POMOVLSTART3_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE3 = POM_POMREGSIZE3_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART4 = POM_POMPROGSTART4_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART4 = POM_POMOVLSTART4_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE4 = POM_POMREGSIZE4_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART5 = POM_POMPROGSTART5_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART5 = POM_POMOVLSTART5_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE5 = POM_POMREGSIZE5_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART6 = POM_POMPROGSTART6_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART6 = POM_POMOVLSTART6_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE6 = POM_POMREGSIZE6_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART7 = POM_POMPROGSTART7_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART7 = POM_POMOVLSTART7_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE7 = POM_POMREGSIZE7_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART8 = POM_POMPROGSTART8_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART8 = POM_POMOVLSTART8_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE8 = POM_POMREGSIZE8_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART9 = POM_POMPROGSTART9_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART9 = POM_POMOVLSTART9_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE9 = POM_POMREGSIZE9_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART10 = POM_POMPROGSTART10_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART10 = POM_POMOVLSTART10_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE10 = POM_POMREGSIZE10_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART11 = POM_POMPROGSTART11_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART11 = POM_POMOVLSTART11_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE11 = POM_POMREGSIZE11_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART12 = POM_POMPROGSTART12_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART12 = POM_POMOVLSTART12_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE12 = POM_POMREGSIZE12_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART13 = POM_POMPROGSTART13_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART13 = POM_POMOVLSTART13_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE13 = POM_POMREGSIZE13_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART14 = POM_POMPROGSTART14_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART14 = POM_POMOVLSTART14_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE14 = POM_POMREGSIZE14_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART15 = POM_POMPROGSTART15_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART15 = POM_POMOVLSTART15_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE15 = POM_POMREGSIZE15_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART16 = POM_POMPROGSTART16_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART16 = POM_POMOVLSTART16_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE16 = POM_POMREGSIZE16_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART17 = POM_POMPROGSTART17_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART17 = POM_POMOVLSTART17_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE17 = POM_POMREGSIZE17_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART18 = POM_POMPROGSTART18_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART18 = POM_POMOVLSTART18_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE18 = POM_POMREGSIZE18_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART19 = POM_POMPROGSTART19_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART19 = POM_POMOVLSTART19_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE19 = POM_POMREGSIZE19_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART20 = POM_POMPROGSTART20_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART20 = POM_POMOVLSTART20_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE20 = POM_POMREGSIZE20_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART21 = POM_POMPROGSTART21_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART21 = POM_POMOVLSTART21_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE21 = POM_POMREGSIZE21_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART22 = POM_POMPROGSTART22_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART22 = POM_POMOVLSTART22_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE22 = POM_POMREGSIZE22_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART23 = POM_POMPROGSTART23_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART23 = POM_POMOVLSTART23_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE23 = POM_POMREGSIZE23_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART24 = POM_POMPROGSTART24_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART24 = POM_POMOVLSTART24_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE24 = POM_POMREGSIZE24_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART25 = POM_POMPROGSTART25_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART25 = POM_POMOVLSTART25_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE25 = POM_POMREGSIZE25_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART26 = POM_POMPROGSTART26_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART26 = POM_POMOVLSTART26_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE26 = POM_POMREGSIZE26_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART27 = POM_POMPROGSTART27_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART27 = POM_POMOVLSTART27_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE27 = POM_POMREGSIZE27_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART28 = POM_POMPROGSTART28_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART28 = POM_POMOVLSTART28_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE28 = POM_POMREGSIZE28_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART29 = POM_POMPROGSTART29_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART29 = POM_POMOVLSTART29_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE29 = POM_POMREGSIZE29_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART30 = POM_POMPROGSTART30_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART30 = POM_POMOVLSTART30_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE30 = POM_POMREGSIZE30_CONFIGVALUE; + config_reg->CONFIG_POMPROGSTART31 = POM_POMPROGSTART31_CONFIGVALUE; + config_reg->CONFIG_POMOVLSTART31 = POM_POMOVLSTART31_CONFIGVALUE; + config_reg->CONFIG_POMREGSIZE31 = POM_POMREGSIZE31_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "LDRA Tool issue" */ + config_reg->CONFIG_POMGLBCTRL = pomREG->POMGLBCTRL; + config_reg->CONFIG_POMPROGSTART0 = pomREG->POMRGNCONF_ST[ 0 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART0 = pomREG->POMRGNCONF_ST[ 0 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE0 = pomREG->POMRGNCONF_ST[ 0 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART1 = pomREG->POMRGNCONF_ST[ 1 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART1 = pomREG->POMRGNCONF_ST[ 1 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE1 = pomREG->POMRGNCONF_ST[ 1 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART2 = pomREG->POMRGNCONF_ST[ 2 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART2 = pomREG->POMRGNCONF_ST[ 2 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE2 = pomREG->POMRGNCONF_ST[ 2 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART3 = pomREG->POMRGNCONF_ST[ 3 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART3 = pomREG->POMRGNCONF_ST[ 3 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE3 = pomREG->POMRGNCONF_ST[ 3 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART4 = pomREG->POMRGNCONF_ST[ 4 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART4 = pomREG->POMRGNCONF_ST[ 4 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE4 = pomREG->POMRGNCONF_ST[ 4 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART5 = pomREG->POMRGNCONF_ST[ 5 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART5 = pomREG->POMRGNCONF_ST[ 5 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE5 = pomREG->POMRGNCONF_ST[ 5 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART6 = pomREG->POMRGNCONF_ST[ 6 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART6 = pomREG->POMRGNCONF_ST[ 6 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE6 = pomREG->POMRGNCONF_ST[ 6 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART7 = pomREG->POMRGNCONF_ST[ 7 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART7 = pomREG->POMRGNCONF_ST[ 7 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE7 = pomREG->POMRGNCONF_ST[ 7 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART8 = pomREG->POMRGNCONF_ST[ 8 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART8 = pomREG->POMRGNCONF_ST[ 8 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE8 = pomREG->POMRGNCONF_ST[ 8 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART9 = pomREG->POMRGNCONF_ST[ 9 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART9 = pomREG->POMRGNCONF_ST[ 9 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE9 = pomREG->POMRGNCONF_ST[ 9 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART10 = pomREG->POMRGNCONF_ST[ 10 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART10 = pomREG->POMRGNCONF_ST[ 10 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE10 = pomREG->POMRGNCONF_ST[ 10 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART11 = pomREG->POMRGNCONF_ST[ 11 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART11 = pomREG->POMRGNCONF_ST[ 11 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE11 = pomREG->POMRGNCONF_ST[ 11 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART12 = pomREG->POMRGNCONF_ST[ 12 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART12 = pomREG->POMRGNCONF_ST[ 12 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE12 = pomREG->POMRGNCONF_ST[ 12 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART13 = pomREG->POMRGNCONF_ST[ 13 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART13 = pomREG->POMRGNCONF_ST[ 13 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE13 = pomREG->POMRGNCONF_ST[ 13 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART14 = pomREG->POMRGNCONF_ST[ 14 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART14 = pomREG->POMRGNCONF_ST[ 14 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE14 = pomREG->POMRGNCONF_ST[ 14 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART15 = pomREG->POMRGNCONF_ST[ 15 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART15 = pomREG->POMRGNCONF_ST[ 15 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE15 = pomREG->POMRGNCONF_ST[ 15 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART16 = pomREG->POMRGNCONF_ST[ 16 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART16 = pomREG->POMRGNCONF_ST[ 16 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE16 = pomREG->POMRGNCONF_ST[ 16 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART17 = pomREG->POMRGNCONF_ST[ 17 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART17 = pomREG->POMRGNCONF_ST[ 17 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE17 = pomREG->POMRGNCONF_ST[ 17 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART18 = pomREG->POMRGNCONF_ST[ 18 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART18 = pomREG->POMRGNCONF_ST[ 18 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE18 = pomREG->POMRGNCONF_ST[ 18 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART19 = pomREG->POMRGNCONF_ST[ 19 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART19 = pomREG->POMRGNCONF_ST[ 19 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE19 = pomREG->POMRGNCONF_ST[ 19 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART20 = pomREG->POMRGNCONF_ST[ 20 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART20 = pomREG->POMRGNCONF_ST[ 20 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE20 = pomREG->POMRGNCONF_ST[ 20 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART21 = pomREG->POMRGNCONF_ST[ 20 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART21 = pomREG->POMRGNCONF_ST[ 21 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE21 = pomREG->POMRGNCONF_ST[ 21 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART22 = pomREG->POMRGNCONF_ST[ 21 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART22 = pomREG->POMRGNCONF_ST[ 22 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE22 = pomREG->POMRGNCONF_ST[ 22 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART23 = pomREG->POMRGNCONF_ST[ 22 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART23 = pomREG->POMRGNCONF_ST[ 23 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE23 = pomREG->POMRGNCONF_ST[ 23 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART24 = pomREG->POMRGNCONF_ST[ 23 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART24 = pomREG->POMRGNCONF_ST[ 24 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE24 = pomREG->POMRGNCONF_ST[ 24 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART25 = pomREG->POMRGNCONF_ST[ 24 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART25 = pomREG->POMRGNCONF_ST[ 25 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE25 = pomREG->POMRGNCONF_ST[ 25 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART26 = pomREG->POMRGNCONF_ST[ 25 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART26 = pomREG->POMRGNCONF_ST[ 26 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE26 = pomREG->POMRGNCONF_ST[ 26 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART27 = pomREG->POMRGNCONF_ST[ 26 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART27 = pomREG->POMRGNCONF_ST[ 27 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE27 = pomREG->POMRGNCONF_ST[ 27 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART28 = pomREG->POMRGNCONF_ST[ 27 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART28 = pomREG->POMRGNCONF_ST[ 28 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE28 = pomREG->POMRGNCONF_ST[ 28 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART29 = pomREG->POMRGNCONF_ST[ 28 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART29 = pomREG->POMRGNCONF_ST[ 29 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE29 = pomREG->POMRGNCONF_ST[ 29 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART30 = pomREG->POMRGNCONF_ST[ 30 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART30 = pomREG->POMRGNCONF_ST[ 30 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE30 = pomREG->POMRGNCONF_ST[ 30 ].POMREGSIZE; + config_reg->CONFIG_POMPROGSTART31 = pomREG->POMRGNCONF_ST[ 31 ].POMPROGSTART; + config_reg->CONFIG_POMOVLSTART31 = pomREG->POMRGNCONF_ST[ 31 ].POMOVLSTART; + config_reg->CONFIG_POMREGSIZE31 = pomREG->POMRGNCONF_ST[ 31 ].POMREGSIZE; + } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c new file mode 100644 index 00000000000..12377f8e060 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sci.c @@ -0,0 +1,994 @@ +/** @file sci.c + * @brief SCI Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +#include +/* USER CODE END */ + +#include "sci.h" +#include "sys_vim.h" +#include "math.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @struct g_sciTransfer + * @brief Interrupt mode globals + * + */ +static volatile struct g_sciTransfer +{ + uint32 mode; /* Used to check for TX interrupt Enable */ + uint32 tx_length; /* Transmit data length in number of Bytes */ + uint32 rx_length; /* Receive data length in number of Bytes */ + uint8 * tx_data; /* Transmit data pointer */ + uint8 * rx_data; /* Receive data pointer */ +} g_sciTransfer_t[ 4U ]; + +/* SourceId : SCI_SourceId_001 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : CONQ_SCI_SR5 */ + +/** @fn void sciInit(void) + * @brief Initializes the SCI Driver + * + * This function initializes the SCI module. + */ +void sciInit( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /** @b initialize @b SCI3 */ + + /** - bring SCI3 out of reset */ + sciREG3->GCR0 = 0U; + sciREG3->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG3->CLEARINT = 0xFFFFFFFFU; + sciREG3->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG3->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG3->BRS = 40U; /* baudrate */ + + /** - transmission length */ + sciREG3->FORMAT = 8U - 1U; /* length */ + + /** - set SCI3 pins functional mode */ + sciREG3->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI3 pins default output value */ + sciREG3->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins output direction */ + sciREG3->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins open drain enable */ + sciREG3->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins pullup/pulldown enable */ + sciREG3->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI3 pins pullup/pulldown select */ + sciREG3->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG3->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG3->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 2U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 2U ].tx_length = 0U; + g_sciTransfer_t[ 2U ].rx_length = 0U; + + /** - Finaly start SCI3 */ + sciREG3->GCR1 |= 0x80U; + + /** @b initialize @b SCI4 */ + + /** - bring SCI4 out of reset */ + sciREG4->GCR0 = 0U; + sciREG4->GCR0 = 1U; + + /** - Disable all interrupts */ + sciREG4->CLEARINT = 0xFFFFFFFFU; + sciREG4->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + sciREG4->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has no + clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + sciREG4->BRS = 40U; /* baudrate */ + + /** - transmission length */ + sciREG4->FORMAT = 8U - 1U; /* length */ + + /** - set SCI4 pins functional mode */ + sciREG4->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI4 pins default output value */ + sciREG4->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins output direction */ + sciREG4->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins open drain enable */ + sciREG4->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins pullup/pulldown enable */ + sciREG4->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI4 pins pullup/pulldown select */ + sciREG4->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + sciREG4->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - set interrupt enable */ + sciREG4->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U << 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 3U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 3U ].tx_length = 0U; + g_sciTransfer_t[ 3U ].rx_length = 0U; + + /** - Finaly start SCI4 */ + sciREG4->GCR1 |= 0x80U; + + /* USER CODE BEGIN (3) */ + /** @b initialize @b SCILIN */ + + /** - bring SCI out of reset */ + scilinREG->GCR0 = 0U; + scilinREG->GCR0 = 1U; + + /** - Disable all interrupts */ + scilinREG->CLEARINT = 0xFFFFFFFFU; + scilinREG->CLEARINTLVL = 0xFFFFFFFFU; + + /** - global control 1 */ + scilinREG->GCR1 = ( uint32 ) ( ( uint32 ) 1U << 25U ) /* enable transmit */ + | ( uint32 ) ( ( uint32 ) 1U << 24U ) /* enable receive */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* internal clock (device has + no clock pin) */ + | ( uint32 ) ( ( uint32 ) ( 2U - 1U ) << 4U ) /* number of stop bits + */ + | ( uint32 ) ( ( uint32 ) 0U << 3U ) /* even parity, otherwise odd */ + | ( uint32 ) ( ( uint32 ) 0U << 2U ) /* enable parity */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* asynchronous timing mode */ + + /** - set baudrate */ + scilinREG->BRS = 40U; /* baudrate */ + + /** - transmission length */ + scilinREG->FORMAT = 8U - 1U; /* length */ + + /** - set SCI pins functional mode */ + scilinREG->PIO0 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set SCI pins default output value */ + scilinREG->PIO3 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins output direction */ + scilinREG->PIO1 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins open drain enable */ + scilinREG->PIO6 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown enable */ + scilinREG->PIO7 = ( uint32 ) ( ( uint32 ) 0U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ); /* rx pin */ + + /** - set SCI pins pullup/pulldown select */ + scilinREG->PIO8 = ( uint32 ) ( ( uint32 ) 1U << 2U ) /* tx pin */ + | ( uint32 ) ( ( uint32 ) 1U << 1U ); /* rx pin */ + + /** - set interrupt level */ + scilinREG->SETINTLVL = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* Transmit */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - set interrupt enable */ + scilinREG->SETINT = ( uint32 ) ( ( uint32 ) 0U << 26U ) /* Framing error */ + | ( uint32 ) ( ( uint32 ) 0U << 25U ) /* Overrun error */ + | ( uint32 ) ( ( uint32 ) 0U << 24U ) /* Parity error */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* Receive */ + | ( uint32 ) ( ( uint32 ) 0U << 1U ) /* Wakeup */ + | ( uint32 ) ( ( uint32 ) 0U ); /* Break detect */ + + /** - initialize global transfer variables */ + g_sciTransfer_t[ 1U ].mode = ( uint32 ) 0U << 8U; + g_sciTransfer_t[ 1U ].tx_length = 0U; + g_sciTransfer_t[ 1U ].rx_length = 0U; + + /** - Finaly start SCILIN */ + scilinREG->GCR1 |= 0x80U; + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_002 */ +/* DesignId : SCI_DesignId_002 */ +/* Requirements : CONQ_SCI_SR6 */ + +/** @fn void sciSetFunctional(sciBASE_t *sci, uint32 port) + * @brief Change functional behavior of pins at runtime. + * @param[in] sci - sci module base address + * @param[in] port - Value to write to PIO0 register + * + * Change the value of the PCPIO0 register at runtime, this allows to + * dynamically change the functionality of the SCI pins between functional + * and GIO mode. + */ +void sciSetFunctional( sciBASE_t * sci, uint32 port ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + sci->PIO0 = port; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_003 */ +/* DesignId : SCI_DesignId_003 */ +/* Requirements : CONQ_SCI_SR7 */ + +/** @fn void sciSetBaudrate(sciBASE_t *sci, uint32 baud) + * @brief Change baudrate at runtime. + * @param[in] sci - sci module base address + * @param[in] baud - baudrate in Hz + * + * Change the SCI baudrate at runtime. + */ +void sciSetBaudrate( sciBASE_t * sci, uint32 baud ) +{ + float64 vclk = 75.000 * 1000000.0; + uint32 f = ( ( sci->GCR1 & 2U ) == 2U ) ? 16U : 1U; + uint32 temp; + float64 temp2; + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /*SAFETYMCUSW 96 S MR:6.1 "Calculations including int and float cannot be + * avoided" */ + temp = ( f * ( baud ) ); + temp2 = ( ( vclk ) / ( ( float64 ) temp ) ) - 1U; + temp2 = temp2 + 0.5; + sci->BRS = ( uint32 ) ( ( uint32 ) temp2 & 0x00FFFFFFU ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_004 */ +/* DesignId : SCI_DesignId_004 */ +/* Requirements : CONQ_SCI_SR8 */ + +/** @fn uint32 sciIsTxReady(sciBASE_t *sci) + * @brief Check if Tx buffer empty + * @param[in] sci - sci module base address + * + * @return The TX ready flag + * + * Checks to see if the Tx buffer ready flag is set, returns + * 0 is flags not set otherwise will return the Tx flag itself. + */ +uint32 sciIsTxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_TX_INT; +} + +/* SourceId : SCI_SourceId_005 */ +/* DesignId : SCI_DesignId_005 */ +/* Requirements : CONQ_SCI_SR9 */ + +/** @fn void sciSendByte(sciBASE_t *sci, uint8 byte) + * @brief Send Byte + * @param[in] sci - sci module base address + * @param[in] byte - byte to transfer + * + * Sends a single byte in polling mode, will wait in the + * routine until the transmit buffer is empty before sending + * the byte. Use sciIsTxReady to check for Tx buffer empty + * before calling sciSendByte to avoid waiting. + */ +void sciSendByte( sciBASE_t * sci, uint8 byte ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + sci->TD = byte; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_006 */ +/* DesignId : SCI_DesignId_006 */ +/* Requirements : CONQ_SCI_SR10 */ + +/** @fn void sciSend(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Send Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data to send + * + * Send a block of data pointed to by 'data' and 'length' bytes + * long. If interrupts have been enabled the data is sent using + * interrupt mode, otherwise polling mode is used. In interrupt + * mode transmission of the first byte is started and the routine + * returns immediately, sciSend must not be called again until the + * transfer is complete, when the sciNotification callback will + * be called. In polling mode, sciSend will not return until + * the transfer is complete. + * + * @note if data word is less than 8 bits, then the data must be left + * aligned in the data byte. + */ +void sciSend( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + uint8 txdata; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + /*SAFETYMCUSW 139 S MR:13.7 "Mode variable is configured in + * sciEnableNotification()" */ + if( ( g_sciTransfer_t[ index ].mode & ( uint32 ) SCI_TX_INT ) != 0U ) + { + /* we are in interrupt mode */ + + g_sciTransfer_t[ index ].tx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].tx_data = data; + + /* start transmit by sending first byte */ + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + txdata = *g_sciTransfer_t[ index ].tx_data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + g_sciTransfer_t[ index ].tx_data++; + sci->SETINT = ( uint32 ) SCI_TX_INT; + } + else + { + /* send the data */ + /*SAFETYMCUSW 30 S MR:12.2,12.3 "Used for data count in + * Transmit/Receive polling and Interrupt mode" */ + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_TX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + txdata = *data; + sci->TD = ( uint32 ) ( txdata ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_007 */ +/* DesignId : SCI_DesignId_007 */ +/* Requirements : CONQ_SCI_SR11 */ + +/** @fn uint32 sciIsRxReady(sciBASE_t *sci) + * @brief Check if Rx buffer full + * @param[in] sci - sci module base address + * + * @return The Rx ready flag + * + * Checks to see if the Rx buffer full flag is set, returns + * 0 is flags not set otherwise will return the Rx flag itself. + */ +uint32 sciIsRxReady( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_RX_INT; +} + +/* SourceId : SCI_SourceId_008 */ +/* DesignId : SCI_DesignId_008 */ +/* Requirements : CONQ_SCI_SR12 */ + +/** @fn uint32 sciIsIdleDetected(sciBASE_t *sci) + * @brief Check if Idle Period is Detected + * @param[in] sci - sci module base address + * + * @return The Idle flag + * + * Checks to see if the SCI Idle flag is set, returns 0 is flags + * not set otherwise will return the Ilde flag itself. + */ +uint32 sciIsIdleDetected( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + return sci->FLR & ( uint32 ) SCI_IDLE; +} + +/* SourceId : SCI_SourceId_009 */ +/* DesignId : SCI_DesignId_009 */ +/* Requirements : CONQ_SCI_SR13 */ + +/** @fn uint32 sciRxError(sciBASE_t *sci) + * @brief Return Rx Error flags + * @param[in] sci - sci module base address + * + * @return The Rx error flags + * + * Returns the Rx framing, overrun and parity errors flags, + * also clears the error flags before returning. + */ +uint32 sciRxError( sciBASE_t * sci ) +{ + uint32 status = ( sci->FLR + & ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ) ); + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT | ( uint32 ) SCI_PE_INT ); + return status; +} + +/* SourceId : SCI_SourceId_010 */ +/* DesignId : SCI_DesignId_010 */ +/* Requirements : CONQ_SCI_SR14 */ + +/** @fn uint32 sciReceiveByte(sciBASE_t *sci) + * @brief Receive Byte + * @param[in] sci - sci module base address + * + * @return Received byte + * + * Receives a single byte in polling mode. If there is + * not a byte in the receive buffer the routine will wait + * until one is received. Use sciIsRxReady to check to + * see if the buffer is full to avoid waiting. + */ +uint32 sciReceiveByte( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - Hardware Status + * check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + return ( sci->RD & ( uint32 ) 0x000000FFU ); +} + +/* SourceId : SCI_SourceId_011 */ +/* DesignId : SCI_DesignId_011 */ +/* Requirements : CONQ_SCI_SR15 */ + +/** @fn void sciReceive(sciBASE_t *sci, uint32 length, uint8 * data) + * @brief Receive Data + * @param[in] sci - sci module base address + * @param[in] length - number of data words to transfer + * @param[in] data - pointer to data buffer to receive data + * + * Receive a block of 'length' bytes long and place it into the + * data buffer pointed to by 'data'. If interrupts have been + * enabled the data is received using interrupt mode, otherwise + * polling mode is used. In interrupt mode receive is setup and + * the routine returns immediately, sciReceive must not be called + * again until the transfer is complete, when the sciNotification + * callback will be called. In polling mode, sciReceive will not + * return until the transfer is complete. + */ +void sciReceive( sciBASE_t * sci, uint32 length, uint8 * data ) +{ + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + if( ( sci->SETINT & ( uint32 ) SCI_RX_INT ) == ( uint32 ) SCI_RX_INT ) + { + /* we are in interrupt mode */ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* clear error flags */ + sci->FLR = ( ( uint32 ) SCI_FE_INT | ( uint32 ) SCI_OE_INT + | ( uint32 ) SCI_PE_INT ); + + g_sciTransfer_t[ index ].rx_length = length; + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are only + * allowed in this driver" */ + g_sciTransfer_t[ index ].rx_data = data; + } + else + { + while( length > 0U ) + { + /*SAFETYMCUSW 28 D MR:NA "Potentially infinite loop found - + * Hardware Status check for execution sequence" */ + while( ( sci->FLR & ( uint32 ) SCI_RX_INT ) == 0U ) + { + } /* Wait */ + + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + *data = ( uint8 ) ( sci->RD & 0x000000FFU ); + /*SAFETYMCUSW 45 D MR:21.1 "Valid non NULL input parameters are + * only allowed in this driver" */ + /*SAFETYMCUSW 567 S MR:17.1,17.4 "Pointer increment needed" */ + data++; + length--; + } + } + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_012 */ +/* DesignId : SCI_DesignId_014 */ +/* Requirements : CONQ_SCI_SR18 */ + +/** @fn void sciEnableLoopback(sciBASE_t *sci, loopBackType_t Loopbacktype) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * @param[in] Loopbacktype - Digital or Analog + * + * This function enables the Loopback mode for self test. + */ +void sciEnableLoopback( sciBASE_t * sci, loopBackType_t Loopbacktype ) +{ + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /* Clear Loopback incase enabled already */ + sci->IODFTCTRL = 0U; + + /* Enable Loopback either in Analog or Digital Mode */ + sci->IODFTCTRL = ( uint32 ) 0x00000A00U + | ( uint32 ) ( ( uint32 ) Loopbacktype << 1U ); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_013 */ +/* DesignId : SCI_DesignId_015 */ +/* Requirements : CONQ_SCI_SR19 */ + +/** @fn void sciDisableLoopback(sciBASE_t *sci) + * @brief Enable Loopback mode for self test + * @param[in] sci - sci module base address + * + * This function disable the Loopback mode. + */ +void sciDisableLoopback( sciBASE_t * sci ) +{ + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /* Disable Loopback Mode */ + sci->IODFTCTRL = 0x00000500U; + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_014 */ +/* DesignId : SCI_DesignId_012 */ +/* Requirements : CONQ_SCI_SR16 */ + +/** @fn sciEnableNotification(sciBASE_t *sci, uint32 flags) + * @brief Enable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be enabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +void sciEnableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode |= ( flags & ( uint32 ) SCI_TX_INT ); + sci->SETINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_015 */ +/* DesignId : SCI_DesignId_013 */ +/* Requirements : CONQ_SCI_SR17 */ + +/** @fn sciDisableNotification(sciBASE_t *sci, uint32 flags) + * @brief Disable interrupts + * @param[in] sci - sci module base address + * @param[in] flags - Interrupts to be disabled, can be ored value of: + * SCI_FE_INT - framing error, + * SCI_OE_INT - overrun error, + * SCI_PE_INT - parity error, + * SCI_RX_INT - receive buffer ready, + * SCI_TX_INT - transmit buffer ready, + * SCI_WAKE_INT - wakeup, + * SCI_BREAK_INT - break detect + */ +void sciDisableNotification( sciBASE_t * sci, uint32 flags ) +{ + uint32 index = ( sci == sciREG1 ) + ? 0U + : ( ( sci == sciREG2 ) ? 1U : ( ( sci == sciREG3 ) ? 2U : 3U ) ); + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ + + g_sciTransfer_t[ index ].mode &= ( uint32 ) ( ~( flags & ( uint32 ) SCI_TX_INT ) ); + sci->CLEARINT = ( flags & ( uint32 ) ( ~( uint32 ) ( SCI_TX_INT ) ) ); + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ +} + +/* SourceId : SCI_SourceId_016 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : */ + +/** @fn sciEnterResetState(sciBASE_t *sci) + * @brief Enter reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +void sciEnterResetState( sciBASE_t * sci ) +{ + sci->GCR1 &= 0xFFFFFF7FU; +} + +/* SourceId : SCI_SourceId_017 */ +/* DesignId : SCI_DesignId_001 */ +/* Requirements : */ + +/** @fn scixitResetState(sciBASE_t *sci) + * @brief Exit reset state + * @param[in] sci - sci module base address + * @note The SCI should only be configured while in reset state + */ +void sciExitResetState( sciBASE_t * sci ) +{ + sci->GCR1 |= 0x00000080U; +} + +/* SourceId : SCI_SourceId_020 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : CONQ_SCI_SR25 */ + +/** @fn void sci3GetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI3 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void sci3GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI3_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI3_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI3_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI3_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI3_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI3_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI3_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI3_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI3_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI3_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI3_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = sciREG3->GCR0; + config_reg->CONFIG_GCR1 = sciREG3->GCR1; + config_reg->CONFIG_SETINT = sciREG3->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG3->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG3->FORMAT; + config_reg->CONFIG_BRS = sciREG3->BRS; + config_reg->CONFIG_PIO0 = sciREG3->PIO0; + config_reg->CONFIG_PIO1 = sciREG3->PIO1; + config_reg->CONFIG_PIO6 = sciREG3->PIO6; + config_reg->CONFIG_PIO7 = sciREG3->PIO7; + config_reg->CONFIG_PIO8 = sciREG3->PIO8; + } +} + +/* SourceId : SCI_SourceId_021 */ +/* DesignId : SCI_DesignId_016 */ +/* Requirements : CONQ_SCI_SR26 */ + +/** @fn void sci4GetConfigValue(sci_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the SCI4 configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void sci4GetConfigValue( sci_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_GCR0 = SCI4_GCR0_CONFIGVALUE; + config_reg->CONFIG_GCR1 = SCI4_GCR1_CONFIGVALUE; + config_reg->CONFIG_SETINT = SCI4_SETINT_CONFIGVALUE; + config_reg->CONFIG_SETINTLVL = SCI4_SETINTLVL_CONFIGVALUE; + config_reg->CONFIG_FORMAT = SCI4_FORMAT_CONFIGVALUE; + config_reg->CONFIG_BRS = SCI4_BRS_CONFIGVALUE; + config_reg->CONFIG_PIO0 = SCI4_PIO0_CONFIGVALUE; + config_reg->CONFIG_PIO1 = SCI4_PIO1_CONFIGVALUE; + config_reg->CONFIG_PIO6 = SCI4_PIO6_CONFIGVALUE; + config_reg->CONFIG_PIO7 = SCI4_PIO7_CONFIGVALUE; + config_reg->CONFIG_PIO8 = SCI4_PIO8_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_GCR0 = sciREG4->GCR0; + config_reg->CONFIG_GCR1 = sciREG4->GCR1; + config_reg->CONFIG_SETINT = sciREG4->SETINT; + config_reg->CONFIG_SETINTLVL = sciREG4->SETINTLVL; + config_reg->CONFIG_FORMAT = sciREG4->FORMAT; + config_reg->CONFIG_BRS = sciREG4->BRS; + config_reg->CONFIG_PIO0 = sciREG4->PIO0; + config_reg->CONFIG_PIO1 = sciREG4->PIO1; + config_reg->CONFIG_PIO6 = sciREG4->PIO6; + config_reg->CONFIG_PIO7 = sciREG4->PIO7; + config_reg->CONFIG_PIO8 = sciREG4->PIO8; + } +} + +void sci_print( char * str ) +{ + sciDisplayText( scilinREG, str, strlen( str ) ); +} + +void sciDisplayText( sciBASE_t * sci, char * text, uint32_t length ) +{ + while( length-- ) + { + /* Wait until we hit an idle state */ + while( ( sci->FLR & ( uint32_t ) SCI_IDLE ) == 4U ) + { + /* Wait */ + } + + /* Send out text */ + sciSendByte( sci, *text++ ); + } +} + +void sciDisplayData( sciBASE_t * sci, uint8_t * text, uint32_t length ) +{ + uint8_t txt = 0; + uint8_t txt1 = 0; + +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + text = text + ( length - 1 ); +#endif + + while( length-- ) + { +#if( ( __little_endian__ == 1 ) || ( __LITTLE_ENDIAN__ == 1 ) ) + txt = *text--; +#else + txt = *text++; +#endif + + txt1 = txt; + + txt &= ~( 0xF0 ); + txt1 &= ~( 0x0F ); + txt1 = txt1 >> 4; + + if( txt <= 0x9 ) + { + txt += 0x30; + } + else if( ( txt > 0x9 ) && ( txt < 0xF ) ) + { + txt += 0x37; + } + else + { + txt = 0x30; + } + + if( txt1 <= 0x9 ) + { + txt1 += 0x30; + } + else if( ( txt1 > 0x9 ) && ( txt1 <= 0xF ) ) + { + txt1 += 0x37; + } + else + { + txt1 = 0x30; + } + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt1 ); /* send out text */ + + while( ( scilinREG->FLR & 0x4 ) == 4 ) /* wait until busy */ + { + } + + sciSendByte( scilinREG, txt ); /* send out text */ + } +} + +/* USER CODE BEGIN (45) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S new file mode 100644 index 00000000000..af42adc0a01 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_core.S @@ -0,0 +1,574 @@ +/*------------------------------------------------------------------------------- + sys_core.asm + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +-------------------------------------------------------------------------*/ + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize CPU Registers + + .weak _coreInitRegisters_ + .type _coreInitRegisters_, %function + +_coreInitRegisters_: + + @ After reset, the CPU is in the Supervisor mode (M = 10011) + mov r0, lr + mov r1, #0x0000 + mov r2, #0x0000 + mov r3, #0x0000 + mov r4, #0x0000 + mov r5, #0x0000 + mov r6, #0x0000 + mov r7, #0x0000 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mov r13, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to FIQ mode (M = 10001) + cps #17 + mov lr, r0 + mov r8, #0x0000 + mov r9, #0x0000 + mov r10, #0x0000 + mov r11, #0x0000 + mov r12, #0x0000 + mrs r1, cpsr + msr spsr_cxsf, r1 + @ Switch to IRQ mode (M = 10010) + cps #18 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Abort mode (M = 10111) + cps #23 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to Undefined Instruction Mode (M = 11011) + cps #27 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 @ Switch to System Mode ( Shares User Mode registers ) (M = 11111) + cps #31 + mov lr, r0 + mrs r1,cpsr + msr spsr_cxsf, r1 + + mrc p15, #0x00, r2, c1, c0, #0x02 + orr r2, r2, #0xF00000 + mcr p15, #0x00, r2, c1, c0, #0x02 + mov r2, #0x40000000 + fmxr fpexc, r2 + + fmdrr d0, r1, r1 + fmdrr d1, r1, r1 + fmdrr d2, r1, r1 + fmdrr d3, r1, r1 + fmdrr d4, r1, r1 + fmdrr d5, r1, r1 + fmdrr d6, r1, r1 + fmdrr d7, r1, r1 + fmdrr d8, r1, r1 + fmdrr d9, r1, r1 + fmdrr d10, r1, r1 + fmdrr d11, r1, r1 + fmdrr d12, r1, r1 + fmdrr d13, r1, r1 + fmdrr d14, r1, r1 + fmdrr d15, r1, r1 + bl next1 +next1: + bl next2 +next2: + bl next3 +next3: + bl next4 +next4: + bx r0 + +/*-------------------------------------------------------------------------------*/ +@ Initialize Stack Pointers + + .weak _coreInitStackPointer_ + .type _coreInitStackPointer_, %function + +_coreInitStackPointer_: + + cps #17 + ldr sp, fiqSp + cps #18 + ldr sp, irqSp + cps #19 + ldr sp, svcSp + cps #23 + ldr sp, abortSp + cps #27 + ldr sp, undefSp + cps #31 + ldr sp, userSp + bx lr + + +undefSp: .word 0x08000000+0x00000200 +svcSp: .word 0x08000000+0x00000800 +fiqSp: .word 0x08000000+0x00000A00 +abortSp: .word 0x08000000+0x00000C00 +irqSp: .word 0x08000000+0x00001000 +userSp: .word 0x08000000+0x00001000 + +/*-------------------------------------------------------------------------------*/ +@ Get CPSR Value + + .weak _getCPSRValue_ + .type _getCPSRValue_, %function + +_getCPSRValue_: + + mrs r0, CPSR + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Take CPU to IDLE state + + .weak _gotoCPUIdle_ + .type _gotoCPUIdle_, %function + +_gotoCPUIdle_: + + WFI + nop + nop + nop + nop + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable VFP Unit + + .weak _coreEnableVfp_ + .type _coreEnableVfp_, %function + +_coreEnableVfp_: + + mrc p15, #0x00, r0, c1, c0, #0x02 + orr r0, r0, #0xF00000 + mcr p15, #0x00, r0, c1, c0, #0x02 + mov r0, #0x40000000 + fmxr fpexc, r0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Event Bus Export + + .weak _coreEnableEventBusExport_ + .type _coreEnableEventBusExport_, %function + +_coreEnableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + orr r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Event Bus Export + + .weak _coreDisableEventBusExport_ + .type _coreDisableEventBusExport_, %function + +_coreDisableEventBusExport_: + + mrc p15, #0x00, r0, c9, c12, #0x00 + bic r0, r0, #0x10 + mcr p15, #0x00, r0, c9, c12, #0x00 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Offset via Vic controller + + .weak _coreEnableIrqVicOffset_ + .type _coreEnableIrqVicOffset_, %function + +_coreEnableIrqVicOffset_: + + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #0x01000000 + mcr p15, #0, r0, c1, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault status register + + .weak _coreGetDataFault_ + .type _coreGetDataFault_, %function + +_coreGetDataFault_: + + mrc p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault status register + + .weak _coreClearDataFault_ + .type _coreClearDataFault_, %function + +_coreClearDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault status register + + .weak _coreGetInstructionFault_ + .type _coreGetInstructionFault_, %function + +_coreGetInstructionFault_: + + mrc p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault status register + + .weak _coreClearInstructionFault_ + .type _coreClearInstructionFault_, %function + +_coreClearInstructionFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c0, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get data fault address register + + .weak _coreGetDataFaultAddress_ + .type _coreGetDataFaultAddress_, %function + +_coreGetDataFaultAddress_: + + mrc p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear data fault address register + + .weak _coreClearDataFaultAddress_ + .type _coreClearDataFaultAddress_, %function + +_coreClearDataFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get instruction fault address register + + .weak _coreGetInstructionFaultAddress_ + .type _coreGetInstructionFaultAddress_, %function + +_coreGetInstructionFaultAddress_: + + mrc p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear instruction fault address register + + .weak _coreClearInstructionFaultAddress_ + .type _coreClearInstructionFaultAddress_, %function + +_coreClearInstructionFaultAddress_: + + mov r0, #0 + mcr p15, #0, r0, c6, c0, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary data fault status register + + .weak _coreGetAuxiliaryDataFault_ + .type _coreGetAuxiliaryDataFault_, %function + +_coreGetAuxiliaryDataFault_: + + mrc p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary data fault status register + + .weak _coreClearAuxiliaryDataFault_ + .type _coreClearAuxiliaryDataFault_, %function + +_coreClearAuxiliaryDataFault_: + + mov r0, #0 + mcr p15, #0, r0, c5, c1, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get auxiliary instruction fault status register + + .weak _coreGetAuxiliaryInstructionFault_ + .type _coreGetAuxiliaryInstructionFault_, %function + +_coreGetAuxiliaryInstructionFault_: + + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear auxiliary instruction fault status register + + .weak _coreClearAuxiliaryInstructionFault_ + .type _coreClearAuxiliaryInstructionFault_, %function + +_coreClearAuxiliaryInstructionFault_: + + mov r0, #0 + mrc p15, #0, r0, c5, c1, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable IRQ interrupt + + .weak _disable_IRQ_interrupt_ + .type _disable_IRQ_interrupt_, %function + +_disable_IRQ_interrupt_: + + cpsid i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - CPU IRQ + + .weak _enable_IRQ_interrupt_ + .type _enable_IRQ_interrupt_, %function + +_enable_IRQ_interrupt_: + + cpsie i + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable interrupts - CPU IRQ & FIQ + + .weak _enable_interrupt_ + .type _enable_interrupt_, %function + +_enable_interrupt_: + + cpsie if + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Clear ESM CCM errorss + + .weak _esmCcmErrorsClear_ + .type _esmCcmErrorsClear_, %function + +_esmCcmErrorsClear_: + + stmfd sp!, {r0-r2} + ldr r0, ESMSR1_REG @ load the ESMSR1 status register address + ldr r2, ESMSR1_ERR_CLR + str r2, [r0] @ clear the ESMSR1 register + + ldr r0, ESMSR2_REG @ load the ESMSR2 status register address + ldr r2, ESMSR2_ERR_CLR + str r2, [r0] @ clear the ESMSR2 register + + ldr r0, ESMSSR2_REG @ load the ESMSSR2 status register address + ldr r2, ESMSSR2_ERR_CLR + str r2, [r0] @ clear the ESMSSR2 register + + ldr r0, ESMKEY_REG @ load the ESMKEY register address + mov r2, #0x5 @ load R2 with 0x5 + str r2, [r0] @ clear the ESMKEY register + + ldr r0, VIM_INTREQ @ load the INTREQ register address + ldr r2, VIM_INT_CLR + str r2, [r0] @ clear the INTREQ register + ldr r0, CCMR4_STAT_REG @ load the CCMR4 status register address + ldr r2, CCMR4_ERR_CLR + str r2, [r0] @ clear the CCMR4 status register + ldmfd sp!, {r0-r2} + bx lr + +ESMSR1_REG: .word 0xFFFFF518 +ESMSR2_REG: .word 0xFFFFF51C +ESMSR3_REG: .word 0xFFFFF520 +ESMKEY_REG: .word 0xFFFFF538 +ESMSSR2_REG: .word 0xFFFFF53C +CCMR4_STAT_REG: .word 0xFFFFF600 +ERR_CLR_WRD: .word 0xFFFFFFFF +CCMR4_ERR_CLR: .word 0x00010000 +ESMSR1_ERR_CLR: .word 0x80000000 +ESMSR2_ERR_CLR: .word 0x00000004 +ESMSSR2_ERR_CLR: .word 0x00000004 +VIM_INT_CLR: .word 0x00000001 +VIM_INTREQ: .word 0xFFFFFE20 + +/*-------------------------------------------------------------------------------*/ +@Initialize RAM memory + + .weak _memInit_ + .type _memInit_, %function + +_memInit_: + ldr r12, MINITGCR @Load MINITGCR register address + mov r4, #0xA + str r4, [r12] @Enable global memory hardware initialization + + ldr r11, MSIENA @Load MSIENA register address + mov r4, #0x1 @Bit position 0 of MSIENA corresponds to SRAM + str r4, [r11] @Enable auto hardware initalisation for SRAM +mloop: @Loop till memory hardware initialization comletes + ldr r5, MSTCGSTAT + ldr r4, [r5] + tst r4, #0x100 + beq mloop + + mov r4, #5 + str r4, [r12] @Disable global memory hardware initialization + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Check Initialize RAM memory + + .weak _checkMemInitOn_ + .type _checkMemInitOn_, %function + +_checkMemInitOn_: + ldr r12, MINITGCR @Load MINITGCR register address +mloop5: ldr r4, [r12] + teq r4, #0xA + beq mloop5 + bx lr + + +MINITGCR: .word 0xFFFFFF5C +MSIENA: .word 0xFFFFFF60 +MSTCGSTAT: .word 0xFFFFFF68 + +/*-------------------------------------------------------------------------------*/ +@ Enable caches + + .weak _cacheEnable_ + .type _cacheEnable_, %function + +_cacheEnable_: + + stmfd sp!, {r0-r1} + mov r0,#0 + + MRC p15, #0, r1, c1, c0, #1 @ Read auxiliary control register + BIC r1, r1, #0x1 << 5 @ bit is default set to disable ECC. Clearing bit 5 + MCR p15, #0, r1, c1, c0, #1 @ enable ECC, generate abort on ECC errors, enable + @ hardware recovery + + MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data + ORR R1, R1, #0x1 <<12 @ instruction cache enable + ORR R1, R1, #0x1 <<2 @ data cache enable + DSB + MCR p15, #0, r0, c15, c5, #0 @ Invalidate entire data cache + DSB @ delay is required, manually added + MCR p15, #0, r0, c7, c5, #0 @ Invalidate entire instruction cache + DSB @ delay is required, manually added + MCR p15, #0, R1, c1, c0, #0 @ enabled cache RAMs + ISB + + ldmfd sp!, {r0-r1} + + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable caches + + .weak _cacheDisable_ + .type _cacheDisable_, %function + +_cacheDisable_: + + stmfd sp!, {r1} + + MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data + BIC R1, R1, #0x1 <<12 @ instruction cache disable + BIC R1, R1, #0x1 <<2 @ data cache disable + DSB + MCR p15, #0, R1, c1, c0, #0 @ disabled cache RAMs + ISB + + ldmfd sp!, {r1} + + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Invalidate Data Cache + + .weak _dCacheInvalidate_ + .type _dCacheInvalidate_, %function + +_dCacheInvalidate_: + MOV R0,#0 + DSB + MCR P15, #0, R0, C15, C5, #0 + DSB + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Invalidate Instruction Cache + + .weak _iCacheInvalidate_ + .type _iCacheInvalidate_, %function + +_iCacheInvalidate_: + MOV R0,#0 + DSB + MCR p15, #0, r0, c7, c5, #0 + DSB + bx lr +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c new file mode 100644 index 00000000000..bca5ac8d98b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_dma.c @@ -0,0 +1,654 @@ +/** @file sys_dma.c + * @brief DMA Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the DMA driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_dma.h" +#include "sys_vim.h" + +/** @fn void dmaEnable(void) + * @brief enables DMA module + * + * This function brings DMA out of reset + */ +/* SourceId : DMA_SourceId_001 */ +/* DesignId : DMA_DesignId_001 */ +/* Requirements : CONQ_DMA_SR1 */ +void dmaEnable( void ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + dmaREG->GCTRL = 0x00010000U; /* enable dma */ + dmaREG->GCTRL |= 0x00000300U; /* stop at suspend */ + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void dmaDisable(void) + * @brief disables DMA module + * + * This function disables DMA module + */ +/* SourceId : DMA_SourceId_002 */ +/* DesignId : DMA_DesignId_002 */ +/* Requirements : CONQ_DMA_SR2 */ +void dmaDisable( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + while( ( dmaREG->GCTRL & 0x00004000U ) != 0U ) + { + } /* Wait */ + + /* Disable DMA module */ + dmaREG->GCTRL = 0U; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void dmaSetCtrlPacket(uint32 channel) + * @brief Set control packet + * + * This function sets control packet + */ +/* SourceId : DMA_SourceId_003 */ +/* DesignId : DMA_DesignId_003 */ +/* Requirements : CONQ_DMA_SR4 */ +void dmaSetCtrlPacket( dmaChannel_t channel, g_dmaCTRL g_dmaCTRLPKT ) +{ + uint8 i, j; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + dmaRAMREG->PCP[ channel ].ISADDR = g_dmaCTRLPKT.SADD; + + dmaRAMREG->PCP[ channel ].IDADDR = g_dmaCTRLPKT.DADD; + + dmaRAMREG->PCP[ channel ].ITCOUNT = ( g_dmaCTRLPKT.FRCNT << 16U ) + | g_dmaCTRLPKT.ELCNT; + + dmaRAMREG->PCP[ channel ].CHCTRL = ( g_dmaCTRLPKT.RDSIZE << 14U ) + | ( g_dmaCTRLPKT.WRSIZE << 12U ) + | ( g_dmaCTRLPKT.TTYPE << 8U ) + | ( g_dmaCTRLPKT.ADDMODERD << 3U ) + | ( g_dmaCTRLPKT.ADDMODEWR << 1U ) + | ( g_dmaCTRLPKT.AUTOINIT ); + + dmaRAMREG->PCP[ channel ].CHCTRL |= ( g_dmaCTRLPKT.CHCTRL << 16U ); + + dmaRAMREG->PCP[ channel ].EIOFF = ( g_dmaCTRLPKT.ELDOFFSET << 16U ) + | ( g_dmaCTRLPKT.ELSOFFSET ); + + dmaRAMREG->PCP[ channel ].FIOFF = ( g_dmaCTRLPKT.FRDOFFSET << 16U ) + | ( g_dmaCTRLPKT.FRSOFFSET ); + + i = channel / 8U; /* Find the register to write */ + j = channel % 8U; /* Find the offset */ + j = ( uint8 ) 7U - j; /* Reverse the order */ + j = j * 4U; /* Find the bit position */ + + dmaREG->PAR[ i ] &= ~( ( uint32 ) 0xFU << j ); + dmaREG->PAR[ i ] |= ( g_dmaCTRLPKT.PORTASGN << j ); + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void dmaSetChEnable(uint32 channel,uint32 type) + * @brief Enable channel + * @param[in] channel DMA channel + * @param[in] type Type of triggering + * - DMA_HW: Enables the selected DMA channel for hardware triggering + * - DMA_SW: Enables the selected DMA channel for software triggering + * + * This function enables the DMA channel for hardware or software triggering + */ +/* SourceId : DMA_SourceId_004 */ +/* DesignId : DMA_DesignId_004 */ +/* Requirements : CONQ_DMA_SR5 */ +void dmaSetChEnable( dmaChannel_t channel, dmaTriggerType_t type ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + if( type == DMA_HW ) + { + dmaREG->HWCHENAS = ( uint32 ) 1U << channel; + } + else + { + dmaREG->SWCHENAS = ( uint32 ) 1U << channel; + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void dmaReqAssign(uint32 channel,uint32 reqline) + * @brief Assign DMA request lines to channels + * @param[in] channel DMA channel + * @param[in] reqline DMA request line + * + * This function assigns DMA request lines to channels + */ +/* SourceId : DMA_SourceId_005 */ +/* DesignId : DMA_DesignId_005 */ +/* Requirements : CONQ_DMA_SR3 */ +void dmaReqAssign( dmaChannel_t channel, dmaRequest_t reqline ) +{ + uint8 i, j; + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + i = channel / 4U; /* Find the register to configure */ + j = channel % 4U; /* Find the offset */ + j = ( uint8 ) 3U - j; /* reverse the byte order */ + j = j * 8U; /* find the bit location */ + + /* Mapping channel 'i' to request line 'j' */ + dmaREG->DREQASI[ i ] &= ~( ( uint32 ) 0xFFU << j ); + dmaREG->DREQASI[ i ] |= ( ( uint32 ) reqline << j ); + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void dmaSetPriority(uint32 channel, dmaPRIORITY_t priority) + * @brief Assign Priority to the channel + * @param[in] channel DMA channel + * @param[in] priority Priority queue to which channel needs to be assigned + * - LOWPRIORITY : The selected channel will be assigned to low + * priority queue + * - HIGHPRIORITY: The selected channel will be assigned to high + * priority queue + * + * This function assigns the selected priority to the selected channel + */ +/* SourceId : DMA_SourceId_006 */ +/* DesignId : DMA_DesignId_006 */ +/* Requirements : CONQ_DMA_SR6 */ +void dmaSetPriority( dmaChannel_t channel, dmaPriorityQueue_t priority ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( priority == LOWPRIORITY ) + { + dmaREG->CHPRIOR = ( uint32 ) 1U << channel; + } + else + { + dmaREG->CHPRIOS = ( uint32 ) 1U << channel; + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableInterrupt(dmaChannel_t channel, dmaInterrupt_t inttype, + *dmaIntGroup_t group) + * @brief Enable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be enabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for + *the selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled + *for the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + *for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for + *the selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + *channel + * @param[in] group Group to which the interrupt is routed to. + * - DMA_INTA : Group A + * - DMA_INTB : Group B (Do not use this in case of Lock-step + *device) + * + * This function enables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_007 */ +/* DesignId : DMA_DesignId_007 */ +/* Requirements : CONQ_DMA_SR8 */ +void dmaEnableInterrupt( dmaChannel_t channel, + dmaInterrupt_t inttype, + dmaIntGroup_t group ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + dmaREG->GCHIENAS = ( uint32 ) 1U << channel; + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAS = ( uint32 ) 1U << channel; + dmaREG->FTCMAP = ( dmaREG->FTCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case LFS: + dmaREG->LFSINTENAS = ( uint32 ) 1U << channel; + dmaREG->LFSMAP = ( dmaREG->LFSMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case HBC: + dmaREG->HBCINTENAS = ( uint32 ) 1U << channel; + dmaREG->HBCMAP = ( dmaREG->HBCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + case BTC: + dmaREG->BTCINTENAS = ( uint32 ) 1U << channel; + dmaREG->BTCMAP = ( dmaREG->BTCMAP & ~( ( uint32 ) 1U << channel ) ) + | ( ( uint32 ) group << channel ); + break; + default: + break; + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} +/** @fn void dmaDisableInterrupt(uint32 channel, dmaInterrupt_t inttype) + * @brief Disable selected interrupt + * @param[in] channel DMA channel + * @param[in] inttype Interrupt to be disabled + * - FTC: Frame Transfer Complete Interrupt will be disabled for the + * selected channel + * - LFS: Last Frame Transfer Started Interrupt will be disabled for + * the selected channel + * - HBC: First Half Of Block Complete Interrupt will be disabled + * for the selected channel + * - BTC: Block transfer complete Interrupt will be disabled for the + * selected channel + * - BER: Bus Error Interrupt will be disabled for the selected + * channel + * + * This function disables the selected interrupt for the selected channel + */ +/* SourceId : DMA_SourceId_008 */ +/* DesignId : DMA_DesignId_008 */ +/* Requirements : CONQ_DMA_SR9 */ +void dmaDisableInterrupt( dmaChannel_t channel, dmaInterrupt_t inttype ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + switch( inttype ) + { + case FTC: + dmaREG->FTCINTENAR = ( uint32 ) 1U << channel; + break; + case LFS: + dmaREG->LFSINTENAR = ( uint32 ) 1U << channel; + break; + case HBC: + dmaREG->HBCINTENAR = ( uint32 ) 1U << channel; + break; + case BTC: + dmaREG->BTCINTENAR = ( uint32 ) 1U << channel; + break; + default: + break; + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} +/** @fn void dmaDefineRegion(dmaREGION_t region, uint32 start_add, uint32 end_add) + * @brief Configure start and end address of the region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * @param[in] start_add Start address of the the region + * @param[in] end_add End address of the region + * + * This function configure start and end address of the selected region + */ +/* SourceId : DMA_SourceId_009 */ +/* DesignId : DMA_DesignId_009 */ +/* Requirements : CONQ_DMA_SR10 */ +void dmaDefineRegion( dmaMPURegion_t region, uint32 start_add, uint32 end_add ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + if( region < 4U ) + { + dmaREG->DMAMPR_L[ region ].STARTADD = start_add; + dmaREG->DMAMPR_L[ region ].ENDADD = end_add; + } + else + { + dmaREG->DMAMPR_H[ region - 4U ].STARTADD = start_add; + dmaREG->DMAMPR_H[ region - 4U ].ENDADD = end_add; + } + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableRegion(dmaREGION_t region, dmaRegionAccess_t access, dmaMPUInt_t + * intenable) + * @brief Enable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * @param[in] access Access permission of the selected region + * - FULLACCESS + * - READONLY + * - WRITEONLY + * - NOACCESS + * @param[in] intenable Interrupt to be enabled or not + * - INTERRUPTA_ENABLE : Enable Group A interrupt for the selected + * region + * - INTERRUPTB_ENABLE : Enable Group B interrupt for the selected + * region (Do not use this in case of Lock-step device) + * - INTERRUPT_DISABLE : Disable interrupt for the selected region + * + * This function enables the selected region with selected access permission with or + * without interrupt enable + */ +/* SourceId : DMA_SourceId_010 */ +/* DesignId : DMA_DesignId_010 */ +/* Requirements : CONQ_DMA_SR11 */ +void dmaEnableRegion( dmaMPURegion_t region, + dmaRegionAccess_t access, + dmaMPUInt_t intenable ) +{ + uint8 bitpos = 0U; + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + if( region < 4U ) + { + bitpos = region * 8U; + dmaREG->DMAMPCTRL1 &= ~( uint32 ) ( ( uint32 ) 0xFFU << bitpos ); + + dmaREG->DMAMPCTRL1 |= ( ( uint32 ) 1U << bitpos ) /* Enable the region */ + | ( ( uint32 ) access << ( bitpos + 1U ) ) /* Set access + permission for + the region */ + | ( ( uint32 ) intenable + << ( bitpos + 3U ) ); /* Enable or Disable interrupt + */ + } + else + { + bitpos = ( region - 4U ) * 8U; + dmaREG->DMAMPCTRL2 &= ~( ( uint32 ) 0xFFU << bitpos ); + + dmaREG->DMAMPCTRL2 |= ( ( uint32 ) 1U << bitpos ) /* Enable the region */ + | ( ( uint32 ) access << ( bitpos + 1U ) ) /* Set access + permission for + the region */ + | ( ( uint32 ) intenable + << ( bitpos + 3U ) ); /* Enable or Disable interrupt + */ + } + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void dmaDisableRegion(dmaREGION_t region) + * @brief Disable the selected region + * @param[in] region Memory Region + * - DMA_REGION0 + * - DMA_REGION1 + * - DMA_REGION2 + * - DMA_REGION3 + * - DMA_REGION4 + * - DMA_REGION5 + * - DMA_REGION6 + * - DMA_REGION7 + * + * This function disables the selected region(no address checking done). + */ +/* SourceId : DMA_SourceId_011 */ +/* DesignId : DMA_DesignId_011 */ +/* Requirements : CONQ_DMA_SR12 */ +void dmaDisableRegion( dmaMPURegion_t region ) +{ + uint8 bitpos = 0U; + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + if( region < 4U ) + { + bitpos = region * 8U; + dmaREG->DMAMPCTRL1 &= ~( ( uint32 ) 1U << bitpos ); + } + else + { + bitpos = ( region - 4U ) * 8U; + dmaREG->DMAMPCTRL2 &= ~( ( uint32 ) 1U << bitpos ); + } + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void dmaEnableECC(void) + * @brief Enable ECC + * + * This function enables ECC check + */ +/* SourceId : DMA_SourceId_012 */ +/* DesignId : DMA_DesignId_012 */ +/* Requirements : CONQ_DMA_SR13 */ +void dmaEnableECC( void ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + dmaREG->DMAPCR = 0xAU; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void dmaDisableECC(void) + * @brief Disable ECC + * + * This function disables ECC check + */ +/* SourceId : DMA_SourceId_013 */ +/* DesignId : DMA_DesignId_013 */ +/* Requirements : CONQ_DMA_SR14 */ +void dmaDisableECC( void ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + dmaREG->DMAPCR = 0x5U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn uint32 dmaGetReq(uint32 channel) + * @brief Gets the request line number mapped to the selected channel + * @param[in] channel DMA channel + * + * This function returns the request line number mapped to the selected channel + */ +/* SourceId : DMA_SourceId_014 */ +/* DesignId : DMA_DesignId_014 */ +/* Requirements : CONQ_DMA_SR3 */ +uint32 dmaGetReq( dmaChannel_t channel ) +{ + uint8 i, j; + + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + i = channel / 4U; /* Find the register to configure */ + j = channel % 4U; /* Find the offset */ + j = ( uint8 ) 3U - j; /* reverse the byte order */ + j = j * 8U; /* find the bit location */ + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + return ( ( dmaREG->DREQASI[ i ] >> j ) & 0xFFU ); +} + +/** @fn boolean dmaIsChannelActive(dmaChannel_t channel) + * @brief Gets the status of the DMA channel + * @param[in] channel DMA channel + * + * This function returns TRUE if the channel is currently being processed using one of + * the FIFOs. + */ +/* SourceId : DMA_SourceId_015 */ +/* DesignId : DMA_DesignId_016 */ +/* Requirements : CONQ_DMA_SR21 */ +boolean dmaIsChannelActive( dmaChannel_t channel ) +{ + boolean status; + uint32 bitmask = ( uint32 ) 1U << channel; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + if( ( dmaREG->DMASTAT & bitmask ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ + + return status; +} + +/** @fn boolean dmaIsBusy(void) + * @brief Gets the status of the DMA bus + * + * This function returns TRUE if DMA's external bus is busy in data transfers + */ +/* SourceId : DMA_SourceId_016 */ +/* DesignId : DMA_DesignId_015 */ +/* Requirements : CONQ_DMA_SR20 */ +boolean dmaIsBusy( void ) +{ + boolean status; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + if( ( dmaREG->GCTRL & 0x4000U ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + + return status; +} + +/* SourceId : DMA_SourceId_017 */ +/* DesignId : DMA_DesignId_017 */ +/* Requirements : CONQ_DMA_SR22 */ +boolean dmaGetInterruptStatus( dmaChannel_t channel, dmaInterrupt_t inttype ) +{ + boolean status; + uint32 mask = ( uint32 ) 1U << channel; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + switch( inttype ) + { + case FTC: + status = ( ( dmaREG->FTCFLAG & mask ) != 0U ); + break; + case LFS: + status = ( ( dmaREG->LFSFLAG & mask ) != 0U ); + break; + case HBC: + status = ( ( dmaREG->HBCFLAG & mask ) != 0U ); + break; + case BTC: + status = ( ( dmaREG->BTCFLAG & mask ) != 0U ); + break; + default: + status = FALSE; + break; + } + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S new file mode 100644 index 00000000000..881537438ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_intvecs.S @@ -0,0 +1,75 @@ +/*--------------------------------------------------------------------------- + sys_intvecs.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +----------------------------------------------------------------------------*/ + + .syntax unified + .cpu cortex-r5 + .arm + + .section .intvecs,"a",%progbits + .type resetEntry, %object + .size resetEntry, .-resetEntry + +/*-------------------------------------------------------------------------------*/ +@ import reference for interrupt routines + + .extern _c_int00 + .extern FreeRTOS_SVC_Handler + .extern _dabort + .extern phantomInterrupt + .weak resetEntry + +/*-------------------------------------------------------------------------------*/ +@ interrupt vectors + +resetEntry: + b _c_int00 +undefEntry: + b undefEntry +svcEntry: + b FreeRTOS_SVC_Handler +prefetchEntry: + b prefetchEntry +dataAbortEntry: + b _dabort + b phantomInterrupt + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * IRQVECREG: 0x18 - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + /** This LDR loads the memory at ‘PC - 0x1B0’, which is the address of + * FIQVECREG: 0x1C - 0x1B0 = 0xFFFFFE70. */ + ldr pc,[pc,#-0x1b0] + +/*-------------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld new file mode 100644 index 00000000000..958b5541d33 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_link.ld @@ -0,0 +1,186 @@ +/*----------------------------------------------------------------------------*/ +/* sys_link.ld */ +/* */ +/* (c) Texas Instruments 2009-2014, All rights reserved. */ +/* */ +/*----------------------------------------------------------------------------*/ +/* Entry Point */ +ENTRY(_c_int00) + +/* Highest address of the stack */ +_estack = 0x8080000; /* end of 512K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x400; /* required amount of heap */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 4M + RAM (xrw) : ORIGIN = 0x08000000, LENGTH = 512K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K +} + +/** Common sizes + * 0x0000 0001 == 1B + * 0x0000 0002 == 2B + * 0x0000 0004 == 4B + * 0x0000 0008 == 8B + * 0x0000 0010 == 16B + * 0x0000 0020 == 32B + * 0x0000 0040 == 64B + * 0x0000 0080 == 128B + * 0x0000 0100 == 256B + * 0x0000 0200 == 512B + * 0x0000 0400 == 1K + * 0x0000 0800 == 2K + * 0x0000 1000 == 4K + * 0x0000 2000 == 8K + * 0x0000 4000 == 16K + * 0x0000 8000 == 32K + * 0x0001 0000 == 64K + * 0x0002 0000 == 128K + * 0x0003 0000 == 192K + * 0x0004 0000 == 256K + * 0x0008 0000 == 512K + * 0x0010 0000 == 1024K/1MB + * 0x0014 0000 == 1280KB/1.25 MB + * 0x0020 0000 == 2048K/2MB + * 0x0040 0000 == 4096K/4MB + * 0x0080 0000 == 8192K/8MB + * 0x0100 0000 == 16MB + * 0x0200 0000 == 32MB + * 0x0400 0000 == 64MB + * 0x0800 0000 == 128MB +*/ + +/* The first 2K of space in RAM is used for different processor mode stacks */ +__interrupt_stack_region_size = 0x1000; + +/* Define output sections */ +SECTIONS +{ + /* The ISR vector goes first into RAM */ + .intvecs : + { + . = ALIGN(4); + KEEP(*(.intvecs)) + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into RAM */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into RAM */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* Used by sys_startup.c to initialize data */ + _sidata = LOADADDR(.data); + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + . = __interrupt_stack_region_size; + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + PROVIDE ( end = _ebss ); + PROVIDE ( _end = _ebss ); + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c new file mode 100644 index 00000000000..2a4ece6cb9c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pcr.c @@ -0,0 +1,1081 @@ +/** @file sys_pcr.c + * @brief PCR Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * - Interrupt Handlers + * . + * which are relevant for the PCR driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pcr.h" + +/** @fn void peripheral_Memory_Protection_Set(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Set Peripheral Memory Protection + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function enables peripheral memory protection (write in privileged mode only) + * for the selected frame + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_001 */ +/* DesignId : PCR_DesignId_001 */ +/* Requirements : CONQ_PCR_SR1 */ +void peripheral_Memory_Protection_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PMPROTSET0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PMPROTSET1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_Protection_Clr(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Clear Peripheral Memory Protection + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function disables peripheral memory protection (write in privileged mode only) + * for the selected frame + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_002 */ +/* DesignId : PCR_DesignId_002 */ +/* Requirements : CONQ_PCR_SR2 */ +void peripheral_Memory_Protection_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PMPROTCLR0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PMPROTCLR1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_Protection_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Protection + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function enables peripheral frame protection (write in privileged mode only) for + *the selected frame + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_003 */ +/* DesignId : PCR_DesignId_003 */ +/* Requirements : CONQ_PCR_SR3 */ +void peripheral_Frame_Protection_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PPROTSET0 = quadrant << PS * 4U; + } + else if( PS < 16U ) + { + pcr->PPROTSET1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PPROTSET2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PPROTSET3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_Protection_Clr(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Clear Peripheral Frame Protection + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function disables peripheral frame protection (write in privileged mode only) + *for the selected frame + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_004 */ +/* DesignId : PCR_DesignId_004 */ +/* Requirements : CONQ_PCR_SR4 */ +void peripheral_Frame_Protection_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PPROTCLR0 = quadrant << PS * 4U; + } + else if( PS < 16U ) + { + pcr->PPROTCLR1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PPROTCLR2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PPROTCLR3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_PowerDown_Set(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Set Peripheral Memory Power Down + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function disables the clocks to the selected peripheral memory + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_005 */ +/* DesignId : PCR_DesignId_005 */ +/* Requirements : CONQ_PCR_SR5 */ +void peripheral_Memory_PowerDown_Set( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PCSPWRDWNSET0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PCSPWRDWNSET1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_PowerDown_Clr(pcrBASE_t *pcr, peripheral_Memory_t PCS) + * @brief Clear Peripheral Memory Power Down + * + * @param[in] pcr PCR segment that contains the peripheral memory (pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * + * This function enables the clocks to the selected peripheral memory + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + * memory + */ +/* SourceId : PCR_SourceId_006 */ +/* DesignId : PCR_DesignId_006 */ +/* Requirements : CONQ_PCR_SR6 */ +void peripheral_Memory_PowerDown_Clr( pcrBASE_t * pcr, peripheral_Memory_t PCS ) +{ + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + if( PCS < 32U ) + { + pcr->PCSPWRDWNCLR0 = ( uint32 ) 1U << PCS; + } + else + { + pcr->PCSPWRDWNCLR1 = ( uint32 ) 1U << ( PCS - 32U ); + } + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_PowerDown_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Power Down + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function disables the clocks to the selected quadrant(s) + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_007 */ +/* DesignId : PCR_DesignId_007 */ +/* Requirements : CONQ_PCR_SR7 */ +void peripheral_Frame_PowerDown_Set( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PSPWRDWNSET0 = quadrant << ( PS * 4U ); + } + else if( PS < 16U ) + { + pcr->PSPWRDWNSET1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PSPWRDWNSET2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PSPWRDWNSET3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_PowerDown_Set(pcrBASE_t *pcr, peripheral_Frame_t PS, uint32 + *quadrant) + * @brief Set Peripheral Frame Power Down + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * + * This function enables the clocks to the selected quadrant(s) + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_008*/ +/* DesignId : PCR_DesignId_008 */ +/* Requirements : CONQ_PCR_SR8 */ +void peripheral_Frame_PowerDown_Clr( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant ) +{ + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + if( PS < 8U ) + { + pcr->PSPWRDWNCLR0 = quadrant << ( PS * 4U ); + } + else if( PS < 16U ) + { + pcr->PSPWRDWNCLR1 = quadrant << ( ( PS - 8U ) * 4U ); + } + else if( PS < 24U ) + { + pcr->PSPWRDWNCLR2 = quadrant << ( ( PS - 16U ) * 4U ); + } + else + { + pcr->PSPWRDWNCLR3 = quadrant << ( ( PS - 24U ) * 4U ); + } + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, peripheral_Frame_t PS, + *uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_009 */ +/* DesignId : PCR_DesignId_010 */ +/* Requirements : CONQ_PCR_SR14 */ +void peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, peripheral_Frame_t + *PS, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PS Peripheral chip select (PS0..PS31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_010 */ +/* DesignId : PCR_DesignId_009 */ +/* Requirements : CONQ_PCR_SR13 */ +void peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Frame_t PS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PSxMSTID[ PS ].PSxMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Frame_t PPS, uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPS Privileged Peripheral chip select (PPS0..PPS7) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_011 */ +/* DesignId : PCR_DesignId_012 */ +/* Requirements : CONQ_PCR_SR16 */ +void privileged_Peripheral_Frame_MasterIDFilter_Enable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Frame_t PPS, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPS Privileged Peripheral chip select (PPS0..PPS7) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_012 */ +/* DesignId : PCR_DesignId_011 */ +/* Requirements : CONQ_PCR_SR15 */ +void privileged_Peripheral_Frame_MasterIDFilter_Disable( pcrBASE_t * pcr, + privileged_Peripheral_Frame_t PPS, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (22) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSxMSTID[ PPS ].PPSxMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (23) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Extended_Frame_t PPSE, uint32 quadrant, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPSE Privileged Peripheral Extended chip select (PPSE0..PPSE31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSEx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_013 */ +/* DesignId : PCR_DesignId_014 */ +/* Requirements : CONQ_PCR_SR18 */ +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L |= ( uint32 ) 1U << ( master + 16U ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H |= ( uint32 ) 1U << master; + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H |= ( uint32 ) 1U << ( master + 16U ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (25) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Extended_Frame_t PPSE, uint32 quadrant, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral + *quadrant(s) + * + * @param[in] pcr PCR segment that contains the peripheral (pcrREG1..pcrREG3) + * @param[in] PPSE Privileged Peripheral Extended chip select (PPSE0..PPSE31) + * @param[in] quadrant Quandrant(s) of peripheral frame. Can be ORed value of: + * - QUADRANT0 + * - QUADRANT1 + * - QUADRANT2 + * - QUADRANT3 + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral quadrant(s). This function will not enable master-id check for the selected + *PCR. Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPSEx corresponding to each peripheral + *frame + */ +/* SourceId : PCR_SourceId_014 */ +/* DesignId : PCR_DesignId_013 */ +/* Requirements : CONQ_PCR_SR17 */ +void privileged_Peripheral_Extended_Frame_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Extended_Frame_t PPSE, + uint32 quadrant, + master_ID_t master ) +{ + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + quadrant = quadrant & 0xFU; + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + if( ( quadrant & QUADRANT0 ) != 0U ) + { + /* Quadrant 0 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT1 ) != 0U ) + { + /* Quadrant 2 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_L &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + if( ( quadrant & QUADRANT2 ) != 0U ) + { + /* Quadrant 3 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H &= ~( ( uint32 ) 1U << master ); + } + + if( ( quadrant & QUADRANT3 ) != 0U ) + { + /* Quadrant 4 selected */ + pcr->PPSExMSTID[ PPSE ].PPSExMSTID_H &= ~( ( uint32 ) 1U << ( master + 16U ) ); + } + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (27) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_MasterIDFilter_Enable(pcrBASE_t *pcr, peripheral_Memory_t + *PCS, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_015 */ +/* DesignId : PCR_DesignId_016 */ +/* Requirements : CONQ_PCR_SR20 */ +void peripheral_Memory_MasterIDFilter_Enable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PCS / 2U; + j = PCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PCSxMSTID[ i ] |= ( uint32 ) 1U << ( master + j ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (29) */ + /* USER CODE END */ +} + +/** @fn void peripheral_Memory_MasterIDFilter_Disable(pcrBASE_t *pcr, peripheral_Memory_t + *PCS, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PCS Peripheral memory chip select (PCS0..PCS63) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_016 */ +/* DesignId : PCR_DesignId_015 */ +/* Requirements : CONQ_PCR_SR19 */ +void peripheral_Memory_MasterIDFilter_Disable( pcrBASE_t * pcr, + peripheral_Memory_t PCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (30) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PCS / 2U; + j = PCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PCSxMSTID[ i ] &= ~( ( uint32 ) 1U << ( master + j ) ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (31) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Memory_MasterIDFilter_Enable(pcrBASE_t *pcr, + *privileged_Peripheral_Memory_t PPCS, master_ID_t master) + * @brief Enable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PPCS Privileged Peripheral memory chip select (PPCS0..PPCS15) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function enables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_017 */ +/* DesignId : PCR_DesignId_018 */ +/* Requirements : CONQ_PCR_SR22 */ +void privileged_Peripheral_Memory_MasterIDFilter_Enable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PPCS / 2U; + j = PPCS % 2U; + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PPCSxMSTID[ i ] |= ( uint32 ) 1U << ( master + j ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (33) */ + /* USER CODE END */ +} + +/** @fn void privileged_Peripheral_Memory_MasterIDFilter_Disable(pcrBASE_t *pcr, + *privileged_Peripheral_Memory_t PPCS, master_ID_t master) + * @brief Disable permission of the corresponding master to access the peripheral memory + * + * @param[in] pcr PCR segment that contains the peripheral memory + *(pcrREG1..pcrREG3) + * @param[in] PPCS Privileged Peripheral memory chip select (PPCS0..PPCS15) + * @param[in] master Master-ID + * - Master_CPU0 + * - Master_CPU1(Reserved for Lock-Step device) + * - Master_DMA + * - Master_HTU1 + * - Master_HTU2 + * - Master_FTU + * - Master_DMM + * - Master_DAP + * - Master_EMAC + * + * This function disables the permission of the corresponding master to access the + *peripheral memory. This function will not enable master-id check for the selected PCR. + *Application must call the routine pcrEnableMasterIDCheck to do the same. + * @note Please refer the datasheet for PCRx and PPCSx corresponding to each peripheral + *memory + */ +/* SourceId : PCR_SourceId_018 */ +/* DesignId : PCR_DesignId_017 */ +/* Requirements : CONQ_PCR_SR21 */ +void privileged_Peripheral_Memory_MasterIDFilter_Disable( + pcrBASE_t * pcr, + privileged_Peripheral_Memory_t PPCS, + master_ID_t master ) +{ + uint8 i, j; + + /* USER CODE BEGIN (34) */ + /* USER CODE END */ + + /* Enable MasterID register writes */ + pcr->MSTIDWRENA = 0xAU; + + i = PPCS / 2U; /* Find the index of the register to be written */ + j = PPCS % 2U; /* Find the bit position */ + j = j * 16U; /* j = 0 for even numbers and 16 for odd numbers */ + + pcr->PPCSxMSTID[ i ] &= ~( ( uint32 ) 1U << ( master + j ) ); + + /* Disable MasterID register writes */ + pcr->MSTIDWRENA = 0x5U; + + /* USER CODE BEGIN (35) */ + /* USER CODE END */ +} + +/** @fn void pcrEnableMasterIDCheck(pcrBASE_t *pcr) + * @brief Enable Master-ID check + * + * @param[in] pcr PCR segment (pcrREG1..pcrREG3) + * + * This function enables master-id check for the selected PCR. + */ +/* SourceId : PCR_SourceId_019 */ +/* DesignId : PCR_DesignId_019 */ +/* Requirements : CONQ_PCR_SR11 */ +void pcrEnableMasterIDCheck( pcrBASE_t * pcr ) +{ + /* USER CODE BEGIN (36) */ + /* USER CODE END */ + + pcr->MSTIDENA = 0xAU; + + /* USER CODE BEGIN (37) */ + /* USER CODE END */ +} + +/** @fn void pcrDisableMasterIDCheck(pcrBASE_t *pcr) + * @brief Disable Master-ID check + * + * @param[in] pcr PCR segment (pcrREG1..pcrREG3) + * + * This function disables master-id check for the selected PCR. + */ +/* SourceId : PCR_SourceId_020 */ +/* DesignId : PCR_DesignId_020*/ +/* Requirements : CONQ_PCR_SR12 */ +void pcrDisableMasterIDCheck( pcrBASE_t * pcr ) +{ + /* USER CODE BEGIN (38) */ + /* USER CODE END */ + + pcr->MSTIDENA = 0x5U; + + /* USER CODE BEGIN (39) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c new file mode 100644 index 00000000000..ab428fddc7f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_phantom.c @@ -0,0 +1,77 @@ +/** @file sys_phantom.c + * @brief Phantom Interrupt Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Phantom Interrupt Handler + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_common.h" +#include "sys_vim.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Phantom Interrupt Handler */ + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +void phantomInterrupt( void ) +{ + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/** @fn void custom_dabort(void) + * @brief Custom Data abort routine for the application. + * + * Custom Data abort routine for the application. + */ +void custom_dabort( void ) +{ + /* Need custom data abort handler here. + * This data abort is not caused due to diagnostic checks of flash and TCRAM ECC + * logic. + */ + /* USER CODE BEGIN (42) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c new file mode 100644 index 00000000000..a6339001706 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmm.c @@ -0,0 +1,229 @@ +/** @file sys_pmm.c + * @brief PCR Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_pmm.h" + +#define PMM_LODICPWRSTAT 0x3U +#define PMM_DOMAINON 0x100U +#define PMM_AUTOCLKWAKEENA 0x1U + +/** @fn void pmmTurnONLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns on Logic Power Domain + * @param[in] logicPD - Power Domain to be turned on + * - PMM_LOGICPD2: Power domain PD2 will be turned on + * - PMM_LOGICPD3: Power domain PD3 will be turned on + * - PMM_LOGICPD4: Power domain PD4 will be turned on + * - PMM_LOGICPD5: Power domain PD5 will be turned on + * - PMM_LOGICPD6: Power domain PD6 will be turned on + * + * This function turns on the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_001 */ +/* DesignId : PMM_DesignId_001 */ +/* Requirements : CONQ_PMM_SR3 */ +boolean pmmTurnONLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + boolean status = TRUE; + + /* USER CODE BEGIN (0) */ + /* USER CODE END */ + + /* Power On the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x05000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x00050000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000500U; + } + else if( logicPD == PMM_LOGICPD5 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) | 0x00000005U; + } + else if( logicPD == PMM_LOGICPD6 ) + { + pmmREG->LOGICPDPWRCTRL1 = 0x05000000U; + } + else + { + /* Invalid input */ + status = FALSE; + } + + if( status == TRUE ) + { + if( ( pmmREG->GLOBALCTRL1 & PMM_AUTOCLKWAKEENA ) == 0U ) + { + /* Enable clocks to the power domain */ + pmmREG->PDCLKDISCLR = ( uint32 ) 1U << logicPD; + } + + /* Wait until the domain is powered on */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_DOMAINON ) == 0U ) + { + /* Add timeout code here */ + } + } + + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + return status; +} + +/** @fn void pmmTurnOFFLogicPowerDomain(pmm_LogicPD_t logicPD) + * @brief Turns off Logic Power Domain + * @param[in] logicPD - Power Domain to be tured off + * - PMM_LOGICPD2: Power domain PD2 will be turned off + * - PMM_LOGICPD3: Power domain PD3 will be turned off + * - PMM_LOGICPD4: Power domain PD4 will be turned off + * - PMM_LOGICPD5: Power doamin PD5 will be turned off + * - PMM_LOGICPD6: Power doamin PD5 will be turned off + * + * This function turns off the selected Logic Power Domain + * + */ +/* SourceId : PMM_SourceId_002 */ +/* DesignId : PMM_DesignId_002 */ +/* Requirements : CONQ_PMM_SR4 */ +boolean pmmTurnOFFLogicPowerDomain( pmm_LogicPD_t logicPD ) +{ + boolean status = TRUE; + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ + + /* Disable clocks to the power domain */ + pmmREG->PDCLKDISSET = ( uint32 ) 1U << logicPD; + + /* Power Down the domain */ + if( logicPD == PMM_LOGICPD2 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xF0FFFFFFU ) | 0x0A000000U; + } + else if( logicPD == PMM_LOGICPD3 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFF0FFFFU ) | 0x000A0000U; + } + else if( logicPD == PMM_LOGICPD4 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFF0FFU ) | 0x00000A00U; + } + else if( logicPD == PMM_LOGICPD5 ) + { + pmmREG->LOGICPDPWRCTRL0 = ( pmmREG->LOGICPDPWRCTRL0 & 0xFFFFFFF0U ) | 0x0000000AU; + } + else if( logicPD == PMM_LOGICPD6 ) + { + pmmREG->LOGICPDPWRCTRL1 = 0x0A000000U; + } + else + { + /* Invalid input */ + status = FALSE; + } + + if( status == TRUE ) + { + /* Wait until the domain is powered down */ + while( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LODICPWRSTAT ) != 0U ) + { + /* Add timeout code here */ + } + } + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + return status; +} + +/** @fn boolean pmmIsLogicPowerDomainActive(pmm_LogicPD_t logicPD) + * @brief Check if the power domain is active or not + * @param[in] logicPD - Power Domain to be be checked + * - PMM_LOGICPD2: Checks whether Power domain PD2 is active or not + * - PMM_LOGICPD3: Checks whether Power domain PD3 is active or not + * - PMM_LOGICPD4: Checks whether Power domain PD4 is active or not + * - PMM_LOGICPD5: Checks whether Power domain PD5 is active or not + * - PMM_LOGICPD6: Checks whether Power domain PD6 is active or not + * @return The function will return: + * - TRUE : When the selected power domain is in Active state. + * - FALSE: When the selected power domain is in OFF state. + * + * This function checks whether the selected power domain is active or not. + * + */ +/* SourceId : PMM_SourceId_003 */ +/* DesignId : PMM_DesignId_003 */ +/* Requirements : CONQ_PMM_SR5 */ +boolean pmmIsLogicPowerDomainActive( pmm_LogicPD_t logicPD ) +{ + boolean status; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + + if( logicPD == PMM_LOGICPD1 ) + { + status = TRUE; + } + else + { + if( ( pmmREG->LOGICPDPWRSTAT[ logicPD ] & PMM_LODICPWRSTAT ) == 0U ) + { + status = FALSE; + } + else + { + status = TRUE; + } + } + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + return status; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S new file mode 100644 index 00000000000..cf54214b1ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_pmu.S @@ -0,0 +1,215 @@ +/*------------------------------------------------------------------------------ + sys_pmu.s + + Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names of + its contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +---------------------------------------------------------------------------*/ + + + .section .text + .syntax unified + .cpu cortex-r4 + .arm + +/*-------------------------------------------------------------------------------*/ +@ Initialize Pmu +@ Note: It will reset all counters + + .weak _pmuInit_ + .type _pmuInit_, %function + +_pmuInit_: + + @ set control register + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #(1 << 4) + 6 + 1 + mcr p15, #0, r0, c9, c12, #0 + @ clear flags + mov r0, #0 + sub r0, r0, #1 + mcr p15, #0, r0, c9, c12, #3 + @ select counter 0 event + mov r0, #0 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 1 event + mov r0, #1 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + @ select counter 2 event + mov r0, #2 + mcr p15, #0, r0, c9, c12, #5 @ select counter + mov r0, #0x11 + mcr p15, #0, r0, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Enable Counters Global [Cycle, Event [0..2]] +@ Note: It will reset all counters + + .weak _pmuEnableCountersGlobal_ + .type _pmuEnableCountersGlobal_, %function + +_pmuEnableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #7 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Disable Counters Global [Cycle, Event [0..2]] + + .weak _pmuDisableCountersGlobal_ + .type _pmuDisableCountersGlobal_, %function + +_pmuDisableCountersGlobal_: + + mrc p15, #0, r0, c9, c12, #0 + bic r0, r0, #1 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter + + .weak _pmuResetCycleCounter_ + .type _pmuResetCycleCounter_, %function + +_pmuResetCycleCounter_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #4 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Event Counters [0..2] + + .weak _pmuResetEventCounters_ + .type _pmuResetEventCounters_, %function + +_pmuResetEventCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #2 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Reset Cycle Counter abd Event Counters [0..2] + + .weak _pmuResetCounters_ + .type _pmuResetCounters_, %function + +_pmuResetCounters_: + + mrc p15, #0, r0, c9, c12, #0 + orr r0, r0, #6 + mcr p15, #0, r0, c9, c12, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Start Counters [Cycle, 0..2] + + .weak _pmuStartCounters_ + .type _pmuStartCounters_, %function + +_pmuStartCounters_: + + mcr p15, #0, r0, c9, c12, #1 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Stop Counters [Cycle, 0..2] + + .weak _pmuStopCounters_ + .type _pmuStopCounters_, %function + +_pmuStopCounters_: + + mcr p15, #0, r0, c9, c12, #2 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Set Count event + + .weak _pmuSetCountEvent_ + .type _pmuSetCountEvent_, %function + +_pmuSetCountEvent_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mcr p15, #0, r1, c9, c13, #1 @ select event + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Cycle Count + + .weak _pmuGetCycleCount_ + .type _pmuGetCycleCount_, %function + +_pmuGetCycleCount_: + + mrc p15, #0, r0, c9, c13, #0 + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Event Counter Count Value + + .weak _pmuGetEventCount_ + .type _pmuGetEventCount_, %function + +_pmuGetEventCount_: + + mcr p15, #0, r0, c9, c12, #5 @ select counter + mrc p15, #0, r0, c9, c13, #2 @ read event counter + bx lr + +/*-------------------------------------------------------------------------------*/ +@ Get Overflow Flags + + .weak _pmuGetOverflow_ + .type _pmuGetOverflow_, %function + +_pmuGetOverflow_: + + mrc p15, #0, r0, c9, c12, #3 @ read overflow + mov r1, #0 + sub r1, r1, #1 + mcr p15, #0, r1, c9, c12, #3 @ clear flags + bx lr + +/*-------------------------------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c new file mode 100644 index 00000000000..e62403f53fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_startup.c @@ -0,0 +1,290 @@ +/** @file sys_startup.c + * @brief Startup Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - Include Files + * - Type Definitions + * - External Functions + * - VIM RAM Setup + * - Startup Routine + * . + * which are relevant for the Startup. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "sys_common.h" +#include "system.h" +#include "sys_vim.h" +#include "sys_core.h" +#include "esm.h" +#include "sys_mpu.h" +#include "errata_SSWF021_45.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ + +/* External Functions */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(main should be declared by the user)" + */ +extern void main( void ); +/*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be present)" + */ +/*SAFETYMCUSW 354 S MR:NA " Startup code(Extern declaration present in the + * library)" */ +extern void exit( int _status ); + +/* USER CODE BEGIN (3) */ +/* USER CODE END */ +void handlePLLLockFail( void ); +/* Startup Routine */ +void _c_int00( void ) __attribute__( ( noreturn ) ); +#define PLL_RETRIES 5U +/* USER CODE BEGIN (4) */ +/* USER CODE END */ + +__attribute__( ( naked ) ) + +/* SourceId : STARTUP_SourceId_001 */ +/* DesignId : STARTUP_DesignId_001 */ +/* Requirements : CONQ_STARTUP_SR1 */ +void _c_int00( void ) +{ + register resetSource_t rstSrc; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + /* Initialize Core Registers to avoid CCM Error */ + _coreInitRegisters_(); + + /* Initialize Stack Pointers */ + _coreInitStackPointer_(); + + /* Reset handler: the following instructions read from the system exception status + * register to identify the cause of the CPU reset. + */ + rstSrc = getResetSource(); + + switch( rstSrc ) + { + case POWERON_RESET: + /* Initialize L2RAM to avoid ECC errors right after power on */ + _memInit_(); + + /* Add condition to check whether PLL can be started successfully */ + if( _errata_SSWF021_45_both_plls( PLL_RETRIES ) != 0U ) + { + /* Put system in a safe state */ + handlePLLLockFail(); + } + break; + + /*SAFETYMCUSW 62 S MR:15.2, 15.5 "Need to continue to handle + * POWERON Reset" */ + case DEBUG_RESET: + case EXT_RESET: + + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /* Initialize L2RAM to avoid ECC errors right after power on */ + if( rstSrc != POWERON_RESET ) + { + _memInit_(); + } + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ + + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ + + /* Check if there were ESM group3 errors during power-up. + * These could occur during eFuse auto-load or during reads from flash OTP + * during power-up. Device operation is not reliable and not recommended + * in this case. */ + if( ( esmREG->SR1[ 2 ] ) != 0U ) + { + esmGroup3Notification( esmREG, esmREG->SR1[ 2 ] ); + } + + /* Initialize System - Clock, Flash settings with Efuse self check */ + systemInit(); + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Enable IRQ offset via Vic controller */ + _coreEnableIrqVicOffset_(); + + /* Initialize VIM table */ + vimInit(); + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + /* Configure system response to error conditions signaled to the ESM group1 */ + /* This function can be configured from the ESM tab of HALCoGen */ + esmInit(); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + break; + + case OSC_FAILURE_RESET: + /* USER CODE BEGIN (14) */ + /* USER CODE END */ + break; + + case WATCHDOG_RESET: + case WATCHDOG2_RESET: + + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + break; + + case CPU0_RESET: + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /* Enable CPU Event Export */ + + /* This allows the CPU to signal any single-bit or double-bit errors detected + * by its ECC logic for accesses to program flash or data RAM. + */ + _coreEnableEventBusExport_(); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + break; + + case SW_RESET: + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + break; + + default: + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + break; + } + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ + + { + extern uint32 _sidata, _sdata, _edata; + uint32 *src, *dst; + + src = &_sidata; + dst = &_sdata; + + while( dst < &_edata ) + { + *dst++ = *src++; + } + + } + /* USER CODE BEGIN (26) */ + /* USER CODE END */ + + /* call the application */ + /*SAFETYMCUSW 296 S MR:8.6 "Startup code(library functions at block scope)" + */ + /*SAFETYMCUSW 326 S MR:8.2 "Startup code(Declaration for main in library)" + */ + /*SAFETYMCUSW 60 D MR:8.8 "Startup code(Declaration for main in + * library;Only doing an extern for the same)" */ + main(); + + /*SAFETYMCUSW 122 S MR:20.11 "Startup code(exit and abort need to be + * present)" */ + exit( 0 ); + /* USER CODE BEGIN (77) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (29) */ +/* USER CODE END */ + +/** @fn void handlePLLLockFail(void) + * @brief This function handles PLL lock fail. + */ +/* USER CODE BEGIN (30) */ +/* USER CODE END */ +void handlePLLLockFail( void ) +{ + /* USER CODE BEGIN (31) */ + /* USER CODE END */ + while( 1 ) + { + } + + /* USER CODE BEGIN (32) */ + /* USER CODE END */ +} +/* USER CODE BEGIN (33) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c new file mode 100644 index 00000000000..fd3b1c86be6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/sys_vim.c @@ -0,0 +1,855 @@ +/** @file sys_vim.c + * @brief VIM Driver Implementation File + * @date 11-Dec-2018 + * @version 04.07.01 + * + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include "sys_vim.h" +#include "system.h" +#include "esm.h" + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Vim Ram Definition */ +/** @struct vimRam + * @brief Vim Ram Definition + * + * This type is used to access the Vim Ram. + */ +/** @typedef vimRAM_t + * @brief Vim Ram Type Definition + * + * This type is used to access the Vim Ram. + */ +typedef volatile struct vimRam +{ + t_isrFuncPTR ISR[ VIM_CHANNELS ]; +} vimRAM_t; + +#define vimRAM ( ( vimRAM_t * ) 0xFFF82000U ) + +static const t_isrFuncPTR s_vim_init[ 128U ] = { + &phantomInterrupt, &esmHighInterrupt, /* Channel 0 */ + &phantomInterrupt, /* Channel 1 */ + &FreeRTOS_IRQ_Handler, /* Channel 2 */ + &phantomInterrupt, /* Channel 3 */ + &phantomInterrupt, /* Channel 4 */ + &phantomInterrupt, /* Channel 5 */ + &phantomInterrupt, /* Channel 6 */ + &phantomInterrupt, /* Channel 7 */ + &phantomInterrupt, /* Channel 8 */ + &phantomInterrupt, /* Channel 9 */ + &phantomInterrupt, /* Channel 10 */ + &phantomInterrupt, /* Channel 11 */ + &phantomInterrupt, /* Channel 12 */ + &phantomInterrupt, /* Channel 13 */ + &phantomInterrupt, /* Channel 14 */ + &phantomInterrupt, /* Channel 15 */ + &phantomInterrupt, /* Channel 16 */ + &phantomInterrupt, /* Channel 17 */ + &phantomInterrupt, /* Channel 18 */ + &phantomInterrupt, /* Channel 19 */ + &phantomInterrupt, /* Channel 20 */ + &FreeRTOS_IRQ_Handler, /* Channel 21 */ + &phantomInterrupt, /* Channel 22 */ + &phantomInterrupt, /* Channel 23 */ + &phantomInterrupt, /* Channel 24 */ + &phantomInterrupt, /* Channel 25 */ + &phantomInterrupt, /* Channel 26 */ + &phantomInterrupt, /* Channel 27 */ + &phantomInterrupt, /* Channel 28 */ + &phantomInterrupt, /* Channel 29 */ + &phantomInterrupt, /* Channel 30 */ + &phantomInterrupt, /* Channel 31 */ + &phantomInterrupt, /* Channel 32 */ + &phantomInterrupt, /* Channel 33 */ + &phantomInterrupt, /* Channel 34 */ + &phantomInterrupt, /* Channel 35 */ + &phantomInterrupt, /* Channel 36 */ + &phantomInterrupt, /* Channel 37 */ + &phantomInterrupt, /* Channel 38 */ + &phantomInterrupt, /* Channel 39 */ + &phantomInterrupt, /* Channel 40 */ + &phantomInterrupt, /* Channel 41 */ + &phantomInterrupt, /* Channel 42 */ + &phantomInterrupt, /* Channel 43 */ + &phantomInterrupt, /* Channel 44 */ + &phantomInterrupt, /* Channel 45 */ + &phantomInterrupt, /* Channel 46 */ + &phantomInterrupt, /* Channel 47 */ + &phantomInterrupt, /* Channel 48 */ + &phantomInterrupt, /* Channel 49 */ + &phantomInterrupt, /* Channel 50 */ + &phantomInterrupt, /* Channel 51 */ + &phantomInterrupt, /* Channel 52 */ + &phantomInterrupt, /* Channel 53 */ + &phantomInterrupt, /* Channel 54 */ + &phantomInterrupt, /* Channel 55 */ + &phantomInterrupt, /* Channel 56 */ + &phantomInterrupt, /* Channel 57 */ + &phantomInterrupt, /* Channel 58 */ + &phantomInterrupt, /* Channel 59 */ + &phantomInterrupt, /* Channel 60 */ + &phantomInterrupt, /* Channel 61 */ + &phantomInterrupt, /* Channel 62 */ + &phantomInterrupt, /* Channel 63 */ + &phantomInterrupt, /* Channel 64 */ + &phantomInterrupt, /* Channel 65 */ + &phantomInterrupt, /* Channel 66 */ + &phantomInterrupt, /* Channel 67 */ + &phantomInterrupt, /* Channel 68 */ + &phantomInterrupt, /* Channel 69 */ + &phantomInterrupt, /* Channel 70 */ + &phantomInterrupt, /* Channel 71 */ + &phantomInterrupt, /* Channel 72 */ + &phantomInterrupt, /* Channel 73 */ + &phantomInterrupt, /* Channel 74 */ + &phantomInterrupt, /* Channel 75 */ + &phantomInterrupt, /* Channel 76 */ + &phantomInterrupt, /* Channel 77 */ + &phantomInterrupt, /* Channel 78 */ + &phantomInterrupt, /* Channel 79 */ + &phantomInterrupt, /* Channel 80 */ + &phantomInterrupt, /* Channel 81 */ + &phantomInterrupt, /* Channel 82 */ + &phantomInterrupt, /* Channel 83 */ + &phantomInterrupt, /* Channel 84 */ + &phantomInterrupt, /* Channel 85 */ + &phantomInterrupt, /* Channel 86 */ + &phantomInterrupt, /* Channel 87 */ + &phantomInterrupt, /* Channel 88 */ + &phantomInterrupt, /* Channel 89 */ + &phantomInterrupt, /* Channel 90 */ + &phantomInterrupt, /* Channel 91 */ + &phantomInterrupt, /* Channel 92 */ + &phantomInterrupt, /* Channel 93 */ + &phantomInterrupt, /* Channel 94 */ + &phantomInterrupt, /* Channel 95 */ + &phantomInterrupt, /* Channel 96 */ + &phantomInterrupt, /* Channel 97 */ + &phantomInterrupt, /* Channel 98 */ + &phantomInterrupt, /* Channel 99 */ + &phantomInterrupt, /* Channel 100 */ + &phantomInterrupt, /* Channel 101 */ + &phantomInterrupt, /* Channel 102 */ + &phantomInterrupt, /* Channel 103 */ + &phantomInterrupt, /* Channel 104 */ + &phantomInterrupt, /* Channel 105 */ + &phantomInterrupt, /* Channel 106 */ + &phantomInterrupt, /* Channel 107 */ + &phantomInterrupt, /* Channel 108 */ + &phantomInterrupt, /* Channel 109 */ + &phantomInterrupt, /* Channel 110 */ + &phantomInterrupt, /* Channel 111 */ + &phantomInterrupt, /* Channel 112 */ + &phantomInterrupt, /* Channel 113 */ + &phantomInterrupt, /* Channel 114 */ + &phantomInterrupt, /* Channel 115 */ + &phantomInterrupt, /* Channel 116 */ + &phantomInterrupt, /* Channel 117 */ + &phantomInterrupt, /* Channel 118 */ + &phantomInterrupt, /* Channel 119 */ + &phantomInterrupt, /* Channel 120 */ + &phantomInterrupt, /* Channel 121 */ + &phantomInterrupt, /* Channel 122 */ + &phantomInterrupt, /* Channel 123 */ + &phantomInterrupt, /* Channel 124 */ + &phantomInterrupt, /* Channel 125 */ + &phantomInterrupt, /* Channel 126 */ +}; +void vimECCErrorHandler( void ); + +/* SourceId : VIM_SourceId_001 */ +/* DesignId : VIM_DesignId_001 */ +/* Requirements : CONQ_VIM_SR2 */ +/** @fn void vimInit(void) + * @brief Initializes VIM module + * + * This function initializes VIM RAM and registers + */ + +void vimInit( void ) +{ + /* USER CODE BEGIN (1) */ + /* USER CODE END */ + + /* Enable ECC for VIM RAM */ + /* Errata VIM#28 Workaround: Disable Single Bit error correction */ + vimREG->ECCCTL = ( uint32 ) ( ( uint32 ) 0xAU << 0U ) + | ( uint32 ) ( ( uint32 ) 0x5U << 16U ); + + /* Initialize VIM table */ + { + uint32 i; + + for( i = 0U; i < VIM_CHANNELS; i++ ) + { + vimRAM->ISR[ i ] = s_vim_init[ i ]; + } + } + vimREG->FBVECADDR = ( uint32 ) &vimECCErrorHandler; + + /* set IRQ/FIQ priorities */ + vimREG->FIRQPR0 = ( uint32 ) ( ( uint32 ) SYS_FIQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_FIQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR1 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR2 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + vimREG->FIRQPR3 = ( uint32 ) ( ( uint32 ) SYS_IRQ << 0U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 1U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 2U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 3U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 5U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 6U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 7U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 9U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 10U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 11U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 12U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 13U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 14U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 15U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 17U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 18U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 19U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 21U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 22U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 23U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 25U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 26U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 27U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 28U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 29U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 30U ) + | ( uint32 ) ( ( uint32 ) SYS_IRQ << 31U ); + + /* enable interrupts */ + vimREG->REQMASKSET0 = ( uint32 ) ( ( uint32 ) 1U << 0U ) + | ( uint32 ) ( ( uint32 ) 1U << 1U ) + | ( uint32 ) ( ( uint32 ) 1U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 1U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET1 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET2 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + vimREG->REQMASKSET3 = ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 1U ) + | ( uint32 ) ( ( uint32 ) 0U << 2U ) + | ( uint32 ) ( ( uint32 ) 0U << 3U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) 0U << 5U ) + | ( uint32 ) ( ( uint32 ) 0U << 6U ) + | ( uint32 ) ( ( uint32 ) 0U << 7U ) + | ( uint32 ) ( ( uint32 ) 0U << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 9U ) + | ( uint32 ) ( ( uint32 ) 0U << 10U ) + | ( uint32 ) ( ( uint32 ) 0U << 11U ) + | ( uint32 ) ( ( uint32 ) 0U << 12U ) + | ( uint32 ) ( ( uint32 ) 0U << 13U ) + | ( uint32 ) ( ( uint32 ) 0U << 14U ) + | ( uint32 ) ( ( uint32 ) 0U << 15U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) + | ( uint32 ) ( ( uint32 ) 0U << 17U ) + | ( uint32 ) ( ( uint32 ) 0U << 18U ) + | ( uint32 ) ( ( uint32 ) 0U << 19U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) 0U << 21U ) + | ( uint32 ) ( ( uint32 ) 0U << 22U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 25U ) + | ( uint32 ) ( ( uint32 ) 0U << 26U ) + | ( uint32 ) ( ( uint32 ) 0U << 27U ) + | ( uint32 ) ( ( uint32 ) 0U << 28U ) + | ( uint32 ) ( ( uint32 ) 0U << 29U ) + | ( uint32 ) ( ( uint32 ) 0U << 30U ) + | ( uint32 ) ( ( uint32 ) 0U << 31U ); + + /* Set Capture event sources */ + vimREG->CAPEVT = ( ( uint32 ) ( ( uint32 ) 0U << 0U ) + | ( uint32 ) ( ( uint32 ) 0U << 16U ) ); + + /* USER CODE BEGIN (2) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_002 */ +/* DesignId : VIM_DesignId_002 */ +/* Requirements : CONQ_VIM_SR5 */ +/** @fn void vimChannelMap(uint32 request, uint32 channel, t_isrFuncPTR handler) + * @brief Map selected interrupt request to the selected channel + * + * @param[in] request: Interrupt request number 2..95 + * @param[in] channel: VIM Channel number 2..95 + * @param[in] handler: Address of the interrupt handler + * + * This function will map selected interrupt request to the selected channel. + * + */ +void vimChannelMap( uint32 request, uint32 channel, t_isrFuncPTR handler ) +{ + uint32 i, j; + + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + i = channel >> 2U; /* Find the register to configure */ + j = channel - ( i << 2U ); /* Find the offset of the type */ + j = 3U - j; /* reverse the byte order */ + j = j << 3U; /* find the bit location */ + + /*Mapping the required interrupt request to the required channel*/ + vimREG->CHANCTRL[ i ] &= ~( uint32 ) ( ( uint32 ) 0xFFU << j ); + vimREG->CHANCTRL[ i ] |= ( request << j ); + + /*Updating VIMRAM*/ + vimRAM->ISR[ channel + 1U ] = handler; + + /* USER CODE BEGIN (4) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_003 */ +/* DesignId : VIM_DesignId_003 */ +/* Requirements : CONQ_VIM_SR3 */ +/** @fn void vimEnableInterrupt(uint32 channel, systemInterrupt_t inttype) + * @brief Enable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..95 + * @param[in] inttype: Interrupt type + * - SYS_IRQ: Selected channel will be enabled as IRQ + * - SYS_FIQ: Selected channel will be enabled as FIQ + * + * This function will enable interrupt for the selected channel. + * + */ +void vimEnableInterrupt( uint32 channel, systemInterrupt_t inttype ) +{ + /* USER CODE BEGIN (5) */ + /* USER CODE END */ + + if( channel >= 96U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR3 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 96U ) ); + } + else + { + vimREG->FIRQPR3 |= ( ( uint32 ) 1U << ( channel - 96U ) ); + } + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR2 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 64U ) ); + } + else + { + vimREG->FIRQPR2 |= ( ( uint32 ) 1U << ( channel - 64U ) ); + } + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR1 &= ~( uint32 ) ( ( uint32 ) 1U << ( channel - 32U ) ); + } + else + { + vimREG->FIRQPR1 |= ( ( uint32 ) 1U << ( channel - 32U ) ); + } + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + if( inttype == SYS_IRQ ) + { + vimREG->FIRQPR0 &= ~( uint32 ) ( ( uint32 ) 1U << channel ); + } + else + { + vimREG->FIRQPR0 |= ( ( uint32 ) 1U << channel ); + } + vimREG->REQMASKSET0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } + /* USER CODE BEGIN (6) */ + /* USER CODE END */ +} + +/* SourceId : VIM_SourceId_004 */ +/* DesignId : VIM_DesignId_004 */ +/* Requirements : CONQ_VIM_SR5 */ +/** @fn void vimDisableInterrupt(uint32 channel) + * @brief Disable interrupt for the the selected channel + * + * @param[in] channel: VIM Channel number 2..95 + * + * This function will disable interrupt for the selected channel. + * + */ +void vimDisableInterrupt( uint32 channel ) +{ + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + if( channel >= 96U ) + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( channel - 96U ); + } + else if( channel >= 64U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( channel - 64U ); + } + else if( channel >= 32U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( channel - 32U ); + } + else if( channel >= 2U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << channel; + } + else + { + /* Empty */ + } + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (9) */ +/* USER CODE END */ + +/* SourceId : VIM_SourceId_005 */ +/* DesignId : VIM_DesignId_005 */ +/* Requirements : CONQ_VIM_SR7 */ +/** @fn void vimGetConfigValue(vim_config_reg_t *config_reg, config_value_type_t type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current value + * of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + * + */ + +void vimGetConfigValue( vim_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_FIRQPR0 = VIM_FIRQPR0_CONFIGVALUE; + config_reg->CONFIG_FIRQPR1 = VIM_FIRQPR1_CONFIGVALUE; + config_reg->CONFIG_FIRQPR2 = VIM_FIRQPR2_CONFIGVALUE; + config_reg->CONFIG_FIRQPR3 = VIM_FIRQPR3_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET0 = VIM_REQMASKSET0_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET1 = VIM_REQMASKSET1_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET2 = VIM_REQMASKSET2_CONFIGVALUE; + config_reg->CONFIG_REQMASKSET3 = VIM_REQMASKSET3_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET0 = VIM_WAKEMASKSET0_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET1 = VIM_WAKEMASKSET1_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET2 = VIM_WAKEMASKSET2_CONFIGVALUE; + config_reg->CONFIG_WAKEMASKSET3 = VIM_WAKEMASKSET3_CONFIGVALUE; + config_reg->CONFIG_CAPEVT = VIM_CAPEVT_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 0U ] = VIM_CHANCTRL0_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 1U ] = VIM_CHANCTRL1_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 2U ] = VIM_CHANCTRL2_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 3U ] = VIM_CHANCTRL3_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 4U ] = VIM_CHANCTRL4_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 5U ] = VIM_CHANCTRL5_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 6U ] = VIM_CHANCTRL6_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 7U ] = VIM_CHANCTRL7_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 8U ] = VIM_CHANCTRL8_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 9U ] = VIM_CHANCTRL9_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 10U ] = VIM_CHANCTRL10_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 11U ] = VIM_CHANCTRL11_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 12U ] = VIM_CHANCTRL12_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 13U ] = VIM_CHANCTRL13_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 14U ] = VIM_CHANCTRL14_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 15U ] = VIM_CHANCTRL15_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 16U ] = VIM_CHANCTRL16_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 17U ] = VIM_CHANCTRL17_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 18U ] = VIM_CHANCTRL18_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 19U ] = VIM_CHANCTRL19_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 20U ] = VIM_CHANCTRL20_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 21U ] = VIM_CHANCTRL21_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 22U ] = VIM_CHANCTRL22_CONFIGVALUE; + config_reg->CONFIG_CHANCTRL[ 23U ] = VIM_CHANCTRL23_CONFIGVALUE; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Register read back support" */ + config_reg->CONFIG_FIRQPR0 = vimREG->FIRQPR0; + config_reg->CONFIG_FIRQPR1 = vimREG->FIRQPR1; + config_reg->CONFIG_FIRQPR2 = vimREG->FIRQPR2; + config_reg->CONFIG_FIRQPR3 = vimREG->FIRQPR3; + config_reg->CONFIG_REQMASKSET0 = vimREG->REQMASKSET0; + config_reg->CONFIG_REQMASKSET1 = vimREG->REQMASKSET1; + config_reg->CONFIG_REQMASKSET2 = vimREG->REQMASKSET2; + config_reg->CONFIG_REQMASKSET3 = vimREG->REQMASKSET3; + config_reg->CONFIG_WAKEMASKSET0 = vimREG->WAKEMASKSET0; + config_reg->CONFIG_WAKEMASKSET1 = vimREG->WAKEMASKSET1; + config_reg->CONFIG_WAKEMASKSET2 = vimREG->WAKEMASKSET2; + config_reg->CONFIG_WAKEMASKSET3 = vimREG->WAKEMASKSET3; + config_reg->CONFIG_CAPEVT = vimREG->CAPEVT; + config_reg->CONFIG_CHANCTRL[ 0U ] = vimREG->CHANCTRL[ 0U ]; + config_reg->CONFIG_CHANCTRL[ 1U ] = vimREG->CHANCTRL[ 1U ]; + config_reg->CONFIG_CHANCTRL[ 2U ] = vimREG->CHANCTRL[ 2U ]; + config_reg->CONFIG_CHANCTRL[ 3U ] = vimREG->CHANCTRL[ 3U ]; + config_reg->CONFIG_CHANCTRL[ 4U ] = vimREG->CHANCTRL[ 4U ]; + config_reg->CONFIG_CHANCTRL[ 5U ] = vimREG->CHANCTRL[ 5U ]; + config_reg->CONFIG_CHANCTRL[ 6U ] = vimREG->CHANCTRL[ 6U ]; + config_reg->CONFIG_CHANCTRL[ 7U ] = vimREG->CHANCTRL[ 7U ]; + config_reg->CONFIG_CHANCTRL[ 8U ] = vimREG->CHANCTRL[ 8U ]; + config_reg->CONFIG_CHANCTRL[ 9U ] = vimREG->CHANCTRL[ 9U ]; + config_reg->CONFIG_CHANCTRL[ 10U ] = vimREG->CHANCTRL[ 10U ]; + config_reg->CONFIG_CHANCTRL[ 11U ] = vimREG->CHANCTRL[ 11U ]; + config_reg->CONFIG_CHANCTRL[ 12U ] = vimREG->CHANCTRL[ 12U ]; + config_reg->CONFIG_CHANCTRL[ 13U ] = vimREG->CHANCTRL[ 13U ]; + config_reg->CONFIG_CHANCTRL[ 14U ] = vimREG->CHANCTRL[ 14U ]; + config_reg->CONFIG_CHANCTRL[ 15U ] = vimREG->CHANCTRL[ 15U ]; + config_reg->CONFIG_CHANCTRL[ 16U ] = vimREG->CHANCTRL[ 16U ]; + config_reg->CONFIG_CHANCTRL[ 17U ] = vimREG->CHANCTRL[ 17U ]; + config_reg->CONFIG_CHANCTRL[ 18U ] = vimREG->CHANCTRL[ 18U ]; + config_reg->CONFIG_CHANCTRL[ 19U ] = vimREG->CHANCTRL[ 19U ]; + config_reg->CONFIG_CHANCTRL[ 20U ] = vimREG->CHANCTRL[ 20U ]; + config_reg->CONFIG_CHANCTRL[ 21U ] = vimREG->CHANCTRL[ 21U ]; + config_reg->CONFIG_CHANCTRL[ 22U ] = vimREG->CHANCTRL[ 22U ]; + config_reg->CONFIG_CHANCTRL[ 23U ] = vimREG->CHANCTRL[ 23U ]; + } +} + +/* USER CODE BEGIN (10) */ +/* USER CODE END */ + +/* SourceId : VIM_SourceId_006 */ +/* DesignId : VIM_DesignId_006 */ +/* Requirements : CONQ_VIM_SR6 */ +void vimECCErrorHandler( void ) +{ + uint32 vec; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /* Identify the corrupted address */ + uint32 error_addr = vimREG->UERRADDR; + + /* Identify the channel number */ + uint32 error_channel = ( ( error_addr & 0x3FFU ) >> 2U ); + + /* Correct the corrupted location */ + vimRAM->ISR[ error_channel ] = s_vim_init[ error_channel ]; + + /* Clear Parity Error Flag */ + vimREG->ECCSTAT = 1U; + + /* Disable and enable the highest priority pending channel */ + if( vimREG->FIQINDEX != 0U ) + { + vec = vimREG->FIQINDEX - 1U; + } + else + { + /*SAFETYMCUSW 134 S MR:12.2 "Read 32 bit volatile register" */ + vec = vimREG->IRQINDEX - 1U; + } + if( vec == 0U ) + { + vimREG->INTREQ0 = 1U; + vec = esmREG->IOFFHR - 1U; + + if( vec < 32U ) + { + esmREG->SR1[ 0U ] = ( uint32 ) 1U << vec; + esmGroup1Notification( esmREG, vec ); + } + else if( vec < 64U ) + { + esmREG->SR1[ 1U ] = ( uint32 ) 1U << ( vec - 32U ); + esmGroup2Notification( esmREG, ( vec - 32U ) ); + } + else if( vec < 96U ) + { + esmREG->SR4[ 0U ] = ( uint32 ) 1U << ( vec - 64U ); + esmGroup1Notification( esmREG, ( vec - 32U ) ); + } + else if( ( vec >= 128U ) && ( vec < 160U ) ) + { + esmREG->SR7[ 0U ] = ( uint32 ) 1U << ( vec - 128U ); + esmGroup2Notification( esmREG, ( vec - 96U ) ); + } + else + { + esmREG->SR7[ 0U ] = 0xFFFFFFFFU; + esmREG->SR4[ 1U ] = 0xFFFFFFFFU; + esmREG->SR4[ 0U ] = 0xFFFFFFFFU; + esmREG->SR1[ 1U ] = 0xFFFFFFFFU; + esmREG->SR1[ 0U ] = 0xFFFFFFFFU; + } + } + else if( vec < 32U ) + { + vimREG->REQMASKCLR0 = ( uint32 ) 1U << vec; + vimREG->REQMASKSET0 = ( uint32 ) 1U << vec; + } + else if( vec < 64U ) + { + vimREG->REQMASKCLR1 = ( uint32 ) 1U << ( vec - 32U ); + vimREG->REQMASKSET1 = ( uint32 ) 1U << ( vec - 32U ); + } + else if( vec < 96U ) + { + vimREG->REQMASKCLR2 = ( uint32 ) 1U << ( vec - 64U ); + vimREG->REQMASKSET2 = ( uint32 ) 1U << ( vec - 64U ); + } + else + { + vimREG->REQMASKCLR3 = ( uint32 ) 1U << ( vec - 96U ); + vimREG->REQMASKSET3 = ( uint32 ) 1U << ( vec - 96U ); + } + /* USER CODE BEGIN (12) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (13) */ +/* USER CODE END */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c new file mode 100644 index 00000000000..c12435362e4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/BoardFiles/source/system.c @@ -0,0 +1,652 @@ +/** @file system.c + * @brief System Driver Source File + * @date 11-Dec-2018 + * @version 04.07.01 + * + * This file contains: + * - API Functions + * . + * which are relevant for the System driver. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +/* USER CODE BEGIN (0) */ +/* USER CODE END */ + +/* Include Files */ + +#include "system.h" +#include "reg_pcr.h" +#include "pinmux.h" + +#include "emif.h" + +/* USER CODE BEGIN (1) */ +/* USER CODE END */ + +/** @fn void systemInit(void) + * @brief Initializes System Driver + * + * This function initializes the System driver. + * + */ + +/* USER CODE BEGIN (2) */ +/* USER CODE END */ +/* SourceId : SYSTEM_SourceId_001 */ +/* DesignId : SYSTEM_DesignId_001 */ +/* Requirements : CONQ_SYSTEM_SR3 */ +void setupPLL( void ) +{ + /* USER CODE BEGIN (3) */ + /* USER CODE END */ + + /* Disable PLL1 and PLL2 */ + systemREG1->CSDISSET = 0x00000002U | 0x00000040U; + /*SAFETYMCUSW 28 D MR:NA "Hardware status bit read check" */ + while( ( systemREG1->CSDIS & 0x42U ) != 0x42U ) + { + /* Wait */ + } + + /* Clear Global Status Register */ + systemREG1->GBLSTAT = 0x301U; + + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /** - Setup pll control register 1: + * - Setup reset on oscillator slip + * - Setup bypass on pll slip + * - setup Pll output clock divider to max before Lock + * - Setup reset on oscillator fail + * - Setup reference clock divider + * - Setup Pll multiplier + */ + systemREG1->PLLCTL1 = ( uint32 ) 0x00000000U | ( uint32 ) 0x20000000U + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) | ( uint32 ) 0x00000000U + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) + | ( uint32 ) ( 0x9500U ); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider + * - Setup spreading amount + */ + systemREG1->PLLCTL2 = ( uint32 ) ( ( uint32 ) 255U << 22U ) + | ( uint32 ) ( ( uint32 ) 7U << 12U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 9U ) | ( uint32 ) 61U; + + /** @b Initialize @b Pll2: */ + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + systemREG2->PLLCTL3 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 29U ) + | ( uint32 ) ( ( uint32 ) 0x1FU << 24U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) << 16U ) + | ( uint32 ) ( 0x9500U ); + + /** - Enable PLL(s) to start up or Lock */ + systemREG1->CSDIS = 0x00000000U | 0x00000000U | 0x00000008U | 0x00000080U + | 0x00000000U | 0x00000000U | 0x00000000U | 0x00000004U; +} + +/** @fn void trimLPO(void) + * @brief Initialize LPO trim values + * + * Load TRIM values from OTP if present else call customTrimLPO() function + * + */ +/* SourceId : SYSTEM_SourceId_002 */ +/* DesignId : SYSTEM_DesignId_002 */ +/* Requirements : CONQ_SYSTEM_SR6 */ +void trimLPO( void ) +{ + uint32 u32clocktestConfig; + /* Save user clocktest register configuration */ + u32clocktestConfig = systemREG1->CLKTEST; + /* USER CODE BEGIN (4) */ + /* USER CODE END */ + /*The TRM states OTP TRIM value should be stepped to avoid large changes in the HF LPO + * clock that would result in a LPOCLKMON fault. At issue is the TRM does not specify + * what the maximum step is so there is no metric to use for the SW implementation - + * the routine can temporarily disable the LPOCLKMON range check so the sudden change + * will not cause a fault.*/ + /* Disable clock range detection*/ + + systemREG1->CLKTEST = ( systemREG1->CLKTEST | ( uint32 ) ( ( uint32 ) 0x1U << 24U ) ) + & ( uint32 ) ( ~( ( uint32 ) 0x1U << 25U ) ); + /*SAFETYMCUSW 139 S MR:13.7 "Hardware status bit read check" */ + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) LPO_TRIM_VALUE ); + } + else + { + customTrimLPO(); + } + + /* Restore the user clocktest register value configuration */ + systemREG1->CLKTEST = u32clocktestConfig; + + /* USER CODE BEGIN (5) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_003 */ +/* DesignId : SYSTEM_DesignId_003 */ +/* Requirements : CONQ_SYSTEM_SR5 */ +void setupFlash( void ) +{ + /* USER CODE BEGIN (6) */ + /* USER CODE END */ + + /** - Setup flash read mode, address wait states and data wait states */ + flashWREG->FRDCNTL = 0x00000000U | ( uint32 ) ( ( uint32 ) 3U << 8U ) | 3U; + + /** - Setup flash access wait states for bank 7 */ + FSM_WR_ENA_HL = 0x5U; + EEPROM_CONFIG_HL = 0x00000002U | ( uint32 ) ( ( uint32 ) 9U << 16U ); + + /* USER CODE BEGIN (7) */ + /* USER CODE END */ + + /** - Disable write access to flash state machine registers */ + FSM_WR_ENA_HL = 0x2U; + + /** - Setup flash bank power modes */ + flashWREG->FBPWRMODE = 0x00000000U + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 14U ) /* BANK 7 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 2U ) /* BANK 1 */ + | ( uint32 ) ( ( uint32 ) SYS_ACTIVE << 0U ); /* BANK 0 */ + + /* USER CODE BEGIN (8) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_004 */ +/* DesignId : SYSTEM_DesignId_004 */ +/* Requirements : CONQ_SYSTEM_SR4 */ +void periphInit( void ) +{ + /* USER CODE BEGIN (9) */ + /* USER CODE END */ + + /** - Disable Peripherals before peripheral powerup*/ + systemREG1->CLKCNTL &= 0xFFFFFEFFU; + + /** - Release peripherals from reset and enable clocks to all peripherals */ + /** - Power-up all peripherals */ + pcrREG1->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG1->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + pcrREG2->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG2->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + pcrREG3->PSPWRDWNCLR0 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR1 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR2 = 0xFFFFFFFFU; + pcrREG3->PSPWRDWNCLR3 = 0xFFFFFFFFU; + + /** - Enable Peripherals */ + systemREG1->CLKCNTL |= 0x00000100U; + + /* USER CODE BEGIN (10) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : CONQ_SYSTEM_SR7 */ +void mapClocks( void ) +{ + uint32 SYS_CSVSTAT, SYS_CSDIS; + + /* USER CODE BEGIN (11) */ + /* USER CODE END */ + + /** @b Initialize @b Clock @b Tree: */ + /** - Setup system clock divider for HCLK */ + systemREG2->HCLKCNTL = 1U; + + /** - Disable / Enable clock domain */ + systemREG1->CDDIS = ( uint32 ) ( ( uint32 ) 0U << 4U ) /* AVCLK1 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 1U << 5U ) /* AVCLK2 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 8U ) /* VCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 9U ) /* VCLK4 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 10U ) /* AVCLK3 , 1 - OFF, 0 - ON */ + | ( uint32 ) ( ( uint32 ) 0U << 11U ); /* AVCLK4 , 1 - OFF, 0 - ON + */ + + /* Always check the CSDIS register to make sure the clock source is turned on and + * check the CSVSTAT register to make sure the clock source is valid. Then write to + * GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + while( ( SYS_CSVSTAT & ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + != ( ( SYS_CSDIS ^ 0xFFU ) & 0xFFU ) ) + { + SYS_CSVSTAT = systemREG1->CSVSTAT; + SYS_CSDIS = systemREG1->CSDIS; + } /* Wait */ + + /* USER CODE BEGIN (12) */ + /* USER CODE END */ + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and + * after wakeup */ + systemREG1->GHVSRC = ( uint32 ) ( ( uint32 ) SYS_PLL1 << 24U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 16U ) + | ( uint32 ) ( ( uint32 ) SYS_PLL1 << 0U ); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + systemREG1->RCLKSRC = ( uint32 ) ( ( uint32 ) 1U << 24U ) /* RTI2 divider (Not + applicable for lock-step + device) */ + | ( uint32 ) ( ( uint32 ) SYS_VCLK + << 16U ) /* RTI2 clock source (Not applicable + for lock-step device) */ + | ( uint32 ) ( ( uint32 ) 1U << 8U ) /* RTI1 divider */ + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); /* RTI1 clock source + */ + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + systemREG1->VCLKASRC = ( uint32 ) ( ( uint32 ) SYS_VCLK << 8U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xF0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 24U ); + systemREG1->CLKCNTL = ( systemREG1->CLKCNTL & 0xFFF0FFFFU ) + | ( uint32 ) ( ( uint32 ) 1U << 16U ); + + systemREG2->CLK2CNTRL = ( systemREG2->CLK2CNTRL & 0xFFFFFFF0U ) + | ( uint32 ) ( ( uint32 ) 1U << 0U ); + + systemREG2->VCLKACON1 = ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 20U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 16U ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 8U ) + | ( uint32 ) ( ( uint32 ) 0U << 4U ) + | ( uint32 ) ( ( uint32 ) SYS_VCLK << 0U ); + + /* USER CODE BEGIN (13) */ + /* USER CODE END */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed + * value */ + systemREG1->PLLCTL1 = ( systemREG1->PLLCTL1 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + /*SAFETYMCUSW 134 S MR:12.2 " Clear and write to the volatile register " */ + systemREG2->PLLCTL3 = ( systemREG2->PLLCTL3 & 0xE0FFFFFFU ) + | ( uint32 ) ( ( uint32 ) ( 1U - 1U ) << 24U ); + + /* Enable/Disable Frequency modulation */ + systemREG1->PLLCTL2 |= 0x00000000U; + + /* USER CODE BEGIN (14) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_006 */ +/* DesignId : SYSTEM_DesignId_006 */ +/* Requirements : CONQ_SYSTEM_SR2 */ +void systemInit( void ) +{ + /* USER CODE BEGIN (15) */ + /* USER CODE END */ + + /* Configure PLL control registers and enable PLLs. + * The PLL takes (127 + 1024 * NR) oscillator cycles to acquire lock. + * This initialization sequence performs all the tasks that are not + * required to be done at full application speed while the PLL locks. + */ + setupPLL(); + + /* USER CODE BEGIN (16) */ + /* USER CODE END */ + + /* Enable clocks to peripherals and release peripheral reset */ + periphInit(); + + /* USER CODE BEGIN (17) */ + /* USER CODE END */ + + /* Configure device-level multiplexing and I/O multiplexing */ + muxInit(); + + /* USER CODE BEGIN (18) */ + /* USER CODE END */ + + /** - Set up flash address and data wait states based on the target CPU clock + * frequency The number of address and data wait states for the target CPU clock + * frequency are specified in the specific part's datasheet. + */ + setupFlash(); + + /* USER CODE BEGIN (19) */ + /* USER CODE END */ + + /** - Configure the LPO such that HF LPO is as close to 10MHz as possible */ + trimLPO(); + + /* + * As per the errata EMIF#5, EMIF SDRAM initialization must performed with EMIF + * clock below 40MHz. Hence the init function needs to be called from the startup + * before the PLL is configured. + */ + emif_SDRAM_StartupInit(); + + /* USER CODE BEGIN (20) */ + /* USER CODE END */ + + /** - Wait for PLLs to start up and map clock domains to desired clock sources */ + mapClocks(); + + /* USER CODE BEGIN (21) */ + /* USER CODE END */ + + /** - set ECLK pins functional mode */ + systemREG1->SYSPC1 = 0U; + + /** - set ECLK pins default output value */ + systemREG1->SYSPC4 = 0U; + + /** - set ECLK pins output direction */ + systemREG1->SYSPC2 = 1U; + + /** - set ECLK pins open drain enable */ + systemREG1->SYSPC7 = 0U; + + /** - set ECLK pins pullup/pulldown enable */ + systemREG1->SYSPC8 = 0U; + + /** - set ECLK pins pullup/pulldown select */ + systemREG1->SYSPC9 = 1U; + + /** - Setup ECLK */ + systemREG1->ECPCNTL = ( uint32 ) ( ( uint32 ) 0U << 24U ) + | ( uint32 ) ( ( uint32 ) 0U << 23U ) + | ( uint32 ) ( ( uint32 ) ( 8U - 1U ) & 0xFFFFU ); + + /* USER CODE BEGIN (22) */ + /* USER CODE END */ +} + +/* SourceId : SYSTEM_SourceId_007 */ +/* DesignId : SYSTEM_DesignId_007 */ +/* Requirements : CONQ_SYSTEM_SR8 */ +void systemPowerDown( uint32 mode ) +{ + /* USER CODE BEGIN (23) */ + /* USER CODE END */ + + /* Disable clock sources */ + systemREG1->CSDISSET = mode & 0x000000FFU; + + /* Disable clock domains */ + systemREG1->CDDIS = ( mode >> 8U ) & 0x00000FFFU; + + /* Idle CPU */ + /*SAFETYMCUSW 88 S MR:2.1 "Assembly in C needed" */ + _gotoCPUIdle_(); + + /* USER CODE BEGIN (24) */ + /* USER CODE END */ +} + +/* USER CODE BEGIN (25) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_008 */ +/* DesignId : SYSTEM_DesignId_008 */ +/* Requirements : CONQ_SYSTEM_SR9 */ +resetSource_t getResetSource( void ) +{ + register resetSource_t rst_source; + + if( ( SYS_EXCEPTION & ( uint32 ) POWERON_RESET ) != 0U ) + { + /* power-on reset condition */ + rst_source = POWERON_RESET; + /* Clear all exception status Flag and proceed since it's power up */ + SYS_EXCEPTION = 0x0000FFFFU; + } + + else if( ( SYS_EXCEPTION & ( uint32 ) EXT_RESET ) != 0U ) + { + SYS_EXCEPTION = ( uint32 ) EXT_RESET; + /*** Check for other causes of EXT_RESET that would take precedence **/ + if( ( SYS_EXCEPTION & ( uint32 ) OSC_FAILURE_RESET ) != 0U ) + { + /* Reset caused due to oscillator failure. Add user code here to handle + * oscillator failure */ + rst_source = OSC_FAILURE_RESET; + SYS_EXCEPTION = ( uint32 ) OSC_FAILURE_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) WATCHDOG_RESET ) != 0U ) + { + /* Reset caused due watchdog violation */ + rst_source = WATCHDOG_RESET; + SYS_EXCEPTION = ( uint32 ) WATCHDOG_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) WATCHDOG2_RESET ) != 0U ) + { + /* Reset caused due watchdog violation */ + rst_source = WATCHDOG2_RESET; + SYS_EXCEPTION = ( uint32 ) WATCHDOG2_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) SW_RESET ) != 0U ) + { + /* Reset caused due to software reset. */ + rst_source = SW_RESET; + SYS_EXCEPTION = ( uint32 ) SW_RESET; + } + else + { + /* Reset caused due to External reset. */ + rst_source = EXT_RESET; + } + } + else if( ( SYS_EXCEPTION & ( uint32 ) DEBUG_RESET ) != 0U ) + { + /* Reset caused due Debug reset request */ + rst_source = DEBUG_RESET; + SYS_EXCEPTION = ( uint32 ) DEBUG_RESET; + } + else if( ( SYS_EXCEPTION & ( uint32 ) CPU0_RESET ) != 0U ) + { + /* Reset caused due to CPU0 reset. CPU reset can be caused by CPU self-test + * completion, or by toggling the "CPU RESET" bit of the CPU Reset Control + * Register. */ + rst_source = CPU0_RESET; + SYS_EXCEPTION = ( uint32 ) CPU0_RESET; + } + else + { + /* No_reset occured. */ + rst_source = NO_RESET; + } + return rst_source; +} + +/* USER CODE BEGIN (26) */ +/* USER CODE END */ + +/* SourceId : SYSTEM_SourceId_009 */ +/* DesignId : SYSTEM_DesignId_009 */ +/* Requirements : CONQ_SYSTEM_SR10 */ +/** @fn void systemGetConfigValue(system_config_reg_t *config_reg, config_value_type_t + * type) + * @brief Get the initial or current values of the configuration registers + * + * @param[in] *config_reg: pointer to the struct to which the initial or current + * value of the configuration registers need to be stored + * @param[in] type: whether initial or current value of the configuration registers + * need to be stored + * - InitialValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * - CurrentValue: initial value of the configuration registers + * will be stored in the struct pointed by config_reg + * + * This function will copy the initial or current value (depending on the parameter + * 'type') of the configuration registers to the struct pointed by config_reg + */ +void systemGetConfigValue( system_config_reg_t * config_reg, config_value_type_t type ) +{ + if( type == InitialValue ) + { + config_reg->CONFIG_SYSPC1 = SYS_SYSPC1_CONFIGVALUE; + config_reg->CONFIG_SYSPC2 = SYS_SYSPC2_CONFIGVALUE; + config_reg->CONFIG_SYSPC7 = SYS_SYSPC7_CONFIGVALUE; + config_reg->CONFIG_SYSPC8 = SYS_SYSPC8_CONFIGVALUE; + config_reg->CONFIG_SYSPC9 = SYS_SYSPC9_CONFIGVALUE; + config_reg->CONFIG_CSDIS = SYS_CSDIS_CONFIGVALUE; + config_reg->CONFIG_CDDIS = SYS_CDDIS_CONFIGVALUE; + config_reg->CONFIG_GHVSRC = SYS_GHVSRC_CONFIGVALUE; + config_reg->CONFIG_VCLKASRC = SYS_VCLKASRC_CONFIGVALUE; + config_reg->CONFIG_RCLKSRC = SYS_RCLKSRC_CONFIGVALUE; + config_reg->CONFIG_MSTGCR = SYS_MSTGCR_CONFIGVALUE; + config_reg->CONFIG_MINITGCR = SYS_MINITGCR_CONFIGVALUE; + config_reg->CONFIG_MSINENA = SYS_MSINENA_CONFIGVALUE; + config_reg->CONFIG_PLLCTL1 = SYS_PLLCTL1_CONFIGVALUE_2; + config_reg->CONFIG_PLLCTL2 = SYS_PLLCTL2_CONFIGVALUE; + config_reg->CONFIG_SYSPC10 = SYS_SYSPC10_CONFIGVALUE; + if( LPO_TRIM_VALUE != 0xFFFFU ) + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_1; + } + else + { + config_reg->CONFIG_LPOMONCTL = SYS_LPOMONCTL_CONFIGVALUE_2; + } + config_reg->CONFIG_CLKTEST = SYS_CLKTEST_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG1 = SYS_DFTCTRLREG1_CONFIGVALUE; + config_reg->CONFIG_DFTCTRLREG2 = SYS_DFTCTRLREG2_CONFIGVALUE; + config_reg->CONFIG_GPREG1 = SYS_GPREG1_CONFIGVALUE; + config_reg->CONFIG_RAMGCR = SYS_RAMGCR_CONFIGVALUE; + config_reg->CONFIG_BMMCR1 = SYS_BMMCR1_CONFIGVALUE; + config_reg->CONFIG_CLKCNTL = SYS_CLKCNTL_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL = SYS_ECPCNTL_CONFIGVALUE; + config_reg->CONFIG_DEVCR1 = SYS_DEVCR1_CONFIGVALUE; + config_reg->CONFIG_SYSECR = SYS_SYSECR_CONFIGVALUE; + config_reg->CONFIG_PLLCTL3 = SYS2_PLLCTL3_CONFIGVALUE_2; + config_reg->CONFIG_STCCLKDIV = SYS2_STCCLKDIV_CONFIGVALUE; + config_reg->CONFIG_ECPCNTL1 = SYS2_ECPCNTL1_CONFIGVALUE; + config_reg->CONFIG_CLK2CNTRL = SYS2_CLK2CNTRL_CONFIGVALUE; + config_reg->CONFIG_VCLKACON1 = SYS2_VCLKACON1_CONFIGVALUE; + config_reg->CONFIG_HCLKCNTL = SYS2_HCLKCNTL_CONFIGVALUE; + config_reg->CONFIG_CLKSLIP = SYS2_CLKSLIP_CONFIGVALUE; + config_reg->CONFIG_EFC_CTLEN = SYS2_EFC_CTLEN_CONFIGVALUE; + } + else + { + config_reg->CONFIG_SYSPC1 = systemREG1->SYSPC1; + config_reg->CONFIG_SYSPC2 = systemREG1->SYSPC2; + config_reg->CONFIG_SYSPC7 = systemREG1->SYSPC7; + config_reg->CONFIG_SYSPC8 = systemREG1->SYSPC8; + config_reg->CONFIG_SYSPC9 = systemREG1->SYSPC9; + config_reg->CONFIG_CSDIS = systemREG1->CSDIS; + config_reg->CONFIG_CDDIS = systemREG1->CDDIS; + config_reg->CONFIG_GHVSRC = systemREG1->GHVSRC; + config_reg->CONFIG_VCLKASRC = systemREG1->VCLKASRC; + config_reg->CONFIG_RCLKSRC = systemREG1->RCLKSRC; + config_reg->CONFIG_MSTGCR = systemREG1->MSTGCR; + config_reg->CONFIG_MINITGCR = systemREG1->MINITGCR; + config_reg->CONFIG_MSINENA = systemREG1->MSINENA; + config_reg->CONFIG_PLLCTL1 = systemREG1->PLLCTL1; + config_reg->CONFIG_PLLCTL2 = systemREG1->PLLCTL2; + config_reg->CONFIG_SYSPC10 = systemREG1->SYSPC10; + config_reg->CONFIG_LPOMONCTL = systemREG1->LPOMONCTL; + config_reg->CONFIG_CLKTEST = systemREG1->CLKTEST; + config_reg->CONFIG_DFTCTRLREG1 = systemREG1->DFTCTRLREG1; + config_reg->CONFIG_DFTCTRLREG2 = systemREG1->DFTCTRLREG2; + config_reg->CONFIG_GPREG1 = systemREG1->GPREG1; + config_reg->CONFIG_RAMGCR = systemREG1->RAMGCR; + config_reg->CONFIG_BMMCR1 = systemREG1->BMMCR1; + config_reg->CONFIG_CLKCNTL = systemREG1->CLKCNTL; + config_reg->CONFIG_ECPCNTL = systemREG1->ECPCNTL; + config_reg->CONFIG_DEVCR1 = systemREG1->DEVCR1; + config_reg->CONFIG_SYSECR = systemREG1->SYSECR; + config_reg->CONFIG_PLLCTL3 = systemREG2->PLLCTL3; + config_reg->CONFIG_STCCLKDIV = systemREG2->STCCLKDIV; + config_reg->CONFIG_ECPCNTL1 = systemREG2->ECPCNTL1; + config_reg->CONFIG_CLK2CNTRL = systemREG2->CLK2CNTRL; + config_reg->CONFIG_VCLKACON1 = systemREG2->VCLKACON1; + config_reg->CONFIG_HCLKCNTL = systemREG2->HCLKCNTL; + config_reg->CONFIG_CLKSLIP = systemREG2->CLKSLIP; + config_reg->CONFIG_EFC_CTLEN = systemREG2->EFC_CTLEN; + } +} + +/** @fn customTrimLPO(void) + * @brief custom function to initilize LPO trim values + * + * This function initializes default LPO trim values if OTP value is 0XFFFF, + * user can also write their own code to handle this case . + * + */ +void customTrimLPO( void ) +{ + /* User can write logic to handle the case where LPO trim is set to 0xFFFFu */ + /* USER CODE BEGIN (27) */ + /* USER CODE END */ + + /* Load default trimLPO value */ + systemREG1->LPOMONCTL = ( uint32 ) ( ( uint32 ) 1U << 24U ) + | ( uint32 ) ( ( uint32 ) 16U << 8U ) + | ( uint32 ) ( ( uint32 ) 16U ); + + /* USER CODE BEGIN (28) */ + /* USER CODE END */ +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt new file mode 100644 index 00000000000..6cc77d74ad2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/CMakeLists.txt @@ -0,0 +1,204 @@ +cmake_minimum_required(VERSION 3.22) + +SET(CMAKE_CROSSCOMPILING "TRUE" CACHE STRING "Set Cross Compiling to true" FORCE) + +# Strip the default MacOSX flags that cause cross-compilations to fail. +SET(CMAKE_OSX_DEPLOYMENT_TARGET "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) +SET(CMAKE_OSX_SYSROOT "" CACHE STRING "Force unset of the deployment target for iOS" FORCE) + +# Set the compiler before declaring the project for the test build +SET(CMAKE_C_COMPILER "arm-none-eabi-gcc") +SET(CMAKE_ASM_COMPILER "arm-none-eabi-gcc") + +# Set the system processor and name before declaring the project +# Needs to be set here otherwise it will fail the test compilation +SET(CMAKE_SYSTEM_NAME "Generic" CACHE STRING "Target system is a generic ARM Processor") +SET(CMAKE_SYSTEM_PROCESSOR "armv7-r" CACHE STRING "Target system is an ARM7r Processor") + +# Set the ASM and C compilation flags +SET(CMAKE_ASM_FLAGS "-mcpu=cortex-r5 -mfpu=vfpv3-d16 -Og -g -ggdb -Wall -MMD -MP") +SET(CMAKE_ASM_FLAGS "${CMAKE_ASM_FLAGS} -specs=\"nosys.specs\" -specs=\"nano.specs\"") +SET(CMAKE_C_FLAGS "${CMAKE_ASM_FLAGS} -marm -mfloat-abi=hard") + +project(RM57_FreeRTOS C ASM) + +SET(EXECUTABLE_OUTPUT_PATH ${PROJECT_BINARY_DIR} CACHE STRING "") + +# Increase the debug level of the CMAKE build +SET(CMAKE_VERBOSE_MAKEFILE ON) + +# Get the absolute path to the Demo Directory +SET(DEMO_DIR_REL "${CMAKE_CURRENT_SOURCE_DIR}") +GET_FILENAME_COMPONENT(DEMO_DIR ${DEMO_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Board Files +SET(BOARD_FILES_DIR_REL "${DEMO_DIR}/BoardFiles") +GET_FILENAME_COMPONENT(BOARD_FILES_DIR ${BOARD_FILES_DIR_REL} ABSOLUTE) + +SET(FREERTOS_CONFIG_FILE_DIRECTORY "${DEMO_DIR}/include" CACHE STRING "Config File Path") +SET(FREERTOS_PORT "GCC_ARM_CRx_No_GIC" CACHE STRING "FreeRTOS Port to Use") + +ADD_LIBRARY(freertos_config INTERFACE) +TARGET_INCLUDE_DIRECTORIES(freertos_config SYSTEM + INTERFACE + INCLUDE ${FREERTOS_CONFIG_FILE_DIRECTORY} +) + +# Clone the tag of the FreeRTOS-Kernel last tested with this project. +INCLUDE(FetchContent) + +FetchContent_Declare( + FreeRTOS-Kernel + GIT_REPOSITORY https://github.com/FreeRTOS/FreeRTOS-Kernel.git + # Last tested FreeRTOS-Kernel Commit + GIT_TAG main + SOURCE_DIR "${DEMO_DIR}/../../Source" + USES_TERMINAL_DOWNLOAD YES + USES_TERMINAL_UPDATE YES + BUILD_COMMAND "" +) + +# Uncomment the following lines to use Fetch-Content to clone Kernel. +# FetchContent_GetProperties(FreeRTOS-Kernel) +# if(NOT FreeRTOS-Kernel_POPULATED) +# FetchContent_Populate(FreeRTOS-Kernel) +# endif() + + +# Get the absolute path to the FreeRTOS-Kernel Directory +SET(FREERTOS_KERNEL_DIR_REL "${DEMO_DIR}/../../Source") +GET_FILENAME_COMPONENT(FREERTOS_KERNEL_DIR ${FREERTOS_KERNEL_DIR_REL} ABSOLUTE) + +# Get the absolute path to the Port Directory +SET(PORT_DIR_REL "${FREERTOS_KERNEL_DIR}/portable/GCC/ARM_CRx_No_GIC") +GET_FILENAME_COMPONENT(PORT_DIR ${PORT_DIR_REL} ABSOLUTE) + +# Debug +MESSAGE("Project: ${PROJECT_NAME}") +MESSAGE("Demo Directory: ${DEMO_DIR}") +MESSAGE("FREERTOS_KERNEL_DIR: ${FREERTOS_KERNEL_DIR}") +MESSAGE("PORT_DIR: ${PORT_DIR}") + +INCLUDE_DIRECTORIES( + ${DEMO_DIR} + ${DEMO_DIR}/include + ${BOARD_FILES_DIR}/include + ${FREERTOS_KERNEL_DIR}/include + ${PORT_DIR} +) + +# Source files used for the FreeRTOS Demos +SET(FREERTOS_DEMO_SOURCES + ${DEMO_DIR}/source/main.c + ${DEMO_DIR}/source/irq_demo.c + ${DEMO_DIR}/source/notification_demo.c + ${DEMO_DIR}/source/queue_demo.c + ${DEMO_DIR}/source/reg_test.c + ${DEMO_DIR}/source/reg_test_GCC.S +) + +# Source files used for the Board Support Package +ADD_LIBRARY(TI_BOARD_SUPPORT_PACKAGE OBJECT + ${BOARD_FILES_DIR}/source/adc.c + ${BOARD_FILES_DIR}/source/can.c + ${BOARD_FILES_DIR}/source/crc.c + ${BOARD_FILES_DIR}/source/dabort.S + ${BOARD_FILES_DIR}/source/dcc.c + ${BOARD_FILES_DIR}/source/ecap.c + ${BOARD_FILES_DIR}/source/emac.c + ${BOARD_FILES_DIR}/source/emif.c + ${BOARD_FILES_DIR}/source/epc.c + ${BOARD_FILES_DIR}/source/eqep.c + ${BOARD_FILES_DIR}/source/errata.c + ${BOARD_FILES_DIR}/source/errata_SSWF021_45.c + ${BOARD_FILES_DIR}/source/esm.c + ${BOARD_FILES_DIR}/source/etpwm.c + ${BOARD_FILES_DIR}/source/gio.c + ${BOARD_FILES_DIR}/source/het.c + ${BOARD_FILES_DIR}/source/i2c.c + ${BOARD_FILES_DIR}/source/lin.c + ${BOARD_FILES_DIR}/source/mdio.c + ${BOARD_FILES_DIR}/source/mibspi.c + ${BOARD_FILES_DIR}/source/nmpu.c + ${BOARD_FILES_DIR}/source/notification.c + ${BOARD_FILES_DIR}/source/phy_dp83640.c + ${BOARD_FILES_DIR}/source/phy_tlk111.c + ${BOARD_FILES_DIR}/source/pinmux.c + ${BOARD_FILES_DIR}/source/pom.c + ${BOARD_FILES_DIR}/source/sci.c + ${BOARD_FILES_DIR}/source/sys_core.S + ${BOARD_FILES_DIR}/source/sys_dma.c + ${BOARD_FILES_DIR}/source/sys_intvecs.S + ${BOARD_FILES_DIR}/source/sys_link.ld + ${BOARD_FILES_DIR}/source/sys_pcr.c + ${BOARD_FILES_DIR}/source/sys_phantom.c + ${BOARD_FILES_DIR}/source/sys_pmm.c + ${BOARD_FILES_DIR}/source/sys_pmu.S + ${BOARD_FILES_DIR}/source/sys_startup.c + ${BOARD_FILES_DIR}/source/system.c + ${BOARD_FILES_DIR}/source/sys_vim.c +) + +# FreeRTOS Kernel Files +ADD_LIBRARY(FREERTOS_KERNEL OBJECT + ${FREERTOS_KERNEL_DIR}/croutine.c + ${FREERTOS_KERNEL_DIR}/event_groups.c + ${FREERTOS_KERNEL_DIR}/list.c + ${FREERTOS_KERNEL_DIR}/queue.c + ${FREERTOS_KERNEL_DIR}/stream_buffer.c + ${FREERTOS_KERNEL_DIR}/tasks.c + ${FREERTOS_KERNEL_DIR}/timers.c +) + +ADD_LIBRARY(FREERTOS_PORT OBJECT + ${PORT_DIR}/portASM.S + ${PORT_DIR}/port.c +) + +# On Mac the C_LINK flags by default adds "-Wl,-search_paths_first -Wl,-headerpad_max_install_names" which +# Causes the executable that gets built to strip the symbols, so force set it to empty here. +SET(CMAKE_C_LINK_FLAGS "") +SET(CMAKE_EXE_LINKER_FLAGS "-Wl,-Map,\"RTOSDemo.map\" -Wl,-T\"${BOARD_FILES_DIR}/source/sys_link.ld\"") + +# Debug +MESSAGE("Demo Sources: ${FREERTOS_DEMO_SOURCES}") +MESSAGE("FreeRTOS Sources: ${FREERTOS_KERNEL_SOURCES}") +MESSAGE("Port Sources: ${FREERTOS_PORT_SOURCES}") + +# Create Full Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Full.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Register Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Register_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Queue Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Queue_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create IRQ Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_IRQ_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# Create Notification Demo executable +ADD_EXECUTABLE(RM57_FreeRTOS_Notification_Demo.out + ${FREERTOS_DEMO_SOURCES} +) + +# These options are explained in the demo_tasks.h file +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Full.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x0F") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Register_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x1") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Queue_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x2") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_IRQ_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x4") +SET_TARGET_PROPERTIES(RM57_FreeRTOS_Notification_Demo.out PROPERTIES COMPILE_DEFINITIONS "mainDEMO_TYPE=0x8") + +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Full.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Register_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Queue_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_IRQ_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) +TARGET_LINK_LIBRARIES(RM57_FreeRTOS_Notification_Demo.out FREERTOS_PORT FREERTOS_KERNEL TI_BOARD_SUPPORT_PACKAGE ) diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/README.md b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/README.md new file mode 100644 index 00000000000..b4e6919ffd9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/README.md @@ -0,0 +1,67 @@ +# Intro + +This directory contains a FreeRTOS project to build a set of demos for the +[RM57L843](https://www.ti.com/product/RM57L843) board. The demos to build are +selected using the macro `mainDEMO_TYPE` in the `include/demo_tasks.h` file. + +It is set up to blink LEDs on the Texas Instruments +[LAUNCHXL2-RM57L](https://www.ti.com/tool/LAUNCHXL2-RM57L) +and the [TMDXRM57LHDK](https://www.ti.com/tool/TMDXRM57LHDK) Development Kits. + +The code related to the Main Demo Files can be found in the +[source](./source) directory. +The code related to the board setup can be found in the +[BoardFiles](./BoardFiles) directory. + +## Building + +This demo can either be loaded into Texas Instrument's +[Code Composer Studio (CCS)](https://www.ti.com/tool/CCSTUDIO). +or built using [CMake](https://cmake.org/). + +### CCS Build + +If building with CCS you need to install CCS, and then install the +[ARM Compiler Tools](https://software-dl.ti.com/ccs/esd/documents/ccs_compiler-installation-selection.html#compiler-installation) +as well as the Hercules Safety MCUs +[device support targets](https://software-dl.ti.com/ccs/esd/documents/users_guide/ccs_installation.html#device-support). + +After doing this, you can then open this directory in CCS, which will load up the +project. If everything installed correctly you should then be able to build and flash +to the board. + +Please be aware there is a filter on [CMakeLists.txt](./CMakeLists.txt) and the *build* +directory in the CCS project. + +This is to keep CCS from attempting to use resources generated with a CMAKE build. +If a directory other than "build" is selected when building using CMAKE, CCS will +attempt to use the the files in that directory, leading to build issues in CCS. +At time of writing this can be fixed by right clicking the folder in CCS +and selecting "Exclude from build". + +### CMake build + +When using CMake you will need to install a compatible version of the +[Arm GNU Toolchain](https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain) +and add this to your `PATH`. + +After doing this inspect the [demo_task.h](./include/demo_tasks.h#L30) file to see +what the possible demo configurations are, and select your desired demo config. + +The `all` options builds all combinations of these. +Example Usage: + +```sh +cmake -S . -B build; +make -C build all; +``` + +The generated binaries can then be found in the `build` directory. +These binaries can then be flashed to the board by using +[Uniflash](https://www.ti.com/tool/UNIFLASH) or by using CCS. + +## UART Output + +Rudimentary UART output is available by opening a Serial Connection +to the board. The settings for the UART are a BAUD rate of 115200, 1 stopbit, +and None Parity. diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h new file mode 100644 index 00000000000..acef1b15ed2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/FreeRTOSConfig.h @@ -0,0 +1,170 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Section of the file that can't be included in ASM Pre-processor */ +#ifndef FREERTOS_ASSEMBLY + #include + #ifndef configASSERT + +/* debug ASSERT The first option calls a function that prints to UART + * The second one loops for when using a debugger. */ +extern void vAssertCalled( const char * pcFileName, uint32_t ulLine ); + #define configASSERT( x ) \ + if( ( x ) == pdFALSE ) \ + { \ + vAssertCalled( __func__, __LINE__ ); \ + } + +extern void vMainSetupTimerInterrupt( void ); + #define configCLEAR_TICK_INTERRUPT() + #define configSETUP_TICK_INTERRUPT() vMainSetupTimerInterrupt() + #endif /* configASSERT */ +#endif /* FREERTOS_ASSEMBLY */ + +#ifndef FREERTOS_CONFIG_H + #define FREERTOS_CONFIG_H + + /*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + + /** Code Composer Studio will throw errors about NULL not being defined. + * as such wrap a define for NULL to 0 to remove the errors. + */ + #ifndef NULL + #define NULL 0x0 + #endif + + #define configNUMBER_OF_CORES 1U + #define configUSE_PREEMPTION 1U + #define configUSE_IDLE_HOOK 1U + #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 + #define configUSE_TICK_HOOK 0 + #define configMAX_PRIORITIES ( 30UL ) + #define configQUEUE_REGISTRY_SIZE 10U + #define configSUPPORT_STATIC_ALLOCATION 1U + #define configSUPPORT_DYNAMIC_ALLOCATION 0U + #define configUSE_TASK_FPU_SUPPORT 2U + + #define configCPU_CLOCK_HZ ( 110000000U ) + #define configTICK_RATE_HZ ( 1000U ) + #define configMINIMAL_STACK_SIZE ( 0x80 ) + #define configSYSTEM_CALL_STACK_SIZE configMINIMAL_STACK_SIZE + #define configTOTAL_HEAP_SIZE ( ( 80 * 512 ) ) + #define configMAX_TASK_NAME_LEN ( 0x20U ) + #define configUSE_TRACE_FACILITY 0U + #define configUSE_16_BIT_TICKS 0 + #define configIDLE_SHOULD_YIELD 0 + #define configUSE_CO_ROUTINES 0 + #define configUSE_MUTEXES 1U + #define configUSE_RECURSIVE_MUTEXES 1U + #define configUSE_EVENT_GROUPS 0U + #define configCHECK_FOR_STACK_OVERFLOW 0 + #define configUSE_QUEUE_SETS 1U + #define configUSE_COUNTING_SEMAPHORES 1U + #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1U + #define configUSE_POSIX_ERRNO 0 + #define configUSE_TIME_SLICING 0 + #define configUSE_C_RUNTIME_TLS_SUPPORT 0 + #define configUSE_NEWLIB_REENTRANT 0 + #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 + #define configUSE_MALLOC_FAILED_HOOK 0 + #define configHEAP_CLEAR_MEMORY_ON_FREE 0 + #define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + #define configAPPLICATION_ALLOCATED_HEAP 0 + #define configUSE_SB_COMPLETED_CALLBACK 0 + #define configRUN_MULTIPLE_PRIORITIES 0 + #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 + #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING 0 + #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 + #define configUSE_MINI_LIST_ITEM 0 + #define configPROTECTED_KERNEL_OBJECT_POOL_SIZE 0x20UL + + /* Timer related defines. */ + #define configUSE_TIMERS 1 + #define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 6UL ) + #define configTIMER_QUEUE_LENGTH 20 + #define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + #define INCLUDE_xTimerGetTimerDaemonTaskHandle 1 + #define INCLUDE_xTimerPendFunctionCall 1 + + /* Task Notification defines. */ + #define configUSE_TASK_NOTIFICATIONS 1 + #define configTASK_NOTIFICATION_ARRAY_ENTRIES 3 + +/* Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. */ + + #define INCLUDE_vTaskPrioritySet 1 + #define INCLUDE_uxTaskPriorityGet 1 + #define INCLUDE_vTaskDelete 1 + #define INCLUDE_vTaskCleanUpResources 0 + #define INCLUDE_vTaskSuspend 1 + #define INCLUDE_xTaskDelayUntil 1 + #define INCLUDE_vTaskDelay 1 + #define INCLUDE_uxTaskGetStackHighWaterMark 1 + #define INCLUDE_xTaskGetSchedulerState 1 + #define INCLUDE_xTaskGetIdleTaskHandle 1 + #define INCLUDE_xSemaphoreGetMutexHolder 1 + #define INCLUDE_eTaskGetState 1 + #define INCLUDE_xTaskAbortDelay 1 + #define INCLUDE_xTaskGetHandle 1 + + /** Note: These value come from the Board Support Package. They are pulled directly + * from sys_vim.h, and reg_vim.h. These values correspond to hardware registers + * and keys exclusive to the board that this demo was written for. + */ + + /** @brief Address of MCU Register used to mark the end of an IRQ */ + #define configEOI_ADDRESS 0xFFFFFE70UL + + /** @brief Address of Real Time Interrupt (RTI) used for the system clock */ + #define configRTI_ADDRESS 0xFFFFFC88UL + + /** @brief Value used to clear a RTI Interrupt */ + #define configRTI_CLEAR_VALUE 0x1 + + /** @brief Address of Register used to trigger Software Interrupts (SWI) */ + #define configSWI_ADDRESS 0xFFFFFFB0UL + + /** @brief Key value that is written to the SWI Interrupt Register */ + #define configSWI_KEY_VAL 0x7500UL + + /** @brief Address of Register used to clear SWI Interrupts */ + #define configSWI_CLEAR_ADDRESS 0xFFFFFFF4UL + + /** @brief Value to write to clear a Software Interrupt (SWI) */ + #define configSWI_CLEAR_VAL 0x0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h new file mode 100644 index 00000000000..abf24267bab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/include/demo_tasks.h @@ -0,0 +1,181 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef DEMO_TASKS_H +#define DEMO_TASKS_H + +/* ----------------------------------- Demo Option ----------------------------------- */ + +/** @brief Create Tasks that are written in assembly to test context swaps */ +#define REGISTER_DEMO 0x1 + +/** @brief Demo that uses timers, timer callbacks, and Queues */ +#define QUEUE_DEMO 0x2 + +/** @brief Demo that causes and unwinds a Nested IRQ */ +#define IRQ_DEMO 0x4 + +/** @brief Demo that uses the Task Notification APIs */ +#define NOTIFICATION_DEMO 0x8 + +/** @brief Build Register, Queue, IRQ, and Notification demos */ +#define FULL_DEMO ( REGISTER_DEMO | QUEUE_DEMO | IRQ_DEMO | NOTIFICATION_DEMO ) + +/** @brief Bitfield used to select the Demo Tasks to build and run + * + * @note This project contains multiple demo and test tasks. A bitfield is used + * to select which demos and tests are built and run as part of the executable. + * More information about what these demos and tests do can be found in their + * corresponding files. + * + * Bit 1 Set: Include the Register Test Tasks + * + * Bit 2 Set: Include the Queue Send and Receive Test Tasks + * + * Bit 3 Set: Include the Nested IRQ Test Tasks + * + * Bit 4 Set: Include the Notification Test Tasks + * + */ +#ifndef mainDEMO_TYPE + #define mainDEMO_TYPE ( FULL_DEMO ) +#endif /* mainDEMO_TYPE */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "portmacro.h" + +/* These tasks have been given pseudo random priority values for testing. + * Except for the queue send and receive task any of these tasks priorities + * should be able to be set to any valid priority without issue. */ + +/** @brief Priority at which the Register Task 1 is created. */ +#define demoREG_TASK_1_PRIORITY ( configMAX_PRIORITIES - 2UL ) + +/** @brief Priority at which the Register Task 2 is created. */ +#define demoREG_TASK_2_PRIORITY ( configMAX_PRIORITIES - 1UL ) + +/** @brief Priority at which the prvQueueSendTask is created. */ +#define demoQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1UL ) + +/** @brief Priority at which the prvQueueReceiveTask is created. */ +#define demoQUEUE_RECEIVE_TASK_PRIORITY ( demoQUEUE_SEND_TASK_PRIORITY + 1UL ) + +/** @brief Priority at which the Nested IRQ Test Task is created. */ +#define demoIRQ_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 2UL ) + +/** @brief Priority at which the Notification Demo Task is created. */ +#define demoNOTIFICATION_TASK_PRIORITY ( configTIMER_TASK_PRIORITY + 1UL ) + +/* ------------------------------- Register Test Tasks ------------------------------- */ + +/* @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest1Implementation( void ); + +/** @brief ASM function in reg_test_GCC.S that tests proper context swaps. */ +void vRegTest2Implementation( void ); + +/** @brief Creates the Register Test Tasks implemented in reg_test_GCC.S + * @return pdPASS if all tasks are created, pdFAIL if they are not. + */ +BaseType_t xCreateRegisterTestTasks( void ); + +/* ----------------------------- Demo Tasks Declarations ----------------------------- */ + +/** + * @brief Create two tasks, a queue, and a timer, which are used to blink an LED. + * + * @return + * pdPASS if all objects are created. + * pdFAIL if any object cannot be created. + */ +BaseType_t xCreateQueueTasks( void ); + +/** @brief Create a task that waits for a response from a nested IRQ + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateIRQTestTask( void ); + +/** + * @brief Create tasks that send task notifications back and forth. + * + * @return pdPASS if tasks are created + * pdFAIL if tasks are not created + */ +BaseType_t xCreateNotificationTestTask( void ); + +/** @brief Interrupt Handler used for Software Raised Interrupts */ +PRIVILEGED_FUNCTION void vIRQDemoHandler( void ); + +/* Registers required to configure the Real Time Interrupt (RTI). */ +#define portRTI_GCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC00UL ) ) +#define portRTI_TBCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC04UL ) ) +#define portRTI_COMPCTRL_REG ( *( ( volatile uint32_t * ) 0xFFFFFC0CUL ) ) +#define portRTI_CNT0_FRC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC10UL ) ) +#define portRTI_CNT0_UC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC14UL ) ) +#define portRTI_CNT0_CPUC0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC18UL ) ) +#define portRTI_CNT0_COMP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC50UL ) ) +#define portRTI_CNT0_UDCP0_REG ( *( ( volatile uint32_t * ) 0xFFFFFC54UL ) ) +#define portRTI_SETINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC80UL ) ) +#define portRTI_CLEARINTENA_REG ( *( ( volatile uint32_t * ) 0xFFFFFC84UL ) ) +#define portRTI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFC88UL ) ) +#define portEND_OF_INTERRUPT_REG ( ( ( volatile uint32_t * ) configEOI_ADDRESS ) ) + + +/* Registers used by the Vectored Interrupt Manager */ +typedef void ( * ISRFunction_t )( void ); +#define portVIM_IRQ_INDEX ( *( ( volatile uint32_t * ) 0xFFFFFE00 ) ) +#define portVIM_IRQ_VEC_REG ( *( ( volatile ISRFunction_t * ) 0xFFFFFE70 ) ) + +#define portSSI_INT_REG_BASE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) + +#define portSSI_INT_REG_ONE ( ( ( volatile uint32_t * ) 0xFFFFFFB0 ) ) +#define portSSI_ONE_KEY 0x7500UL + +#define portSSI_INT_REG_TWO ( ( ( volatile uint32_t * ) 0xFFFFFFB4 ) ) +#define portSSI_TWO_KEY 0x8400UL + +#define portSSI_INT_REG_THREE ( ( ( volatile uint32_t * ) 0xFFFFFFB8 ) ) +#define portSSI_THREE_KEY 0x9300UL + +#define portSSI_INT_REG_FOUR ( ( ( volatile uint32_t * ) 0xFFFFFFBC ) ) +#define portSSI_FOUR_KEY 0xA200UL + +#define portSSI_VEC_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF4 ) ) +#define portSSI_INTFLAG_REG ( *( ( volatile uint32_t * ) 0xFFFFFFF8 ) ) + +/* --------------------------- Shared Function Deceleration --------------------------- */ + +/** @brief Function to toggle LEDs on the RM57-XL2 Launchpad + * @param ulLED Which LED to flicker + */ +void vToggleLED( uint32_t ulLED ); + +/* ----------------------------------------------------------------------------------- */ + +#endif /* DEMO_TASKS_H */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c new file mode 100644 index 00000000000..f097d9f8574 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/irq_demo.c @@ -0,0 +1,244 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if ( mainDEMO_TYPE &IRQ_DEMO ) + +/** @brief TCB used by the IRQ Test Task. */ + static StaticTask_t xIRQTestTaskTCB; + +/** @brief Stack used by the IRQ Test Task. */ + + static StackType_t uxIRQTestTaskStack[ configMINIMAL_STACK_SIZE ]; + +/** @brief Parameters that are passed into the IRQ test task solely for + * the purpose of ensuring parameters are passed into tasks correctly. */ + #define irqTASK_PARAMETER ( 0xFEEDBEEFUL ) + +/** @brief Statically allocated task handle for the IRQ Test task. */ + static TaskHandle_t xIRQTaskHandle; + + volatile static uint32_t ulIntNestTestVal; +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the IRQ Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task raises Software Interrupts (SWI) in the form of IRQs using the + * Vectored Interrupt Manager (VIM) built into the RM57 by Texas Instrument (TI). + * It does this through use of the Software Interrupt Registers (SSIRs). + * More information about these can be found in the following document: + * https://www.ti.com/document-viewer/RM57L843/datasheet#system_information_and_electrical_specifications/SPNS1607150 + */ + static void prvIRQTestTask( void * pvParameters ) + { + /* Ensure that the correct parameter was passed to the task. */ + configASSERT( ( uint32_t ) pvParameters == irqTASK_PARAMETER ); + volatile uint32_t * xSoftwareInterruptRegister; + volatile TickType_t ulLoopCount; + volatile TickType_t xPreIRQTickCount; + + for( ; ; ) + { + sci_print( "IRQ Test Task Starting IRQ Nesting Test!\r\n" ); + ulIntNestTestVal = 0xFFFFUL; + + /* Get the tick count before raising the SWI */ + xPreIRQTickCount = xTaskGetTickCount(); + + /* Trigger an IRQ by writing to the SSI Register with a data value */ + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + *xSoftwareInterruptRegister = portSSI_FOUR_KEY | 0x44UL; + + /* When using a debugger IRQs can be paused/delayed. + * This loop exists to keep the compiler from optimizing it out + * while also giving the debugger time to trigger the IRQ. */ + ulLoopCount = xPreIRQTickCount; + + while( ( ulLoopCount + xPreIRQTickCount ) < ( xPreIRQTickCount + 0x20UL ) ) + { + if( 0xFFFFUL != ulIntNestTestVal ) + { + ulLoopCount++; + } + else + { + ulLoopCount = 0xFFFF0000UL; + } + } + + if( 0x4UL == ulIntNestTestVal ) + { + sci_print( "IRQ Test Task reported correct unwinding!\r\n" ); + vToggleLED( 0x1 ); + } + else + { + sci_print( "IRQ Test Task did not receive the correct nesting value!\r\n" ); + configASSERT( 0x0 ); + } + + sci_print( "IRQ Test Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times. */ + vTaskDelay( pdMS_TO_TICKS( 3150UL ) ); + } + } + +/* ----------------------------------------------------------------------------------- */ + + void vIRQDemoHandler( void ) + { + sci_print( "\tSWI Based IRQ was raised!\r\n" ); + volatile uint32_t ulSSIRegisterValue; + volatile uint32_t ulSSIIntFlagValue; + volatile uint32_t * xSoftwareInterruptRegister; + /* The 4 different SWI Registers use a bitfield to mark that they where raised. */ + { + /* Determine what channel raised the IRQ without clearing the interrupt. */ + ulSSIIntFlagValue = portSSI_INTFLAG_REG; + + if( 0x1UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x11UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #1 Raised with Data Value 0x11, clearing the " + "IRQs...\r\n" ); + /* Read to mark this IRQ as cleared. */ + /* Mark the Nested Channel 1 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x1101UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 2 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x2202UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 3 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x3303UL == ulSSIIntFlagValue ); + + /* Mark the Nested Channel 4 IRQ as cleared. */ + ulSSIIntFlagValue = portSSI_VEC_REG; + configASSERT( 0x4404UL == ulSSIIntFlagValue ); + + /* Should be no other IRQs raised, mask out the data. */ + ulSSIIntFlagValue = ( portSSI_VEC_REG ) & 0XFFUL; + configASSERT( 0x0UL == ulSSIIntFlagValue ); + } + } + + else if( 0x2UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x22UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #2 triggering nested Channel #1 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_ONE; + *xSoftwareInterruptRegister = portSSI_ONE_KEY | 0x11UL; + __asm volatile ( "CPSIE I" ); + } + } + + else if( 0x4UL & ulSSIIntFlagValue ) + { + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x33UL ) + { + ulIntNestTestVal++; + sci_print( "\t\tSWI Channel #3 triggering nested Channel #2 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_TWO; + *xSoftwareInterruptRegister = portSSI_TWO_KEY | 0x22UL; + __asm volatile ( "CPSIE I" ); + } + } + + else /* if( 0x8UL & ulSSIIntFlagValue ) */ + { + xSoftwareInterruptRegister = portSSI_INT_REG_FOUR; + ulSSIRegisterValue = *xSoftwareInterruptRegister; + + if( ulSSIRegisterValue & 0x44UL ) + { + ulIntNestTestVal = 0x1UL; + sci_print( "\t\tSWI Channel #4 triggering nested Channel #3 IRQ!\r\n" ); + xSoftwareInterruptRegister = portSSI_INT_REG_THREE; + *xSoftwareInterruptRegister = portSSI_THREE_KEY | 0x33UL; + __asm volatile ( "CPSIE I" ); + } + } + } + } + +/* ----------------------------------------------------------------------------------- */ + + BaseType_t xCreateIRQTestTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* Create the IRQ check tasks, as described at the top of this file. */ + xIRQTaskHandle = xTaskCreateStatic( prvIRQTestTask, + "IRQTestTask", + configMINIMAL_STACK_SIZE, + ( void * ) irqTASK_PARAMETER, + ( configTIMER_TASK_PRIORITY + 0x2UL ), + uxIRQTestTaskStack, + &xIRQTestTaskTCB ); + + if( xIRQTaskHandle != NULL ) + { + sci_print( "Created the IRQ Test Task\r\n" ); + xReturn = pdPASS; + } + else + { + sci_print( "Failed to create the IRQ Test Task\r\n" ); + } + + ulIntNestTestVal = 0xFEEDBEEFUL; + return xReturn; + } +#endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/main.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/main.c new file mode 100644 index 00000000000..fcd4380cd38 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/main.c @@ -0,0 +1,466 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* ------------------------------------------------------------------------- */ + +/** + * @file main.c + * @brief File implementing RM57L843 specific functions + */ + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "portmacro.h" +#include "task.h" +#include "timers.h" + +/* Standard includes. */ +#include +#include + +/* HalCoGen includes. */ +#include "system.h" +#include "gio.h" +#include "het.h" +#include "reg_vim.h" +#include "sci.h" +#include "sys_vim.h" +#include "system.h" + +/* Demo Tasks include */ +#include "demo_tasks.h" + +/* ----------------------- Microcontroller Registers ----------------------- */ + +/** @brief Configure the hardware to start the scheduler timer. */ +void vMainSetupTimerInterrupt( void ); + +/** @brief Set up necessary hardware registers. */ +static void prvSetupHardware( void ); + +/** @brief Landing point function for any failed configASSERT() check. + * @param pcFuncName The function that raised the assert. + * @param ulLine The line that the assert was called from. */ +void vAssertCalled( const char * pcFileName, + uint32_t ulLine ); + +void vApplicationIRQHandler( void ); +/* --------------------- Static Task Memory Allocation --------------------- */ + +/** @brief Statically declared TCB Used by the Idle Task. */ +static StaticTask_t xTimerTaskTCB; + +/** @brief Statically declared stack used by the timer task. */ +static StackType_t uxTimerTaskStack[ configMINIMAL_STACK_SIZE ]; + +/** @brief Statically declared TCB Used by the Idle Task. */ +static StaticTask_t xIdleTaskTCB; + +/** @brief Statically declared stack used by the idle task. */ +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + +/** @brief Simple variable to show how the idle tick hook can be used. */ +static volatile TickType_t ulIdleTickHookCount = 0x0; + +extern volatile uint32_t ulPortYieldRequired; + +/* ------------------------------------------------------------------------- */ + +int main( void ) +{ + UBaseType_t xReturn = pdPASS; + + ulIdleTickHookCount = 0x0; + prvSetupHardware(); + + sci_print( "\r\n---------------------------- Create FreeRTOS Tasks" + "----------------------------\r\n\r\n" ); + + #if ( mainDEMO_TYPE & REGISTER_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Register test tasks\r\n" ); + xReturn = xCreateRegisterTestTasks(); + } + } + #endif /* ( mainDEMO_TYPE & REGISTER_DEMO ) */ + + #if ( mainDEMO_TYPE & QUEUE_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Queue Demo Tasks\r\n" ); + xReturn = xCreateQueueTasks(); + } + } + #endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ + + #if ( mainDEMO_TYPE & IRQ_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the IRQ Demo Tasks\r\n" ); + xReturn = xCreateIRQTestTask(); + } + } + #endif /* ( mainDEMO_TYPE & IRQ_DEMO ) */ + + #if ( mainDEMO_TYPE & NOTIFICATION_DEMO ) + { + if( pdPASS == xReturn ) + { + sci_print( "Creating the Notification Demo Tasks\r\n" ); + xReturn = xCreateNotificationTestTask(); + } + } + #endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ + + if( pdPASS == xReturn ) + { + sci_print( "\r\n--------------------------- Start of FreeRTOS Demo Tasks" + "---------------------------\r\n\r\n" ); + vTaskStartScheduler(); + } + else + { + sci_print( "Failed to create the Demo Tasks\r\n" ); + configASSERT( pdFAIL ); + } + + /* If all is well, the scheduler will now be running, and the following + * line will never be reached. If the following line does execute, then + * there was an error when creating the necessary FreeRTOS objects. */ + configASSERT( 0x0 ); + return 0; +} +/*---------------------------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + systemInit(); + gioInit(); + hetInit(); + sciInit(); + + /* Setup gioPORTB for when using the RM57 Launchpad. */ + gioPORTB->DIR |= ( 0x01 << 6 ); /*configure GIOB[6] as output. */ + gioPORTB->DIR |= ( 0x01 << 7 ); /*configure GIOB[7] as output. */ + + /* Configure HET as master, pull functionality, and switch on. */ + hetREG1->GCR = 0x01000001; + hetREG1->PULDIS = 0x00000000; + + /* Configure pins connected to LEDs NHET[0,2,4,5,25,16,17,18,20,27,29,31] + * as output. */ + hetREG1->DIR = 0xAA178035; + hetREG1->DOUT = 0x0; + + /* Enable notifications for the SCI register. */ + /* Use a BAUD rate of 115200, 1 stop bit, and None Parity. */ + sciEnableNotification( scilinREG, SCI_RX_INT ); +} + +/*---------------------------------------------------------------------------*/ + +void vToggleLED( uint32_t ulLEDNum ) +{ + uint32_t ulLEDVal; + uint32_t ulGIOVal; + + if( 0x0 == ulLEDNum ) + { + /* RM57 TMDX Dev Kit LED1 use NHET[27], Launchpad LED2 uses GIOB[6]. */ + ulLEDVal = 1UL << 27UL; + ulGIOVal = 1UL << 6UL; + } + else + { + /* RM57 TMDX Dev Kit LED2 use NHET[5], Launchpad LED3 uses GIOB[7]. */ + ulLEDVal = 1UL << 5UL; + ulGIOVal = 1UL << 7UL; + } + + if( ( hetREG1->DOUT & ulLEDVal ) == 0 ) + { + hetREG1->DOUT |= ulLEDVal; + gioPORTB->DOUT |= ulGIOVal; + } + else + { + hetREG1->DOUT &= ~ulLEDVal; + gioPORTB->DOUT &= ~ulGIOVal; + } +} + +/*---------------------------------------------------------------------------*/ + +void vMainSetupTimerInterrupt( void ) +{ + /* Disable timer 0. */ + portRTI_GCTRL_REG &= 0xFFFFFFFEUL; + + /* Use the internal counter. */ + portRTI_TBCTRL_REG = 0x00000000U; + + /* COMPSEL0 will use the RTIFRC0 counter. */ + portRTI_COMPCTRL_REG = 0x00000000U; + + /* Initialise the counter and the prescale counter registers. */ + portRTI_CNT0_UC0_REG = 0x00000000U; + portRTI_CNT0_FRC0_REG = 0x00000000U; + + /* Set Prescalar for RTI clock. */ + portRTI_CNT0_CPUC0_REG = 0x00000001U; + portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ; + + /* Clear interrupts. */ + portRTI_INTFLAG_REG = 0x0007000FU; + portRTI_CLEARINTENA_REG = 0x00070F0FU; + + /* Enable the compare 0 interrupt. */ + portRTI_SETINTENA_REG = 0x00000001U; + portRTI_GCTRL_REG |= 0x00000001U; +} + +/*---------------------------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + * to 1 in FreeRTOSConfig.h. It will be called on each iteration of the + * idle task. It is essential that code added to this hook function never + * attempts to block in any way (for example, call xQueueReceive() with a + * block time specified, or call vTaskDelay()). If application tasks make + * use of the vTaskDelete() API function to delete themselves then it is + * also important that vApplicationIdleHook() is permitted to return to its + * calling function, because it is the responsibility of the idle task to + * clean up memory allocated by the kernel to any task that has since + * deleted itself. */ + ulIdleTickHookCount++; + + if( ( TickType_t ) 0xF00000 == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xF0 0000 times!\r\n" ); + } + + else if( ( TickType_t ) 0xFFFFFFFF == ulIdleTickHookCount ) + { + sci_print( "vApplicationIdleHook has run 0xFFFFFFFF times! " + "Setting it to 0x0!\r\n" ); + ulIdleTickHookCount = 0x0; + } +} + +/*---------------------------------------------------------------------------*/ + +void vAssertCalled( const char * pcFuncName, + uint32_t ulLine ) +{ + volatile uint32_t ulSetToNonZeroInDebuggerToContinue = 0; + + /* Called if an assertion passed to configASSERT() fails. See + * http://www.freertos.org/a00110.html#configASSERT for more information. */ + volatile const char * callingFunc = pcFuncName; + volatile uint32_t callingLine = ulLine; + + /* These variables can be inspected in a debugger. */ + if( callingFunc != ( char * ) callingLine ) + { + __asm volatile ( "NOP" ); + } + + taskENTER_CRITICAL(); + { + /* You can step out of this function to debug the assertion by using + * the debugger to set ulSetToNonZeroInDebuggerToContinue to a non-zero + * value. */ + while( ulSetToNonZeroInDebuggerToContinue == 0 ) + { + __asm volatile ( "NOP" ); + __asm volatile ( "NOP" ); + } + } + taskEXIT_CRITICAL(); +} + +/*---------------------------------------------------------------------------*/ + +/** @brief Default IRQ Handler used in the ARM_Cortex_RX ports. + * @note This Handler is directly tied to the Texas Instrument's Hercules + * Vectored Interrupt Manager (VIM). For more information about what + * this is and how it operates please refer to their document: + * https://www.ti.com/lit/pdf/spna218 + */ +void vApplicationIRQHandler( void ) +{ + /* Load the IRQ Channel Number and Function PTR from the VIM. */ + volatile uint32_t ulIRQChannelIndex = portVIM_IRQ_INDEX; + volatile ISRFunction_t xIRQFncPtr = portVIM_IRQ_VEC_REG; + + /* Setup Bit Mask Clear Values. */ + volatile uint32_t ulPendingIRQMask; + + volatile uint32_t ulPendISRReg0 = vimREG->REQMASKCLR0; + volatile uint32_t ulPendISRReg1 = vimREG->REQMASKCLR1; + volatile uint32_t ulPendISRReg2 = vimREG->REQMASKCLR2; + volatile uint32_t ulPendISRReg3 = vimREG->REQMASKCLR3; + + if( NULL == xIRQFncPtr ) + { + sci_print( "Received a NULL Function Pointer from the IRQ VIM\r\n" ); + configASSERT( pdFALSE ); + } + else + { + if( 0U != ulIRQChannelIndex ) + { + ulIRQChannelIndex--; + } + + if( ulIRQChannelIndex <= 31U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ulIRQChannelIndex; + vimREG->REQMASKCLR0 = ulPendingIRQMask; + vimREG->REQMASKCLR1 = 0xFFFFFFFFU; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 63U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 32U ); + vimREG->REQMASKCLR1 = ulPendingIRQMask; + vimREG->REQMASKCLR2 = 0xFFFFFFFFU; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else if( ulIRQChannelIndex <= 95U ) + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 64U ); + vimREG->REQMASKCLR2 = ulPendingIRQMask; + vimREG->REQMASKCLR3 = 0xFFFFFFFFU; + } + else + { + ulPendingIRQMask = 0xFFFFFFFFU << ( ulIRQChannelIndex - 96U ); + vimREG->REQMASKCLR3 = ulPendingIRQMask; + } + } + + /* + * Channel 0 is the ESM handler, treat this as a special case. + * phantomInterrupt() + * Keep interrupts disabled, this function does not return. + */ + + if( 0UL == ulIRQChannelIndex ) + { + sci_print( "Phantom interrupt?\r\n" ); + configASSERT( pdFALSE ); + ( *xIRQFncPtr )(); + } + else if( ( phantomInterrupt == xIRQFncPtr ) ) + { + sci_print( "IRQ With no registered function in sys_vim.c has been raised\r\n" ); + configASSERT( pdFALSE ); + } + else + { + /* Information about the mapping of Interrupts in the VIM to their + * causes can be found in the RM57L843 Data Sheet: + * https://www.ti.com/document-viewer/RM57L843/datasheet#system_information_and_electrical_specifications/SPNS1607150 */ + /* An IRQ Raised by Channel Two of the VIM is RTI Compare Interrupt 0. */ + if( 2UL == ulIRQChannelIndex ) + { + /* This is the System Tick Timer Interrupt. */ + ulPortYieldRequired = xTaskIncrementTick(); + /* Acknowledge the System Tick Timer Interrupt. */ + portRTI_INTFLAG_REG = 0x1UL; + } + /* An IRQ Raised by Channel 21 of the VIM is a Software Interrupt (SSI). */ + else if( 21UL == ulIRQChannelIndex ) + { + #if ( mainDEMO_TYPE &IRQ_DEMO ) + /* This is an interrupt raised by Software. */ + vIRQDemoHandler(); + #else + sci_print( "SWI of unknown cause was raised!\r\n" ); + configASSERT( 0x0 ); + #endif + + /* Register read is needed to mark the end of the IRQ. */ + volatile uint32_t ulEndOfIntRegVal = *portEND_OF_INTERRUPT_REG; + *portEND_OF_INTERRUPT_REG = ulEndOfIntRegVal; + } + else + { + sci_print( "Unmapped IRQ Channel Number Raised\r\n" ); + } + } + + vimREG->REQMASKSET0 = ulPendISRReg0; + vimREG->REQMASKSET1 = ulPendISRReg1; + vimREG->REQMASKSET2 = ulPendISRReg2; + vimREG->REQMASKSET3 = ulPendISRReg3; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, + StackType_t ** ppxIdleTaskStackBuffer, + uint32_t * pulIdleTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Idle + * task's state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ + +void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, + StackType_t ** ppxTimerTaskStackBuffer, + uint32_t * pulTimerTaskStackSize ) +{ + /* Pass out a pointer to the StaticTask_t structure in which the Timer + * task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + * Note that, as the array is necessarily of type StackType_t, + * configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*---------------------------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c new file mode 100644 index 00000000000..43f2070615d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/notification_demo.c @@ -0,0 +1,203 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +#if ( mainDEMO_TYPE & NOTIFICATION_DEMO ) + + /** @brief Parameters that are passed into the notification test task solely + * for the purpose of ensuring parameters are passed into tasks correctly. */ + #define notificationTASK_PARAMETER ( 0xFEEDBEEFUL ) + + /** @brief Value sent back and forth between the tasks. */ + #define notificationTEST_VALUE 0x1234UL + + /** @brief TCB used by the Notification Test Task. */ + static StaticTask_t xNotificationTestTaskTCB; + + /** @brief Stack used by the Notification Test Task. */ + static StackType_t uxNotificationTestTaskStack[ configMINIMAL_STACK_SIZE ]; + + /** @brief Statically allocated task handle for the Notification Test task. */ + static TaskHandle_t xNotificationTaskOneHandle; + +/* ----------------------------------------------------------------------------------- */ + + static void prvNotifyCheck( BaseType_t ulRetVal ) + { + if( pdPASS == ulRetVal ) + { + sci_print( "Notification API Returned a passing value!\r\n" ); + } + else + { + sci_print( "Notification API did not return pdPASS.\r\n" ); + configASSERT( ulRetVal ); + } + } + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Notification Test Task. + * @param pvParameters A test value to ensure the task's arguments are correctly + * set. + * @note This task sends itself and another task notifications using the + * cross-task notification APIs. + */ + static void prvNotificationTestTask( void * pvParameters ) + { + BaseType_t xReturned; + UBaseType_t ulNotificationValue; + + /* Ensure that the correct parameter was passed to the task. */ + configASSERT( ( uint32_t ) pvParameters == notificationTEST_VALUE ); + + for( ; ; ) + { + /* Clear the notification value each loop. */ + ulNotificationValue = 0x0UL; + + /* The task should not yet have a notification pending. */ + xReturned = xTaskNotifyWait( 0x0UL, 0x0UL, + &ulNotificationValue, 0x0UL ); + configASSERT( pdFAIL == xReturned ); + configASSERT( 0x0UL == ulNotificationValue ); + + /* Tell the task to notify itself twice. */ + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + xReturned = xTaskNotifyGive( xTaskGetCurrentTaskHandle() ); + prvNotifyCheck( xReturned ); + + /* Perform a non-blocking notification read, should see two "gives". */ + ulNotificationValue = ulTaskNotifyTake( pdTRUE, 0x0 ); + + /* Two notifications have been sent to this task by itself. */ + configASSERT( 0x2UL == ulNotificationValue ); + sci_print( "Notification Task correctly sent itself two" + "notifications!\r\n" ); + + /* Now make the task send itself a notification with a value. */ + xReturned = xTaskNotify( xTaskGetCurrentTaskHandle(), + notificationTEST_VALUE, + eSetValueWithOverwrite ); + prvNotifyCheck( xReturned ); + + /* Clear ulNotificationValue before using it. */ + ulNotificationValue = 0x0UL; + + /* Receive the value sent using xTaskNotify. */ + xReturned = xTaskNotifyWait( 0, + ( uint32_t ) 0xFFFFFFFFUL, + &ulNotificationValue, + ( TickType_t ) 0x50UL ); + prvNotifyCheck( xReturned ); + + if( notificationTEST_VALUE == ulNotificationValue ) + { + sci_print( "Notification Task got the expected value!\r\n" ); + } + else + { + sci_print( "Notification Task did NOT get the expected" + "value!\r\n" ); + configASSERT( 0x0UL ); + } + + /* Reset the variable before using it. */ + ulNotificationValue = 0x0UL; + + /* There should be no value to receive this time. */ + xReturned = xTaskNotifyWait( 0, 0, &ulNotificationValue, + ( TickType_t ) 0x0UL ); + + if( ( pdPASS == xReturned ) || ( 0x0 != ulNotificationValue ) ) + { + sci_print( "Notification Task received a value when there" + "should have been none" ); + configASSERT( 0x0UL ); + } + + xTaskNotify( xTaskGetCurrentTaskHandle(), + ulNotificationValue, + eSetValueWithOverwrite ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* First time a notification was pending. */ + configASSERT( xReturned == pdTRUE ); + xReturned = xTaskNotifyStateClear( NULL ); + + /* Second time the notification was already clear. */ + configASSERT( xReturned == pdFALSE ); + + sci_print( "Notification Task sleeping before next loop!\r\n\r\n" ); + /* Sleep for odd number of seconds to schedule at different real-times. */ + vTaskDelay( pdMS_TO_TICKS( 2750UL ) ); + } + } + +/* ----------------------------------------------------------------------------------- */ + + BaseType_t xCreateNotificationTestTask( void ) + { + BaseType_t xReturn = pdFAIL; + + /* Create the notification test task. */ + xNotificationTaskOneHandle = xTaskCreateStatic( prvNotificationTestTask, + "NotificationTestTask", + configMINIMAL_STACK_SIZE, + ( void * ) notificationTEST_VALUE, + demoNOTIFICATION_TASK_PRIORITY, + uxNotificationTestTaskStack, + &xNotificationTestTaskTCB ); + + if( xNotificationTaskOneHandle != NULL ) + { + sci_print( "Created the Notification Test Task\r\n" ); + xReturn = pdPASS; + } + else + { + sci_print( "Failed to create the Notification Test Task\r\n" ); + } + + return xReturn; + } +#endif /* ( mainDEMO_TYPE & NOTIFICATION_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c new file mode 100644 index 00000000000..00233d01ab1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/queue_demo.c @@ -0,0 +1,355 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file queue_demo.c + * @brief Use the Queue APIs to send data from a sender task to a receiver task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "queue.h" + +/* Board Support Package Includes. */ +#include "sci.h" +#include "reg_system.h" + +/* Demo Specific Includes. */ +#include "demo_tasks.h" + +#if ( mainDEMO_TYPE & QUEUE_DEMO ) + + /* ------------------------------ Demo Task Configs --------------------*/ + + /** @brief The rate at which data is sent to the queue from the send task. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTASK_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200UL ) + + /** @brief The rate at which data is sent to the queue from the timer. + * @note Ticks are converted to milliseconds using pdMS_TO_TICKS(). */ + #define queueTIMER_SEND_FREQUENCY_MS pdMS_TO_TICKS( 2000UL ) + + /** @brief The number of items the queue can hold at once. */ + #define queueQUEUE_LENGTH ( 2 ) + + /** @brief Value sent from the send task to the receive task. */ + #define queueVALUE_SENT_FROM_TASK ( 0x1234UL ) + + /** @brief Value sent from the timer to the receive task. */ + #define queueVALUE_SENT_FROM_TIMER ( 0x4321UL ) + +/* --------------------- Task Function Declaration --------------------- */ + +/** @brief Function run by the task that receives data from the queue. + * @note + * The queue receive task is implemented by the prvQueueReceiveTask() + * function in this file. prvQueueReceiveTask() waits for data to arrive on + * the queue. When data is received, the task checks the value of the data, + * then outputs a message to indicate if the data came from the queue send + * task or the queue send software timer. */ + static void prvQueueReceiveTask( void * pvParameters ); + +/** @brief Function run by the task that sends data to a queue. + * @note + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. It uses vTaskDelayUntil() to create a periodic task that + * sends queueVALUE_SENT_FROM_TASK to the queue every 200 milliseconds. */ + static void prvQueueSendTask( void * pvParameters ); + +/** @brief The callback function executed when the timer expires. + * @note + * The timer is an auto-reload timer with a period of two seconds. Its + * callback function sends the value queueVALUE_SENT_FROM_TIMER to the + * queue. The callback function is implemented by prvQueueSendTimerCallback(). + */ + static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ); + +/*-------------------- Static Task Memory Allocation ------------------- */ + +/** @brief Statically allocated Queue object. */ + static StaticQueue_t xStaticQueue; + +/** @brief Statically allocated Storage for the Queue. */ + static uint8_t xQueueStorage[ 0x20 ]; + +/** @brief Statically allocated QueueHandle. */ + static QueueHandle_t xQueue; + +/* Each task needs to know the other tasks' handle so they can send signals to + * each other. The handle is obtained from the task's name. */ + +/** @brief Task name for the queue send task. */ + static const char * pcSendTaskName = "SendTaskName"; + +/** @brief Task name for the queue receive task. */ + static const char * pcReceiveTaskName = "ReceiveTaskName"; + +/** @brief Statically allocated stack used by the Queue Send Task. */ + static StackType_t xQueueSendTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/** @brief Static TCB Used by the Queue Send Task. */ + static StaticTask_t xQueueSendTaskTCB; + +/** @brief Statically allocated stack used by the Queue Receive Task. */ + static StackType_t xQueueReceiveTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/** @brief Static TCB Used by the Queue Receive Task. */ + static StaticTask_t xQueueReceiveTaskTCB; + +/** @brief A software timer that is started from the tick hook. */ + static TimerHandle_t xTimer = NULL; + +/** @brief Statically allocated timer object. */ + static StaticTimer_t xStaticTimer; + +/** @brief Statically allocated task handle for the queue receive task. */ + static TaskHandle_t xReceiveTaskHandle; + +/** @brief Statically allocated task handle for the queue send task. */ + static TaskHandle_t xSendTaskHandle; + +/* ------------------------------------------------------------------------------------ */ + + BaseType_t prvCreateQueueTasks( void ) + { + BaseType_t xReturn = pdPASS; + + xReceiveTaskHandle = xTaskCreateStatic( prvQueueReceiveTask, + pcReceiveTaskName, + configMINIMAL_STACK_SIZE / 2U, + NULL, + demoQUEUE_RECEIVE_TASK_PRIORITY, + xQueueReceiveTaskStack, + &xQueueReceiveTaskTCB ); + + if( xReceiveTaskHandle != NULL ) + { + sci_print( "Created the Queue Receive Task\r\n" ); + + xSendTaskHandle = xTaskCreateStatic( prvQueueSendTask, + pcSendTaskName, + configMINIMAL_STACK_SIZE / 2U, + NULL, + demoQUEUE_SEND_TASK_PRIORITY, + xQueueSendTaskStack, + &xQueueSendTaskTCB ); + + if( xSendTaskHandle != NULL ) + { + sci_print( "Created the Queue Send Task\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + } + else + { + sci_print( "Failed to create the Queue Receive Task\r\n" ); + xReturn = pdFAIL; + } + + return xReturn; + } + +/* ------------------------------------------------------------------------------------ */ + + BaseType_t xCreateQueueTasks( void ) + { + BaseType_t xReturn = pdPASS; + + /* The Receive Task MUST be a higher priority than the send task. */ + configASSERT( demoQUEUE_RECEIVE_TASK_PRIORITY > demoQUEUE_SEND_TASK_PRIORITY ); + + /* Create the queue used by the queue tasks . */ + xQueue = xQueueCreateStatic( queueQUEUE_LENGTH, + sizeof( uint32_t ), + xQueueStorage, + &xStaticQueue ); + + if( xQueue != NULL ) + { + sci_print( "Created the Queue for the tasks\r\n" ); + + /** @brief The debugging text name for the timer. */ + const char * pcTimerName = "Timer"; + /** @brief Mark that this is an auto-reload timer. */ + const BaseType_t xAutoReload = ( BaseType_t ) pdTRUE; + /** @brief Timer ID that is not used in this demo. */ + void * const pvTimerID = NULL; + /** @brief Callback function for the timer. */ + TimerCallbackFunction_t pxCallbackFunction = prvQueueSendTimerCallback; + + /* Create a statically allocated timer. */ + xTimer = xTimerCreateStatic( pcTimerName, + ( const TickType_t ) queueTIMER_SEND_FREQUENCY_MS, + xAutoReload, + pvTimerID, + pxCallbackFunction, + &( xStaticTimer ) ); + } + else + { + sci_print( "Failed to create the Queue for the tasks\r\n" ); + xReturn = pdFAIL; + } + + if( NULL != xTimer ) + { + sci_print( "Created the Queue Timer\r\n" ); + } + else + { + sci_print( "Failed to create the Queue Timer\r\n" ); + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + xReturn = prvCreateQueueTasks(); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + /* The scheduler has not started so use a block time of 0. */ + xReturn = xTimerStart( xTimer, 0 ); + } + else + { + xReturn = pdFAIL; + } + + if( pdPASS == xReturn ) + { + sci_print( "Started the Timer\r\n" ); + } + else + { + sci_print( "Failed to start the Queue Timer\r\n" ); + } + + return xReturn; + } + +/*-----------------------------------------------------------------------*/ + + static void prvQueueSendTask( void * pvParameters ) + { + TickType_t xNextWakeTime; + const TickType_t xBlockTime = queueTASK_SEND_FREQUENCY_MS; + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TASK; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ; ; ) + { + /* Move this task to the blocked state for xBlockTime milliseconds. + * The block time is specified in ticks, pdMS_TO_TICKS() was used to + * convert a time specified in milliseconds into a time specified in + * ticks. While in the Blocked state this task will not consume any + * CPU time. */ + xTaskDelayUntil( &xNextWakeTime, xBlockTime ); + + /* Send to the queue - causing the queue receive task to unblock + * and write to the console. 0 is used as the block time so the send + * operation will not block. It shouldn't need to block as the queue + * should always have at least one space at this point in the code. + */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } + } + +/*-----------------------------------------------------------------------*/ + + static void prvQueueSendTimerCallback( TimerHandle_t xTimerHandle ) + { + const uint32_t ulValueToSend = queueVALUE_SENT_FROM_TIMER; + + /* This is the software timer callback function. The software timer has + * a period of two seconds. This callback function will execute if the + * timer expires, which will happen every two seconds. */ + + /* Avoid compiler warnings resulting from the unused parameter. */ + ( void ) xTimerHandle; + + /* Send to the queue - causing the queue receive task to unblock and + * write out a message. This function is called from the timer/daemon + * task, so must not block. Hence the block time is set to 0. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } + +/*-----------------------------------------------------------------------*/ + + static void prvQueueReceiveTask( void * pvParameters ) + { + uint32_t ulReceivedValue = 0; + + /* Prevent the compiler warning about the unused parameter. */ + ( void ) pvParameters; + + for( ; ; ) + { + /* Wait until something arrives in the queue - this task will block + * indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + * FreeRTOSConfig.h. It will not use any CPU time while it is in the + * Blocked state. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, + * but is it an expected value? */ + if( ulReceivedValue == queueVALUE_SENT_FROM_TASK ) + { + vToggleLED( 0x0 ); + } + else if( ulReceivedValue == queueVALUE_SENT_FROM_TIMER ) + { + vToggleLED( 0x1 ); + } + else + { + /* Invalid value received. Force an assert. */ + configASSERT( ulReceivedValue == !ulReceivedValue ); + } + } + } +/* --------------------------------------------------------------------- */ + +#endif /* ( mainDEMO_TYPE & QUEUE_DEMO ) */ diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c new file mode 100644 index 00000000000..e8735978cfa --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test.c @@ -0,0 +1,176 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/* Standard includes. */ +#include + +/* FreeRTOS includes. */ +#include "FreeRTOSConfig.h" +#include "FreeRTOS.h" +#include "task.h" +#include "portmacro.h" + +/* HalCoGen includes. */ +#include "sci.h" + +/* Demo include */ +#include "demo_tasks.h" + +/* ----------------------------------------------------------------------------------- */ + +/** @brief TCB used by Register Test Task One. */ +static StaticTask_t xRegTestOneTaskTCB; + +/** @brief Stack used by Register Test Task One. */ +static StackType_t uxRegTestOneTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/** @brief TCB used by Register Test Two Task. */ +static StaticTask_t xRegTestTwoTaskTCB; + +/** @brief Stack used by Register Test Task Two. */ +static StackType_t uxRegTestTwoTaskStack[ configMINIMAL_STACK_SIZE / 2U ]; + +/* Parameters that are passed into the register check tasks solely for the + * purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Array to track the number of loops the register test tasks have run. + * + * Register Test One will use loopCount[0]; + * Register Test Two Will use loopCount[1]; + */ +uint32_t loopCounter[ 0x8 ]; + +/** @brief Statically allocated task handle for the first register task. */ +static TaskHandle_t xRegisterTaskOneHandle; + +/** @brief Statically allocated task handle for the second register task. */ +static TaskHandle_t xRegisterTaskTwoHandle; + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Register Test 1 Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry1( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + else + { + /** The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +/** @brief Entry point for the Register Test 2 Task. + * @param pvParameters A test value to ensure the task's arguments are correctly set. + * @note This task runs in a loop to ensure that all General and Floating Point Registers + * don't change. Any change in value in the registers can only occur due to an improper + * context save or load. + */ +static void prvRegTestTaskEntry2( void * pvParameters ) +{ + /** Although the Register Test task is written in assembly, its entry point + * is written in C for convenience of checking the task parameter is being + * passed in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + else + { + /* The following line will only execute if the task parameter is found to + * be incorrect. The check task will detect that the regtest loop counter + * is not being incremented and flag an error. */ + vTaskDelete( NULL ); + } +} + +/* ----------------------------------------------------------------------------------- */ + +BaseType_t xCreateRegisterTestTasks( void ) +{ + BaseType_t xReturn = pdFAIL; + + /* Create the register check tasks, as described at the top of this file. */ + + /* Create the first register test task. */ + xRegisterTaskOneHandle = xTaskCreateStatic( prvRegTestTaskEntry1, + "RegTestOne", + configMINIMAL_STACK_SIZE / 0x2, + mainREG_TEST_TASK_1_PARAMETER, + demoREG_TASK_1_PRIORITY, + uxRegTestOneTaskStack, + &xRegTestOneTaskTCB ); + + if( xRegisterTaskOneHandle != NULL ) + { + sci_print( "Created the Register Test 1 Task\r\n" ); + + /* Create the second register test task. */ + xRegisterTaskTwoHandle = xTaskCreateStatic( prvRegTestTaskEntry2, + "RegTestTwo", + configMINIMAL_STACK_SIZE / 0x2, + mainREG_TEST_TASK_2_PARAMETER, + demoREG_TASK_2_PRIORITY, + uxRegTestTwoTaskStack, + &xRegTestTwoTaskTCB ); + + if( xRegisterTaskTwoHandle != NULL ) + { + sci_print( "Created the Register Test 2 Task\r\n" ); + xReturn = pdPASS; + } + else + { + sci_print( "Failed to create the Register Test 2 Task\r\n" ); + } + } + else + { + sci_print( "Failed to create the Register Test 1 Task\r\n" ); + } + + return xReturn; +} diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S new file mode 100644 index 00000000000..56684d893e0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/source/reg_test_GCC.S @@ -0,0 +1,443 @@ +/* + * FreeRTOS V202212.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#define FREERTOS_ASSEMBLY + #include "FreeRTOSConfig.h" +#undef FREERTOS_ASSEMBLY + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern vPortYield + .extern + .extern loopCounter + .text + .arm + +/*-----------------------------------------------------------*/ + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + MOV R0, #0xFF + MOV R1, #0x11 + MOV R2, #0x22 + MOV R3, #0x33 + MOV R4, #0x44 + MOV R5, #0x55 + MOV R6, #0x66 + MOV R7, #0x77 + MOV R8, #0x88 + MOV R9, #0x99 + MOV R10, #0xAA + MOV R11, #0xBB + MOV R12, #0xCC + MOV R14, #0xEE + + /* Fill each FPU register with a known value. */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg1_loop: + /* Perform a yield to increase test coverage */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88 + BLNE reg1_error_loopf + CMP R1, #0x99 + BLNE reg1_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA + BLNE reg1_error_loopf + CMP R1, #0xBB + BLNE reg1_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF + BLNE reg1_error_loopf + CMP R1, #0x11 + BLNE reg1_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22 + BLNE reg1_error_loopf + CMP R1, #0x33 + BLNE reg1_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44 + BLNE reg1_error_loopf + CMP R1, #0x55 + BLNE reg1_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66 + BLNE reg1_error_loopf + CMP R1, #0x77 + BLNE reg1_error_loopf + + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B reg1_error_loopf + B 0xDEACFC + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + CMP R0, #0xFF + BLNE reg1_error_loop + CMP R1, #0x11 + BLNE reg1_error_loop + CMP R2, #0x22 + BLNE reg1_error_loop + CMP R3, #0x33 + BLNE reg1_error_loop + CMP R4, #0x44 + BLNE reg1_error_loop + CMP R5, #0x55 + BLNE reg1_error_loop + CMP R6, #0x66 + BLNE reg1_error_loop + CMP R7, #0x77 + BLNE reg1_error_loop + CMP R8, #0x88 + BLNE reg1_error_loop + CMP R9, #0x99 + BLNE reg1_error_loop + CMP R10, #0xAA + BLNE reg1_error_loop + CMP R11, #0xBB + BLNE reg1_error_loop + CMP R12, #0xCC + BLNE reg1_error_loop + CMP R14, #0xEE + BLNE reg1_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0] + ADD R1, R1, #1 + STR R1, [R0] + POP { R0-R1 } + + /* Delay for 0x100 ticks before running again */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x100 + LDR R1, =vTaskDelay + BLX R1 + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B reg1_error_loop + NOP + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + MOV R0, #0xFF000000 + MOV R1, #0x11000000 + MOV R2, #0x22000000 + MOV R3, #0x33000000 + MOV R4, #0x44000000 + MOV R5, #0x55000000 + MOV R6, #0x66000000 + MOV R7, #0x77000000 + MOV R8, #0x88000000 + MOV R9, #0x99000000 + MOV R10, #0xAA000000 + MOV R11, #0xBB000000 + MOV R12, #0xCC000000 + MOV R14, #0xEE000000 + + /* Likewise the floating point registers. */ + VMOV D0, R0, R1 + VMOV D1, R2, R3 + VMOV D2, R4, R5 + VMOV D3, R6, R7 + VMOV D4, R8, R9 + VMOV D5, R10, R11 + VMOV D6, R0, R1 + VMOV D7, R2, R3 + VMOV D8, R4, R5 + VMOV D9, R6, R7 + VMOV D10, R8, R9 + VMOV D11, R10, R11 + VMOV D12, R0, R1 + VMOV D13, R2, R3 + VMOV D14, R4, R5 + VMOV D15, R6, R7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg2_loop: + + /* Yield to increase test coverage. */ + PUSH {R0, R14} + BLX vPortYield + POP {R0, R14} + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + PUSH { R0-R1 } + + VMOV R0, R1, D0 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D1 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D2 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D3 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D4 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D5 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D6 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D7 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D8 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D9 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + VMOV R0, R1, D10 + CMP R0, #0x88000000 + BLNE reg2_error_loopf + CMP R1, #0x99000000 + BLNE reg2_error_loopf + VMOV R0, R1, D11 + CMP R0, #0xAA000000 + BLNE reg2_error_loopf + CMP R1, #0xBB000000 + BLNE reg2_error_loopf + VMOV R0, R1, D12 + CMP R0, #0xFF000000 + BLNE reg2_error_loopf + CMP R1, #0x11000000 + BLNE reg2_error_loopf + VMOV R0, R1, D13 + CMP R0, #0x22000000 + BLNE reg2_error_loopf + CMP R1, #0x33000000 + BLNE reg2_error_loopf + VMOV R0, R1, D14 + CMP R0, #0x44000000 + BLNE reg2_error_loopf + CMP R1, #0x55000000 + BLNE reg2_error_loopf + VMOV R0, R1, D15 + CMP R0, #0x66000000 + BLNE reg2_error_loopf + CMP R1, #0x77000000 + BLNE reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + POP {R0-R1} + + /* VFP register test passed. Jump to the core register test. */ + B reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + B reg2_error_loopf + +reg2_loopf_pass: + + CMP R0, #0xFF000000 + BLNE reg2_error_loop + CMP R1, #0x11000000 + BLNE reg2_error_loop + CMP R2, #0x22000000 + BLNE reg2_error_loop + CMP R3, #0x33000000 + BLNE reg2_error_loop + CMP R4, #0x44000000 + BLNE reg2_error_loop + CMP R5, #0x55000000 + BLNE reg2_error_loop + CMP R6, #0x66000000 + BLNE reg2_error_loop + CMP R7, #0x77000000 + BLNE reg2_error_loop + CMP R8, #0x88000000 + BLNE reg2_error_loop + CMP R9, #0x99000000 + BLNE reg2_error_loop + CMP R10, #0xAA000000 + BLNE reg2_error_loop + CMP R11, #0xBB000000 + BLNE reg2_error_loop + CMP R12, #0xCC000000 + BLNE reg2_error_loop + CMP R14, #0xEE000000 + BLNE reg2_error_loop + + /* Everything passed, increment the loop counter. */ + PUSH { R0-R1 } + LDR R0, =loopCounter + LDR R1, [R0, #+0x4] + ADD R1, R1, #1 + STR R1, [R0, #+0x4] + POP { R0-R1 } + + /* Delay for 0x200 ticks before running again. */ + PUSH { R0-R4, R12, R14 } + MOV R0, #0x200 + BLX vTaskDelay + POP { R0-R4, R12, R14 } + + /* Start again. */ + B reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + B reg2_error_loop + NOP + +/* End of file. */ +.end + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml new file mode 100644 index 00000000000..6b3299f439d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/RM57L8xx.ccxml @@ -0,0 +1,14 @@ + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt new file mode 100644 index 00000000000..d783fef4d6a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_No_GIC_R5F_TI_RM57_HERCULES_GCC/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file From c8dc86afc3a0b373d5cfef81156dfec2bb00f6af Mon Sep 17 00:00:00 2001 From: Rahul Kar <118818625+kar-rahul-aws@users.noreply.github.com> Date: Wed, 14 Aug 2024 11:56:38 +0530 Subject: [PATCH 14/15] Remove ipLOCAL_MAC_ADDRESS from demo files (#1244) * Remove ipLOCAL_MAC_ADDRESS from demo files * Add return variable for IP_Init fucntions --- .../Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c | 9 +++++---- .../FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c | 6 ++++-- .../IPv6_Multi_WinSim_demo/main.c | 5 ++++- .../main.c | 9 ++++++--- .../FreeRTOS+TCP/plus_tcp_hooks_winsim.c | 2 +- 5 files changed, 20 insertions(+), 11 deletions(-) diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c index 8fde5343f51..42563624dd4 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Posix/main_networking.c @@ -135,6 +135,7 @@ static UBaseType_t ulNextRand; void main_tcp_echo_client_tasks( void ) { + BaseType_t xResult; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -157,8 +158,6 @@ void main_tcp_echo_client_tasks( void ) /* Initialise the network interface.*/ FreeRTOS_debug_printf( ( "FreeRTOS_IPInit\r\n" ) ); - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - #if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) extern NetworkInterface_t * pxLibslirp_FillInterfaceDescriptor( BaseType_t xEMACIndex, NetworkInterface_t * pxInterface ); @@ -173,12 +172,14 @@ void main_tcp_echo_client_tasks( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - FreeRTOS_IPInit_Multi(); + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xResult = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xResult == pdTRUE ); + /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\n" ) ); vTaskStartScheduler(); diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c index 60e5ca36402..dd964506011 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_Echo_Qemu_mps2/main_networking.c @@ -140,6 +140,7 @@ static UBaseType_t ulNextRand; void main_tcp_echo_client_tasks( void ) { + BaseType_t xReturn; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -180,12 +181,13 @@ void main_tcp_echo_client_tasks( void ) } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - FreeRTOS_IPInit_Multi(); + xReturn = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xReturn = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xReturn == pdTRUE ); /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\n" ) ); diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c index eeeb0a88e6b..62ba4277f51 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_IPv6_Demo/IPv6_Multi_WinSim_demo/main.c @@ -189,6 +189,7 @@ NetworkInterface_t * pxWinPcap_FillInterfaceDescriptor( BaseType_t xEMACIndex, int main( void ) { + BaseType_t xReturn; const uint32_t ulLongTime_ms = pdMS_TO_TICKS( 1000UL ); /* @@ -314,7 +315,9 @@ int main( void ) } #endif /* ( mainNETWORK_UP_COUNT >= 3U ) */ - FreeRTOS_IPInit_Multi(); + xReturn = FreeRTOS_IPInit_Multi(); + + configASSERT( xReturn == pdTRUE ); /* Start the RTOS scheduler. */ FreeRTOS_debug_printf( ( "vTaskStartScheduler\r\n" ) ); diff --git a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c index 1f7ff80b924..1626361c4a4 100644 --- a/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c +++ b/FreeRTOS-Plus/Demo/FreeRTOS_Plus_TCP_UDP_Mode_CLI_Windows_Simulator/main.c @@ -130,6 +130,7 @@ static UBaseType_t ulNextRand; int main( void ) { + BaseType_t xResult; const uint32_t ulLongTime_ms = 250UL; /* Create a mutex that is used to guard against the console being accessed @@ -157,13 +158,15 @@ int main( void ) xEndPoints[ 0 ].bits.bWantDHCP = pdTRUE; } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); - FreeRTOS_IPInit_Multi(); + + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ - FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); + xResult = FreeRTOS_IPInit( ucIPAddress, ucNetMask, ucGatewayAddress, ucDNSServerAddress, ucMACAddress ); #endif /* defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ + configASSERT( xResult == pdTRUE ); + /* Initialise the logging. */ uint32_t ulLoggingIPAddress; diff --git a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c index 2529592cac9..92d08fc5d7f 100644 --- a/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c +++ b/FreeRTOS-Plus/VisualStudio_StaticProjects/FreeRTOS+TCP/plus_tcp_hooks_winsim.c @@ -228,7 +228,7 @@ void vPlatformInitIpStack( void ) xEndPoints[ 0 ].bits.bWantDHCP = pdTRUE; } #endif /* ( ipconfigUSE_DHCP != 0 ) */ - memcpy( ipLOCAL_MAC_ADDRESS, ucMACAddress, sizeof( ucMACAddress ) ); + xResult = FreeRTOS_IPInit_Multi(); #else /* if defined( ipconfigIPv4_BACKWARD_COMPATIBLE ) && ( ipconfigIPv4_BACKWARD_COMPATIBLE == 0 ) */ /* Using the old /single /IPv4 library, or using backward compatible mode of the new /multi library. */ From 404ad81d9d280af2dabcf420f85f2bb3cbcafc07 Mon Sep 17 00:00:00 2001 From: Monika Singh Date: Tue, 13 Aug 2024 14:29:46 +0000 Subject: [PATCH 15/15] Fix doxygen link --- .github/workflows/ci.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 99122b7e3e9..8c50e566902 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -81,7 +81,7 @@ jobs: # Therefore, we can just download it. mkdir -p freertos/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent/source/dependency/coreMQTT/docs/doxygen/output wget -O freertos/FreeRTOS-Plus/Source/Application-Protocols/coreMQTT-Agent/source/dependency/coreMQTT/docs/doxygen/output/mqtt.tag \ - "https://freertos.org/Documentation/api-ref/coreMQTT/docs/doxygen/output/mqtt.tag" + "https://freertos.github.io/coreMQTT/main/mqtt.tag" - name: Generate doxygen ZIP uses: FreeRTOS/CI-CD-Github-Actions/doxygen@main