diff --git a/.gitignore b/.gitignore
index b419f14..9fc29cf 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,3 +35,5 @@
 
 # matlab storage files
 *.mat
+
+build
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..37dcde0
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,133 @@
+# Use := where you can, as it only gets evaluated once
+BUILD := build
+
+# Load previous values of variables
+VARS := $(foreach VAR,$(wildcard $(BUILD)/*.var),$(basename $(notdir $(VARIABLE))))
+$(foreach VAR,$(VARS),$(eval $(VAR) ?= $(shell cat $(BUILD)/$(VAR).var)))
+
+BOARD ?= Lattice/ICE40HX1K-STICK-EVN
+include boards/$(BOARD)/cfg
+FAMILY := $(strip $(subst lp,,$(subst hx,, $(subst up,,$(DEVICE)))))
+# List of variables set by the board cfg
+# We don't just use VARS since this could be the first run,
+# so some of these variables may not have a .var file
+BOARD_VARS := DEVICE PACKAGE LEDS BUTS CLOCK
+BOARD_DEFINES := $(foreach VAR,$(BOARD_VARS),$(and $($(VAR)),-D$(VAR)=$($(VAR))))
+
+ifdef VERBOSE
+Q :=
+else
+Q :=1
+endif
+
+PNR ?= arachne-pnr
+SYNTH ?= yosys
+FLASH ?= iceprog
+
+# Necessary so VPATH doesn't get reinterpreted
+VPATH :=
+MODULES := uart blank blinky passthrough
+
+# SRC holds all source files
+SRC :=
+
+.PHONY: all clean burn-% time-% test-% cov-% FORCE
+
+all:
+
+$(BUILD):
+	mkdir -p $@
+
+# First pattern rule creates a .blif from a .v
+# We also have an order-only prerequisite on the build dir
+# This means it must be created first, but make doesn't care if it's out-of-date
+# The timestamp of a directory changes whenever a file within it is created
+# So if we didn't ignore it, we would build everything three times
+# Quick introduction to make variables:
+# $@ current target, what goes to the left of a make rule
+# $< First dependency
+# $^ all non-order-only dependencies
+# $* the stem of an implicit rule -- what % matches in %.blif
+$(BUILD)/%.blif: %.v | $(BUILD)
+	$(SYNTH) $(and $(Q),-q) -p "read_verilog -noautowire $(BOARD_DEFINES) $^; synth_ice40 -top $* -blif $@"
+
+# .PHONY causes targets to be rebuilt every make, and built even if there is an up-to-date file
+# Depending on a .PHONY target will cause the rule to be run every time
+# but make will pay attention to timestamps and not run further dependencies if the target doesn't get updated
+FORCE:
+
+# We are going to exploit that here to make sure we rebuild if the user changes the value of DEVICE
+# We compare the current value of the variable to what is in env
+# If they are different, we update the file
+# If they are the same we don't
+# Anything which depends on $(BUILD)/DEVICE.var will only update if DEVICE changes
+$(BUILD)/%.var: FORCE | $(BUILD)
+	@echo "$($*)" | cmp -s - "$@" || echo "$($*)" > $@
+
+# Keep .var file around even though they are intermediate targets
+.PRECIOUS: $(BUILD)/%.var
+
+$(BUILD)/%: %
+	ln -f $< $@
+
+# Note that yosys does not run if you only change DEVICE, just things from here down
+%.asc: %.blif boards/$(BOARD)/pcf $(BUILD)/FAMILY.var $(BUILD)/PACKAGE.var $(BUILD)/BOARD.var $(BUILD)/PNR.var
+	$(PNR) $(and $(Q),-q) -d $(FAMILY) -P $(PACKAGE) -p boards/$(BOARD)/pcf -o $@ $<
+
+%.bin: %.asc
+	icepack $< $@
+
+burn-%: $(BUILD)/%.bin $(BUILD)/FLASH.var
+	$(FLASH) $<
+
+time-%: $(BUILD)/%.asc boards/$(BOARD)/pcf $(BUILD)/DEVICE.var $(BUILD)/PACKAGE.var $(BUILD)/BOARD.var
+	icetime -t -d $(DEVICE) -P $(PACKAGE) -p boards/$(BOARD)/pcf $<
+
+clean:
+	rm -rf $(BUILD)
+
+include $(addsuffix /Makefile,$(MODULES))
+
+# The following snippet Copyright 2003-2019 by Wilson Snyder, 2019 Sean Anderson
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+
+VERILATOR ?= verilator
+VERILATOR_COVERAGE ?= verilator_coverage
+# Generate C++ in executable form
+VERILATOR_FLAGS += -cc --exe
+# Optimize
+VERILATOR_FLAGS += -O2 -x-assign 0
+# Warn abount lint issues; may not want this on less solid designs
+VERILATOR_FLAGS += -Wall
+# Make waveforms
+VERILATOR_FLAGS += --trace
+# Check SystemVerilog assertions
+VERILATOR_FLAGS += --assert
+# Generate coverage analysis
+VERILATOR_FLAGS += --coverage
+# end snippet
+
+# Similar to BOARD_DEFINES, but we need to be careful to remove non-c-friendly characters
+# signed numbers are NOT supported
+sanitize = $(lastword $(subst 'h,' 0x,$(subst 'd,' ,$(subst _,,$1))))
+export USER_CPPFLAGS := $(foreach VAR,$(BOARD_VARS),$(and $($(VAR)),-D$(VAR)=$(call sanitize,$($(VAR)))))
+
+$(BUILD)/test-%:
+	mkdir -p $@
+
+test-%: | $(BUILD)/test-%
+	$(VERILATOR) $(VERILATOR_FLAGS) $$(echo "$(BOARD_DEFINES)") -Mdir $(BUILD)/test-$* --prefix $* $^
+	$(MAKE) -C $(BUILD)/test-$* -f $*.mk
+	$(BUILD)/test-$*/$* +trace
+
+cov-%: test-%
+	$(VERILATOR_COVERAGE) --annotate $(BUILD)/test-$*/logs/annotated $(BUILD)/test-$*/logs/coverage.dat
+
+# Because our sources/pinmaps depend on the makefile
+# all targets will get rebuilt every time the makefile changes
+# Additionally, we need to depend on BOARD
+# (and SYNTH/VERILATOR* since this is the only place to put it)
+$(SRC): Makefile $(BUILD)/BOARD.var $(BUILD)/SYNTH.var $(BUILD)/VERILATOR.var $(BUILD)/VERILATOR_COVERAGE.var
+	@touch $@
diff --git a/README.md b/README.md
index aa3b044..517df9a 100644
--- a/README.md
+++ b/README.md
@@ -112,14 +112,15 @@ https://www.dropbox.com/s/3qgiq0j6qj3910f/keypad_instructions.pdf?dl=0
 
 ## Downloading, compiling, and programming the example projects
 In order to download this repository, type `git clone https://github.com/nesl/ice40_examples.git ice40_examples` on the command line. Within the repository you will find a GPL license file, this readme, and several different example project folders such as "blinky." Within a given project folder, you will see:
-* top.v -- the highest level Verilog file, including all pin inputs (e.g. clocks and button lines) and outputs (e.g. LEDs)
-* (other modules.v) -- any other required modules (e.g. UART transmitters) referenced in top.v
-* pinmap.pcf -- the pin map file relating variable names referenced in top.v to physical I/O pins on the ICE40 HX8K. The syntax here is `set_io <wire_name> <physical pin name>`.  You can add the `--warn-no-port` option if you'd like the compiler to warn you if a specified pin does not exist on a given device.
-* Makefile -- this is a typical Unix Makefile that dictates the synthesis and programming flow. For the example projects, this file provides two commands of interest: `make` and `make burn`. `make` will compile your verilog project into a binary bitstream, and `make burn` will download this bitstream onto your FPGA device through USB. 
-* build/ -- this is a folder where all intermediate build files are stored -- e.g. netlists, ascii bitstream, binary bistream. 
+* `<folder_name>.v` -- the highest level Verilog file, including all pin inputs (e.g. clocks and button lines) and outputs (e.g. LEDs)
+* (`other_modules.v`) -- any other required modules (e.g. UART transmitters) referenced in `<folder_name>.v`
+* `<folder_name>_<footprint>.pcf` -- the pin map file relating variable names referenced in `<folder_name>.v` to physical I/O pins on the ICE40 HX8K. The syntax here is `set_io <wire_name> <physical pin name>`.  You can add the `--warn-no-port` option if you'd like the compiler to warn you if a specified pin does not exist on a given device.
+* `Makefile` -- this is a sub-makefile which is included by the top-level makefile, but can also be used on its own. For the example projects, this file provides two commands of interest: `make` and `make burn`. `make` will compile your verilog project into a binary bitstream, and `make burn` will download this bitstream onto your FPGA device through USB. 
 
 In order to compile an example project, navigate to that directory on your terminal.  Type `make` to compile the project. When this finishes, type `make burn` to load the compiled binary onto your FPGA, provided it's connected over USB.
 
+You can also type `make` in the top directory to compile all projects. To load a project onto your FPGA, use `make burn-<project>`.
+
 Note for OSX: If you are having difficulties programming a project onto the FPGA with `make burn`, see the section below on UART transmission under the UART project. 
 
 ## Example Projects List
@@ -160,12 +161,12 @@ If on a Windows machine (for viewing purposes only--i.e. this does not apply if
 
 ## Project Design Process:
 In order to create your own project, start by copying the template provided in the blank project folder.  The general design process looks like this:
-1.  Write your top-level Verilog code in top.v. Any additional Verilog files required can be placed at the same level as top.v (in the project folder).
+1.  Write your top-level Verilog code in `<module>.v`. Any additional Verilog files required can be placed at the same level as `<module>.v` (in the project folder).
 
-2.  Modify your Makefile: change `PROJ` to be your project name, and if any additional Verilog files are required, they should follow the `FILES = top.v` line, using the format `FILES += newfile.v` where `newfile.v` is the name of any additional Verilog file you have written. You can use this syntax for however many files you need. 
+2.  Modify your Makefile: update the `MODULE` variable (this doesn't need to match the folder name, but does need to be unique across all modules). If any additional Verilog files are required, they should be added to `M_VSRC`. Remember to separate each file with spaces. Any other source files (including pcf files) should be added to `M_SRC`.
 
-3.  Modify pinmap.pcf. If any pins are required other than the input clock and LEDs, add a line to the pinmap.pcf file using the format `set_io --warn-no-port <wire_name> <physical pin name>`.
+3.  Modify `<project>_<footprint>.pcf`. `<footprint>` should be the package for your chip which is passed do `arachne-pnr`. The iCE40-HX8K-CT256 uses `ct256`, and the iCE40-HX1K-TQ144 uses `tq144`. For a full list of supported packages, see [the icestorm documentation](http://www.clifford.at/icestorm/#flags). If any pins are required other than the input clock and LEDs, add a line to the file using the format `set_io --warn-no-port <wire_name> <physical pin name>`.
 
-4.  Compile your project by running `make` from the project directory
+4.  Compile your project by running `make` from either the project or top-level directory.
 
-5.  If your project successfully compiles, connect your FPGA over USB and type `make burn` to program the binary to your FPGA. 
+5.  If your project successfully compiles, connect your FPGA over USB and type `make burn` from the project directory, or `make burn-<module>` from the top-level directory to program the binary to your FPGA. 
diff --git a/blank/.gitignore b/blank/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/blank/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/blank/Makefile b/blank/Makefile
index 8a1f8ac..dc564b0 100644
--- a/blank/Makefile
+++ b/blank/Makefile
@@ -1,26 +1,4 @@
-# Project setup
-PROJ      = blank
-BUILD     = ./build
-DEVICE    = 8k
-FOOTPRINT = ct256
+MODULE := blank
+M_VSRC := blank.v
 
-# Files
-FILES = top.v
-
-.PHONY: all clean burn
-
-all:
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:
-	iceprog $(BUILD)/$(PROJ).bin
-
-clean:
-	rm build/*
+include $(realpath $(dir $(lastword $(MAKEFILE_LIST))))/../common.mk
diff --git a/blank/blank.v b/blank/blank.v
new file mode 100644
index 0000000..7cc8708
--- /dev/null
+++ b/blank/blank.v
@@ -0,0 +1,8 @@
+// Blink an LED provided an input clock
+/* module */
+module blank (hwclk, led);
+    /* I/O */
+    input hwclk;
+    output [`LEDS - 1:0] led;
+
+endmodule
diff --git a/blank/pinmap.pcf b/blank/pinmap.pcf
deleted file mode 100644
index aded2bf..0000000
--- a/blank/pinmap.pcf
+++ /dev/null
@@ -1,10 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
\ No newline at end of file
diff --git a/blank/top.v b/blank/top.v
deleted file mode 100644
index 130b3da..0000000
--- a/blank/top.v
+++ /dev/null
@@ -1,15 +0,0 @@
-// Blink an LED provided an input clock
-/* module */
-module top (hwclk, led1, led2, led3, led4, led5, led6, led7, led8 );
-    /* I/O */
-    input hwclk;
-    output led1;
-    output led2;
-    output led3;
-    output led4;
-    output led5;
-    output led6;
-    output led7;
-    output led8;
-
-endmodule
diff --git a/blinky/.gitignore b/blinky/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/blinky/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/blinky/Makefile b/blinky/Makefile
index 4f906f7..7ae39c2 100644
--- a/blinky/Makefile
+++ b/blinky/Makefile
@@ -1,26 +1,4 @@
-# Project setup
-PROJ      = blinky
-BUILD     = ./build
-DEVICE    = 8k
-FOOTPRINT = ct256
+MODULE := blinky
+M_VSRC := blinky.v
 
-# Files
-FILES = top.v
-
-.PHONY: all clean burn
-
-all:
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:
-	iceprog $(BUILD)/$(PROJ).bin
-
-clean:
-	rm build/*
+include $(realpath $(dir $(lastword $(MAKEFILE_LIST))))/../common.mk
diff --git a/blinky/blinky.v b/blinky/blinky.v
new file mode 100644
index 0000000..6ccd4e9
--- /dev/null
+++ b/blinky/blinky.v
@@ -0,0 +1,23 @@
+// Blink an LED provided an input clock
+
+/* module */
+module blinky (hwclk, led);
+    input hwclk;
+    output reg [`LEDS - 1:0] led;
+
+    /*
+     * led[`LEDS-1] should blink at 1hz
+     * the *switching* speed should be 2 hz
+     */
+    parameter cycles = `CLOCK / (2 * `LEDS);
+    reg [32:0] counter = 32'b0;
+
+    always @ (posedge hwclk) begin
+	if (counter == cycles) begin
+		led <= led + 1;
+		counter <= 32'b0;
+	end else
+		counter <= counter + 1;
+    end
+
+endmodule
diff --git a/blinky/pinmap.pcf b/blinky/pinmap.pcf
deleted file mode 100644
index aded2bf..0000000
--- a/blinky/pinmap.pcf
+++ /dev/null
@@ -1,10 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
\ No newline at end of file
diff --git a/blinky/top.v b/blinky/top.v
deleted file mode 100644
index f4e8585..0000000
--- a/blinky/top.v
+++ /dev/null
@@ -1,33 +0,0 @@
-// Blink an LED provided an input clock
-/* module */
-module top (hwclk, led1, led2, led3, led4, led5, led6, led7, led8 );
-    /* I/O */
-    input hwclk;
-    output led1;
-    output led2;
-    output led3;
-    output led4;
-    output led5;
-    output led6;
-    output led7;
-    output led8;
-
-    /* Counter register */
-    reg [31:0] counter = 32'b0;
-
-    /* LED drivers */
-    assign led1 = counter[18];
-    assign led2 = counter[19];
-    assign led3 = counter[20];
-    assign led4 = counter[21];
-    assign led5 = counter[22];
-    assign led6 = counter[23];
-    assign led7 = counter[24];
-    assign led8 = counter[25];
-
-    /* always */
-    always @ (posedge hwclk) begin
-        counter <= counter + 1;
-    end
-
-endmodule
\ No newline at end of file
diff --git a/boards/Lattice/ICE40HX1K-STICK-EVN/cfg b/boards/Lattice/ICE40HX1K-STICK-EVN/cfg
new file mode 100644
index 0000000..f69d3c5
--- /dev/null
+++ b/boards/Lattice/ICE40HX1K-STICK-EVN/cfg
@@ -0,0 +1,5 @@
+DEVICE := hx1k
+PACKAGE := tq144
+LEDS := 5
+BUTS :=
+CLOCK := 32'd12_000_000
diff --git a/boards/Lattice/ICE40HX1K-STICK-EVN/pcf b/boards/Lattice/ICE40HX1K-STICK-EVN/pcf
new file mode 100644
index 0000000..fc2fdd7
--- /dev/null
+++ b/boards/Lattice/ICE40HX1K-STICK-EVN/pcf
@@ -0,0 +1,93 @@
+# Copyright 2015 Al Williams, 2019 Sean Anderson
+# 
+#    Licensed under the Apache License, Version 2.0 (the "License");
+#    you may not use this file except in compliance with the License.
+#    You may obtain a copy of the License at
+# 
+#        http://www.apache.org/licenses/LICENSE-2.0
+# 
+#    Unless required by applicable law or agreed to in writing, software
+#    distributed under the License is distributed on an "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#    See the License for the specific language governing permissions and
+#    limitations under the License.
+
+# Generic iCEstick placement constraints file
+
+# 12 MHz clock
+set_io -nowarn iCE_CLK 21
+set_io -nowarn hwclk 21
+
+# Red LEDs
+set_io -nowarn LED0 99
+set_io -nowarn led[0] 99
+set_io -nowarn LED1 98
+set_io -nowarn led[1] 98
+set_io -nowarn LED2 97
+set_io -nowarn led[2] 97
+set_io -nowarn LED3 96
+set_io -nowarn led[3] 96
+
+# Green LED
+set_io -nowarn LED4 95
+set_io -nowarn led[4] 95
+
+# IrDA port
+set_io -nowarn RXD 106
+set_io -nowarn TXD 105
+set_io -nowarn SD 107
+
+# Pmod connector
+set_io -nowarn PIO1_02 78 # Pin 1
+set_io -nowarn PIO1_03 79 # Pin 2
+set_io -nowarn PIO1_04 80 # Pin 3
+set_io -nowarn PIO1_05 81 # Pin 4
+set_io -nowarn PIO1_06 87 # Pin 7
+set_io -nowarn PIO1_07 88 # Pin 8
+set_io -nowarn PIO1_08 90 # Pin 9
+set_io -nowarn PIO1_09 91 # Pin 10
+
+# Connector J1
+set_io -nowarn PIO0_02 112 # Pin 3
+set_io -nowarn PIO0_03 113 # Pin 4
+set_io -nowarn PIO0_04 114 # Pin 5
+set_io -nowarn PIO0_05 115 # Pin 6
+set_io -nowarn PIO0_06 116 # Pin 7
+set_io -nowarn PIO0_07 117 # Pin 8
+set_io -nowarn PIO0_08 118 # Pin 9
+set_io -nowarn PIO0_09 119 # Pin 10
+
+# Connector J3
+set_io -nowarn PIO2_17 62 # Pin 3
+set_io -nowarn PIO2_16 61 # Pin 4
+set_io -nowarn PIO2_15 60 # Pin 5
+set_io -nowarn PIO2_14 56 # Pin 6
+set_io -nowarn PIO2_13 48 # Pin 7
+set_io -nowarn PIO2_12 47 # Pin 8
+set_io -nowarn PIO2_11 45 # Pin 9
+set_io -nowarn PIO2_10 44 # Pin 10
+
+# FTDI Port B UART
+set_io -nowarn DCDn 1
+set_io -nowarn DSRn 2
+set_io -nowarn DTRn 3
+set_io -nowarn CTSn 4
+set_io -nowarn RTSn 7
+set_io -nowarn RS232_Tx_TTL 8
+set_io -nowarn uart_tx 8
+set_io -nowarn RS232_Rx_TTL 9
+set_io -nowarn uart_rx 9
+
+# SPI
+set_io -nowarn iCE_SCK 70
+set_io -nowarn sck 70
+set_io -nowarn iCE_MISO 68
+set_io -nowarn sdi 68
+set_io -nowarn iCE_MOSI 67
+set_io -nowarn sdo 67
+set_io -nowarn iCE_SS_B 71
+set_io -nowarn ss 71
+
+# Configuration pins
+set_io -nowarn CDONE 65
+set_io -nowarn CRESET 66
diff --git a/boards/Lattice/ICE40HX8K-B-EVN/cfg b/boards/Lattice/ICE40HX8K-B-EVN/cfg
new file mode 100644
index 0000000..e215e95
--- /dev/null
+++ b/boards/Lattice/ICE40HX8K-B-EVN/cfg
@@ -0,0 +1,5 @@
+DEVICE := hx8k
+PACKAGE := ct256
+LEDS := 8
+BUTS :=
+CLOCK := 32'd12_000_000
diff --git a/boards/Olimex/iCE40HX8K-EVB/cfg b/boards/Olimex/iCE40HX8K-EVB/cfg
new file mode 100644
index 0000000..a6b57ab
--- /dev/null
+++ b/boards/Olimex/iCE40HX8K-EVB/cfg
@@ -0,0 +1,5 @@
+DEVICE := hx8k
+PACKAGE := ct256
+LEDS := 2
+BUTS := 2
+CLOCK := 32'd100_000_000
diff --git a/boards/Olimex/iCE40HX8K-EVB/pcf b/boards/Olimex/iCE40HX8K-EVB/pcf
new file mode 100644
index 0000000..d46edad
--- /dev/null
+++ b/boards/Olimex/iCE40HX8K-EVB/pcf
@@ -0,0 +1,81 @@
+# Whenever possible, pin names have been taken from the official schematic
+# <https://github.com/OLIMEX/iCE40HX8K-EVB/blob/master/HARDWARE/REV-B/iCE40HX8K-EVB_Rev_B.pdf>
+
+# Clock
+set_io -nowarn SYSCLK J3
+set_io -nowarn hwclk J3
+
+# LEDs
+set_io -nowarn LED1 M12
+set_io -nowarn led[0] M12
+set_io -nowarn LED2 R16
+set_io -nowarn led[1] R16
+
+# Buttons
+set_io -nowarn BUT1 K11
+set_io -nowarn but[0] K11
+set_io -nowarn BUT2 P13
+set_io -nowarn but[1] P13
+
+# SPI Flash
+set_io -nowarn iCE40-CDONE M10
+set_io -nowarn iCE40-CRESET N11
+set_io -nowarn iCE40-SDO P12
+set_io -nowarn sdo P12
+set_io -nowarn iCE40-SDI P11
+set_io -nowarn sdi P11
+set_io -nowarn iCE40-SCK R11
+set_io -nowarn sck R11
+set_io -nowarn iCE40-SS_B R12
+set_io -nowarn ss R12
+
+# Programming connector
+set_io -nowarn RxD L11
+set_io -nowarn uart_rx L11
+set_io -nowarn TxD T16
+set_io -nowarn uart_tx T16
+
+# SRAM
+set_io -nowarn SRAM_CS T6
+set_io -nowarn SRAM_OE L9
+set_io -nowarn SRAM_WE T7
+set_io -nowarn SA[0] N6
+set_io -nowarn SA[1] T1
+set_io -nowarn SA[2] P4
+set_io -nowarn SA[3] R2
+set_io -nowarn SA[4] N5
+set_io -nowarn SA[5] T2
+set_io -nowarn SA[6] P5
+set_io -nowarn SA[7] R3
+set_io -nowarn SA[8] R5
+set_io -nowarn SA[9] T3
+set_io -nowarn SA[10] R4
+set_io -nowarn SA[11] M7
+set_io -nowarn SA[12] N7
+set_io -nowarn SA[13] P6
+set_io -nowarn SA[14] M8
+set_io -nowarn SA[15] T5
+set_io -nowarn SA[16] R6
+set_io -nowarn SA[17] P8
+set_io -nowarn SD[0] T8
+set_io -nowarn SD[1] P7
+set_io -nowarn SD[2] N9
+set_io -nowarn SD[3] T9
+set_io -nowarn SD[4] M9
+set_io -nowarn SD[5] R9
+set_io -nowarn SD[6] K9
+set_io -nowarn SD[7] P9
+set_io -nowarn SD[8] R10
+set_io -nowarn SD[9] L10
+set_io -nowarn SD[10] P10
+set_io -nowarn SD[11] N10
+set_io -nowarn SD[12] T10
+set_io -nowarn SD[13] T11
+set_io -nowarn SD[14] T15
+set_io -nowarn SD[15] T14
+
+# JTAG
+set_io -nowarn TDI R14
+set_io -nowarn TMS R15
+set_io -nowarn TCK P14
+set_io -nowarn TDO P15
diff --git a/buttons_bounce/.gitignore b/buttons_bounce/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/buttons_bounce/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/buttons_bounce/Makefile b/buttons_bounce/Makefile
deleted file mode 100644
index 894e38f..0000000
--- a/buttons_bounce/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-# Project setup
-PROJ      = buttons
-BUILD     = ./build
-DEVICE    = 8k
-FOOTPRINT = ct256
-
-# Files
-FILES = top.v
-
-.PHONY: all clean burn
-
-all:
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:
-	iceprog $(BUILD)/$(PROJ).bin
-
-clean:
-	rm build/*
diff --git a/buttons_bounce/pinmap.pcf b/buttons_bounce/pinmap.pcf
deleted file mode 100644
index a1e80fd..0000000
--- a/buttons_bounce/pinmap.pcf
+++ /dev/null
@@ -1,18 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
-
-# NUMPAD pins (note: r4 is gnd, can't use)
-set_io --warn-no-port keypad_r1 J15
-set_io --warn-no-port keypad_r2 G14
-set_io --warn-no-port keypad_r3 K14
-set_io --warn-no-port keypad_c1 K15
-set_io --warn-no-port keypad_c2 M16
-set_io --warn-no-port keypad_c3 N16
\ No newline at end of file
diff --git a/buttons_bounce/top.v b/buttons_bounce/top.v
deleted file mode 100644
index 640e6f0..0000000
--- a/buttons_bounce/top.v
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Top level module for button demo without debouncing
-   (not a good way of doing things!)
-   This uses button 1 of the keypad when installed correctly.
-   */
-module top (
-    // input hardware clock (12 MHz)
-    hwclk, 
-    // LED
-    led1,
-    // Keypad lines
-    keypad_r1,
-    keypad_c1,
-    );
-
-    /* Clock input */
-    input hwclk;
-
-    /* LED outputs */
-    output led1;
-
-    /* Numpad I/O */
-    output keypad_r1=0;
-    input keypad_c1;
-
-    /* LED register */
-    reg ledval = 1'b0;
-
-    /* Numpad pull-up settings for columns:
-       PIN_TYPE: <output_type=0>_<input=1>
-       PULLUP: <enable=1>
-       PACKAGE_PIN: <user pad name>
-       D_IN_0: <internal pin wire (data in)>
-    */
-    wire keypad_c1_din;
-    SB_IO #(
-        .PIN_TYPE(6'b0000_01),
-        .PULLUP(1'b1)
-    ) keypad_c1_config (
-        .PACKAGE_PIN(keypad_c1),
-        .D_IN_0(keypad_c1_din)
-    );
-
-    /* LED Wiring */
-    assign led1=ledval;
-    
-    /* Toggle LED when button [1] pressed */
-    always @ (negedge keypad_c1_din) begin
-        ledval = ~ledval;
-    end
-
-
-endmodule
\ No newline at end of file
diff --git a/buttons_debounce/.gitignore b/buttons_debounce/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/buttons_debounce/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/buttons_debounce/Makefile b/buttons_debounce/Makefile
deleted file mode 100644
index 894e38f..0000000
--- a/buttons_debounce/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-# Project setup
-PROJ      = buttons
-BUILD     = ./build
-DEVICE    = 8k
-FOOTPRINT = ct256
-
-# Files
-FILES = top.v
-
-.PHONY: all clean burn
-
-all:
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:
-	iceprog $(BUILD)/$(PROJ).bin
-
-clean:
-	rm build/*
diff --git a/buttons_debounce/pinmap.pcf b/buttons_debounce/pinmap.pcf
deleted file mode 100644
index a1e80fd..0000000
--- a/buttons_debounce/pinmap.pcf
+++ /dev/null
@@ -1,18 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
-
-# NUMPAD pins (note: r4 is gnd, can't use)
-set_io --warn-no-port keypad_r1 J15
-set_io --warn-no-port keypad_r2 G14
-set_io --warn-no-port keypad_r3 K14
-set_io --warn-no-port keypad_c1 K15
-set_io --warn-no-port keypad_c2 M16
-set_io --warn-no-port keypad_c3 N16
\ No newline at end of file
diff --git a/buttons_debounce/top.v b/buttons_debounce/top.v
deleted file mode 100644
index d00fe0d..0000000
--- a/buttons_debounce/top.v
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Top level module for button demo WITH debouncing
-   This uses button 1 of the keypad when installed correctly.
-   */
-module top (
-    // input hardware clock (12 MHz)
-    hwclk, 
-    // LED
-    led1,
-    // Keypad lines
-    keypad_r1,
-    keypad_c1,
-    );
-
-    /* Clock input */
-    input hwclk;
-
-    /* LED outputs */
-    output led1;
-
-    /* Numpad I/O */
-    output keypad_r1=0;
-    input keypad_c1;
-
-    /* LED register */
-    reg ledval = 1'b0;
-
-    /* Numpad pull-up settings for columns:
-       PIN_TYPE: <output_type=0>_<input=1>
-       PULLUP: <enable=1>
-       PACKAGE_PIN: <user pad name>
-       D_IN_0: <internal pin wire (data in)>
-    */
-    wire keypad_c1_din;
-    SB_IO #(
-        .PIN_TYPE(6'b0000_01),
-        .PULLUP(1'b1)
-    ) keypad_c1_config (
-        .PACKAGE_PIN(keypad_c1),
-        .D_IN_0(keypad_c1_din)
-    );
-
-    /* Debouncing timer and period = 10 ms */
-    reg [31:0] debounce_timer = 32'b0;
-    parameter DEBOUNCE_PERIOD = 32'd120000;
-    reg debouncing = 1'b0;
-
-    /* LED Wiring */
-    assign led1=ledval;
-
-    /* Our high speed clock will deal with debounce timing */
-    always @ (posedge hwclk) begin
-        // check for button presses
-        if (~debouncing && ~keypad_c1_din) begin
-            ledval <= ~ledval;
-            debouncing <= 1;
-        // reset debouncing if button is held low
-        end else if (debouncing && ~keypad_c1_din) begin
-            debounce_timer <= 32'b0;
-        // or if it's high, increment debounce timer
-        end else if (debouncing && debounce_timer < DEBOUNCE_PERIOD) begin
-            debounce_timer <= debounce_timer + 1;
-        // finally, if it's high and timer expired, debouncing done!
-        end else if (debouncing) begin
-            debounce_timer <= 32'b0;
-            debouncing <= 1'b0;
-        end
-    end
-
-
-endmodule
\ No newline at end of file
diff --git a/buttons_nopullup/.gitignore b/buttons_nopullup/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/buttons_nopullup/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/buttons_nopullup/Makefile b/buttons_nopullup/Makefile
deleted file mode 100644
index 894e38f..0000000
--- a/buttons_nopullup/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-# Project setup
-PROJ      = buttons
-BUILD     = ./build
-DEVICE    = 8k
-FOOTPRINT = ct256
-
-# Files
-FILES = top.v
-
-.PHONY: all clean burn
-
-all:
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:
-	iceprog $(BUILD)/$(PROJ).bin
-
-clean:
-	rm build/*
diff --git a/buttons_nopullup/pinmap.pcf b/buttons_nopullup/pinmap.pcf
deleted file mode 100644
index a1e80fd..0000000
--- a/buttons_nopullup/pinmap.pcf
+++ /dev/null
@@ -1,18 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
-
-# NUMPAD pins (note: r4 is gnd, can't use)
-set_io --warn-no-port keypad_r1 J15
-set_io --warn-no-port keypad_r2 G14
-set_io --warn-no-port keypad_r3 K14
-set_io --warn-no-port keypad_c1 K15
-set_io --warn-no-port keypad_c2 M16
-set_io --warn-no-port keypad_c3 N16
\ No newline at end of file
diff --git a/buttons_nopullup/top.v b/buttons_nopullup/top.v
deleted file mode 100644
index e6cc188..0000000
--- a/buttons_nopullup/top.v
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Top level module for button demo without debouncing and with no
-   pull-up resistor (not a good way of doing things!)
-   */
-module top (
-    // input hardware clock (12 MHz)
-    hwclk, 
-    // LED
-    led1,
-    // Keypad lines
-    keypad_r1,
-    keypad_c1,
-    );
-
-    /* Clock input */
-    input hwclk;
-
-    /* LED outputs */
-    output led1;
-
-    /* Numpad I/O */
-    output keypad_r1=0;
-    input keypad_c1;
-
-    // Note: Left as is, keypad_c1 is a floating value, meaning
-    // it has an undetermined voltage. It will trigger edges when
-    // we don't want it to.
-
-    /* LED register */
-    reg ledval = 1'b0;
-
-    /* LED Wiring */
-    assign led1=ledval;
-    
-    /* Toggle LED when button [1] pressed */
-    always @ (negedge keypad_c1) begin
-        ledval = ~ledval;
-    end
-
-
-endmodule
\ No newline at end of file
diff --git a/common.mk b/common.mk
new file mode 100644
index 0000000..a8286a3
--- /dev/null
+++ b/common.mk
@@ -0,0 +1,33 @@
+# Really ugly, but make can't decrement so we get this...
+getincluder = $(word $(words $(wordlist 2,$(words $1),$1)),$1)
+DIR := $(dir $(call getincluder,$(MAKEFILE_LIST)))
+
+ifndef BUILD
+.PHONY: all burn clean
+
+all:
+	$(MAKE) -C .. $(MODULE)
+
+burn:
+	$(MAKE) -C .. burn-$(MODULE)
+
+clean:
+	$(MAKE) -C .. $@
+endif
+
+VPATH += $(DIR)
+
+M_VSRC := $(addprefix $(DIR),$(M_VSRC))
+M_CSRC := $(addprefix $(DIR),$(M_CSRC))
+SRC += $(M_VSRC) $(M_CSRC)
+
+.PHONY: $(MODULE)
+$(MODULE): $(BUILD)/$(MODULE).bin
+
+$(BUILD)/$(MODULE).blif: $(M_VSRC)
+
+test-$(MODULE): $(M_VSRC) $(M_CSRC)
+
+ifdef BUILD
+all: $(MODULE)
+endif
diff --git a/fsm_simple/.gitignore b/fsm_simple/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/fsm_simple/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/fsm_simple/Makefile b/fsm_simple/Makefile
deleted file mode 100644
index 8320eb9..0000000
--- a/fsm_simple/Makefile
+++ /dev/null
@@ -1,27 +0,0 @@
-# Project setup
-PROJ      = fsm
-BUILD     = ./build
-DEVICE    = 8k
-FOOTPRINT = ct256
-
-# Files
-FILES = top.v
-FILES += button.v
-
-.PHONY: all clean burn
-
-all:
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap.pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:
-	iceprog $(BUILD)/$(PROJ).bin
-
-clean:
-	rm build/*
diff --git a/fsm_simple/button.v b/fsm_simple/button.v
deleted file mode 100644
index f78119b..0000000
--- a/fsm_simple/button.v
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Simple button module */
-module button (
-    // input clock
-    clk,
-    // I/O pins
-    pin_in,
-    press,
-    );
-
-    input clk;
-    input pin_in;
-    output press;
-
-    /* Pull-up settings for input:
-       PIN_TYPE: <output_type=0>_<input=1>
-       PULLUP: <enable=1>
-       PACKAGE_PIN: <user pad name>
-       D_IN_0: <internal pin wire (data in)>
-    */
-    wire pin_din;
-    SB_IO #(
-        .PIN_TYPE(6'b0000_01),
-        .PULLUP(1'b1)
-    ) pin_in_config (
-        .PACKAGE_PIN(pin_in),
-        .D_IN_0(pin_din)
-    );
-
-    /* Debouncing timer and period = 10 ms */
-    reg [31:0] debounce_timer = 32'b0;
-    parameter DEBOUNCE_PERIOD = 32'd120000;
-    reg debouncing = 1'b0;
-    reg buttonpress = 1'b0;
-    assign press = buttonpress;
-
-    /* Our high speed clock will deal with debounce timing */
-    always @ (posedge clk) begin
-        // check for button presses
-        if (~debouncing && ~pin_din) begin
-            buttonpress <= 1;
-            debouncing <= 1;
-        // reset debouncing if button is held low
-        end else if (debouncing && ~pin_din) begin
-            debounce_timer <= 32'b0;
-        // or if it's high, increment debounce timer
-        end else if (debouncing && debounce_timer < DEBOUNCE_PERIOD) begin
-            debounce_timer <= debounce_timer + 1;
-        // finally, if it's high and timer expired, debouncing done!
-        end else if (debouncing) begin
-            debounce_timer <= 32'b0;
-            debouncing <= 1'b0;
-            buttonpress <= 0;
-        end
-    end
-
-
-endmodule
\ No newline at end of file
diff --git a/fsm_simple/pinmap.pcf b/fsm_simple/pinmap.pcf
deleted file mode 100644
index a1e80fd..0000000
--- a/fsm_simple/pinmap.pcf
+++ /dev/null
@@ -1,18 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
-
-# NUMPAD pins (note: r4 is gnd, can't use)
-set_io --warn-no-port keypad_r1 J15
-set_io --warn-no-port keypad_r2 G14
-set_io --warn-no-port keypad_r3 K14
-set_io --warn-no-port keypad_c1 K15
-set_io --warn-no-port keypad_c2 M16
-set_io --warn-no-port keypad_c3 N16
\ No newline at end of file
diff --git a/fsm_simple/top.v b/fsm_simple/top.v
deleted file mode 100644
index 38bc28a..0000000
--- a/fsm_simple/top.v
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Top level module for button demo WITH debouncing
-   This uses button 1 of the keypad when installed correctly.
-   */
-module top (
-    // input hardware clock (12 MHz)
-    hwclk, 
-    // LED
-    led1,
-    led2,
-    led3,
-    // Keypad lines
-    keypad_r1,
-    keypad_c1,
-    keypad_c2,
-    );
-
-    /* Clock input */
-    input hwclk;
-
-    /* LED outputs */
-    output led1;
-    output led2;
-    output led3;
-    reg [2:0] ledvals = 3'b0;
-
-    /* Numpad I/O */
-    output keypad_r1=0;
-    input keypad_c1;
-    input keypad_c2;
-
-    /* Button Modules */
-    wire press1, press2;
-    button button1 (
-        .clk (hwclk),
-        .pin_in (keypad_c1),
-        .press (press1),
-    );
-    button button2 (
-        .clk (hwclk),
-        .pin_in (keypad_c2),
-        .press (press2),
-    );
-
-    /* State variables */
-    parameter STATE_RST = 8'd0;
-    parameter STATE_1    = 8'd1;
-    parameter STATE_12   = 8'd2;
-    parameter STATE_121  = 8'd3;
-    parameter STATE_1211 = 8'd4;
-    reg [7:0] state = STATE_RST;
-    assign led1 = ledvals[0];
-    assign led2 = ledvals[1];
-    assign led3 = ledvals[2];
-
-    wire button_pressed = press1 | press2;
-
-    /* Our high speed clock will deal with the simple FSM */
-    always @ (posedge button_pressed) begin
-        // toggle LEDs
-        if (press1) begin
-            ledvals[0] <= ~ledvals[0];
-        end else begin
-            ledvals[1] <= ~ledvals[1];
-        end
-        case (state)
-            STATE_RST : begin
-                if (press1) begin
-                    state <= STATE_1;
-                    ledvals[2] <= 0;
-                end else begin
-                    state <= STATE_RST;
-                    ledvals[2] <= 0;
-                end
-                end     
-
-            STATE_1 : begin
-                if (press1) begin
-                    state <= STATE_1;
-                    ledvals[2] <= 0;
-                end else begin
-                    state <= STATE_12;
-                    ledvals[2] <= 0;
-                end 
-                end
-            STATE_12 : begin
-                if (press1) begin
-                    state <= STATE_121;
-                    ledvals[2] <= 0;
-                end else begin
-                    state <= STATE_RST;
-                    ledvals[2] <= 0;
-                end
-                end
-            STATE_121 : begin
-                if (press1) begin
-                    state <= STATE_1211;
-                    ledvals[2] <= 1;
-                end else begin
-                    state <= STATE_12;
-                    ledvals[2] <= 0;
-                end
-                end
-            STATE_1211 : begin
-                if (press1) begin
-                    state <= STATE_1;
-                    ledvals[2] <= 0;
-                end else begin
-                    state <= STATE_12;
-                    ledvals[2] <= 0;
-                end
-                end
-            default : begin
-                state <= STATE_RST;
-                ledvals[2] <= 0;
-            end
-        endcase
-    end
-
-endmodule
\ No newline at end of file
diff --git a/passthrough/Makefile b/passthrough/Makefile
new file mode 100644
index 0000000..db61303
--- /dev/null
+++ b/passthrough/Makefile
@@ -0,0 +1,5 @@
+MODULE := passthrough
+M_VSRC := passthrough.v
+M_CSRC := passthrough.cpp
+
+include $(realpath $(dir $(lastword $(MAKEFILE_LIST))))/../common.mk
diff --git a/passthrough/passthrough.cpp b/passthrough/passthrough.cpp
new file mode 100644
index 0000000..52197e9
--- /dev/null
+++ b/passthrough/passthrough.cpp
@@ -0,0 +1,92 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Wilson Snyder.
+//======================================================================
+
+// Include common routines
+#include <verilated.h>
+
+// Include model header, generated from Verilating "tb.v"
+#include "Vtb.h"
+
+// If "verilator --trace" is used, include the tracing class
+#if VM_TRACE
+# include <verilated_vcd_c.h>
+#endif
+
+// Current simulation time (64-bit unsigned)
+vluint64_t main_time = 0;
+// Called by $time in Verilog
+double sc_time_stamp() {
+    return main_time;  // Note does conversion to real, to match SystemC
+}
+
+int main(int argc, char** argv) {
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    Verilated::commandArgs(argc, argv);
+    // Set debug level, 0 is off, 9 is highest presently used
+    Verilated::debug(0);
+    // Randomize values on reset
+    Verilated::randReset(2);
+
+    // Construct the Verilated model, from Vtb.h generated from Verilating "tb.v"
+    Vpassthrough* tb = new Vpassthrough; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper
+
+#if VM_TRACE
+    // If verilator was invoked with --trace argument,
+    // and if at run time passed the +trace argument, turn on tracing
+    VerilatedVcdC* tfp = NULL;
+    const char* flag = Verilated::commandArgsPlusMatch("trace");
+    if (flag && 0==strcmp(flag, "+trace")) {
+        Verilated::traceEverOn(true);  // Verilator must compute traced signals
+        VL_PRINTF("Enabling waves into logs/vlt_dump.vcd...\n");
+        tfp = new VerilatedVcdC;
+        tb->trace(tfp, 99);  // Trace 99 levels of hierarchy
+        Verilated::mkdir("logs");
+        tfp->open("logs/vlt_dump.vcd");  // Open the dump file
+    }
+#endif
+
+    // Set some inputs
+    tb->but = 0;
+    tb->uart_rx = 0;
+
+    for (; main_time < 20; main_time++) {
+	tb->but = main_time & 3;
+	tb->uart_rx = !!(main_time & 4);
+
+        // Evaluate model
+        tb->eval();
+
+#if VM_TRACE
+        // Dump trace data for this cycle
+        if (tfp)
+		tfp->dump(main_time);
+#endif
+
+        // Read outputs
+        VL_PRINTF("[%" VL_PRI64 "d] but=%x led=%x uart_rx=%x uart_tx=%x\n",
+		  main_clock, tb->but, tb->led, tb->uart_rx, tb->uart_tx);
+    }
+
+    // Final model cleanup
+    tb->final();
+
+    // Close trace if opened
+#if VM_TRACE
+    if (tfp)
+	    tfp->close();
+#endif
+
+    //  Coverage analysis (since test passed)
+#if VM_COVERAGE
+    Verilated::mkdir("logs");
+    VerilatedCov::write("logs/coverage.dat");
+#endif
+
+    // Destroy model
+    delete tb;
+
+    // Fin
+    exit(0);
+}
diff --git a/passthrough/passthrough.v b/passthrough/passthrough.v
new file mode 100644
index 0000000..73673e5
--- /dev/null
+++ b/passthrough/passthrough.v
@@ -0,0 +1,18 @@
+/* Just pass through buttons to LEDs and RxD to TxD */
+
+module passthrough (
+    `ifdef BUTS
+	    input [width - 1:0] but,
+	    output [width - 1:0] led,
+    `endif
+    input uart_rx,
+    output uart_tx
+);
+
+`ifdef BUTS
+    parameter width = `LEDS > `BUTS ? `BUTS : `LEDS;
+    assign but = led;
+`endif
+    assign uart_tx = uart_rx;
+
+endmodule
diff --git a/uart/Makefile b/uart/Makefile
new file mode 100644
index 0000000..1740ae1
--- /dev/null
+++ b/uart/Makefile
@@ -0,0 +1,4 @@
+MODULE := uart
+M_VSRC := uart.v uart_trx.v
+
+include $(realpath $(dir $(lastword $(MAKEFILE_LIST))))/../common.mk
diff --git a/uart_transmission/top.v b/uart/uart.v
similarity index 84%
rename from uart_transmission/top.v
rename to uart/uart.v
index 6560154..42a7126 100644
--- a/uart_transmission/top.v
+++ b/uart/uart.v
@@ -1,31 +1,31 @@
 /* Top level module for keypad + UART demo */
-module top (
+module uart (
     // input hardware clock (12 MHz)
     hwclk, 
     // all LEDs
-    led1,
+    led,
     // UART lines
-    ftdi_tx, 
+    uart_tx,
     );
 
     /* Clock input */
     input hwclk;
 
     /* LED outputs */
-    output led1;
+    output [`LEDS - 1:0] led;
 
-    /* FTDI I/O */
-    output ftdi_tx;
+    /* uart I/O */
+    output uart_tx;
 
-    /* 9600 Hz clock generation (from 12 MHz) */
+    /* 9600 Hz clock generation (from 100 MHz) */
     reg clk_9600 = 0;
     reg [31:0] cntr_9600 = 32'b0;
-    parameter period_9600 = 625;
+    parameter period_9600 = 434;
 
-    /* 1 Hz clock generation (from 12 MHz) */
+    /* 1 Hz clock generation (from 100 MHz) */
     reg clk_1 = 0;
     reg [31:0] cntr_1 = 32'b0;
-    parameter period_1 = 6000000;
+    parameter period_1 = 50000000;
 
     // Note: could also use "0" or "9" below, but I wanted to
     // be clear about what the actual binary value is.
@@ -53,11 +53,11 @@ module top (
         // input: tx is finished
         .txdone (uart_txed),
         // output UART tx pin
-        .tx (ftdi_tx),
+        .tx (uart_tx),
     );
 
     /* Wiring */
-    assign led1=ledval;
+    assign led[0] = ledval;
     
     /* Low speed clock generation */
     always @ (posedge hwclk) begin
@@ -86,4 +86,4 @@ module top (
         end
     end
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/uart_transmission/uart_trx.v b/uart/uart_trx.v
similarity index 100%
rename from uart_transmission/uart_trx.v
rename to uart/uart_trx.v
diff --git a/uart_transmission/.gitignore b/uart_transmission/.gitignore
deleted file mode 100644
index a007fea..0000000
--- a/uart_transmission/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-build/*
diff --git a/uart_transmission/Makefile b/uart_transmission/Makefile
deleted file mode 100644
index dd86769..0000000
--- a/uart_transmission/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-# Project setup
-PROJ      = uart
-BUILD     = ./build
-DEVICE    = 1k
-#DEVICE    = 8k
-ifeq (8k,$(DEVICE))
-FOOTPRINT = ct256
-else
-FOOTPRINT = tq144
-endif
-
-# Files
-FILES = top.v
-FILES += uart_trx.v
-
-.PHONY: all clean burn
-
-all:$(BUILD)/$(PROJ).bin
-
-$(BUILD)/$(PROJ).bin: $(FILES) Makefile
-	# if build folder doesn't exist, create it
-	mkdir -p $(BUILD)
-	# synthesize using Yosys
-	yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(FILES)
-	# Place and route using arachne
-	arachne-pnr -d $(DEVICE) -P $(FOOTPRINT) -o $(BUILD)/$(PROJ).asc -p pinmap_$(FOOTPRINT).pcf $(BUILD)/$(PROJ).blif
-	# Convert to bitstream using IcePack
-	icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
-
-burn:   $(BUILD)/$(PROJ).bin
-	iceprog $<
-
-clean:
-	rm -f build/*
diff --git a/uart_transmission/pinmap_ct256.pcf b/uart_transmission/pinmap_ct256.pcf
deleted file mode 100644
index c6fe96a..0000000
--- a/uart_transmission/pinmap_ct256.pcf
+++ /dev/null
@@ -1,13 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 B5
-set_io --warn-no-port led2 B4
-set_io --warn-no-port led3 A2
-set_io --warn-no-port led4 A1
-set_io --warn-no-port led5 C5
-set_io --warn-no-port led6 C4
-set_io --warn-no-port led7 B3
-set_io --warn-no-port led8 C3
-set_io --warn-no-port hwclk J3
-# FTDI / UART pins
-set_io --warn-no-port ftdi_tx B12
-set_io --warn-no-port ftdi_rx B10
\ No newline at end of file
diff --git a/uart_transmission/pinmap_tq144.pcf b/uart_transmission/pinmap_tq144.pcf
deleted file mode 100644
index 08e8e33..0000000
--- a/uart_transmission/pinmap_tq144.pcf
+++ /dev/null
@@ -1,10 +0,0 @@
-# example.pcf
-set_io --warn-no-port led1 99
-set_io --warn-no-port led2 98
-set_io --warn-no-port led3 97
-set_io --warn-no-port led4 96
-set_io --warn-no-port led5 95
-set_io --warn-no-port hwclk 21
-# FTDI / UART pins
-set_io --warn-no-port ftdi_tx 8
-set_io --warn-no-port ftdi_rx 9