Add metadata field for names that shouldn't be inlined in the verilog code generation

[leonardt]

We already have the logic to blacklist the inlining of certain wire names, so it should be simple to pass this information through to the backend logic. The main use case is for times when signals shouldn't be removed for various features, such as hierarchical references in verilog which refer to a signal that could be inlined, or values that are referred to in inline_verilog.