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ADDX bug? #2

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rimwall opened this issue Dec 22, 2022 · 5 comments
Open

ADDX bug? #2

rimwall opened this issue Dec 22, 2022 · 5 comments

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@rimwall
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rimwall commented Dec 22, 2022

Hi,

Firstly I just want to say a huge thankyou for creating M32R support in Ghidra. It's been very useful for a project I'm working on.

I'm not very familiar with Ghidra processor files, but I am wondering if there is a bug in the *.sinc file for the ADDX command. Often the decompiler produces output with a 'CARRY4' function. An example...

            if (uVar4 < 0x350) {
              uVar6 = (uint)RAM_SSM_msg_data_byte0_0x804c07;
              uVar7 = uVar6 * 0x40000000;
              uVar10 = uVar6 * -0x80000000;
              uVar1 = uVar10 + (uVar4 < 0x350);
              iVar9 = uVar6 * -0x80000000 + (uint)(byte)(CARRY4(uVar7,uVar7) | CARRY4(uVar10,uVar1))
              ;
              if ((byte)(CARRY4(uVar7,uVar7) | CARRY4(uVar10,uVar1)) == 1) goto LAB_0003dd54;
              (&RAM_SSM_rsp_byte0_fmt_0x804c96)[uVar3] = *(&PTR_DAT_0007cd78)[uVar4 & 0xffff];
            }

which comes from the following machine code / disassembly...

image

Just wondering how I can fix this, or interpret the decompiler output?

Thanks!

@GhidrAuto
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how did you get it in the processor file? I have added a few processors without a problem. I cannot get this one added though. it doesnt show up in the processors

@rimwall
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rimwall commented Mar 7, 2024

Hi, so long ago I can't remember. Looks like I made some changes to two of the files (attached). I am using Ghidra 10.1 if that's relevant.
m32r.zip

@GhidrAuto
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GhidrAuto commented Mar 13, 2024 via email

@rimwall
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rimwall commented Mar 14, 2024 via email

@GhidrAuto
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GhidrAuto commented Mar 14, 2024 via email

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