From 7f99888d992294a61b2a6bc8da4d8e3a9db0a3b8 Mon Sep 17 00:00:00 2001 From: Neel Gala Date: Thu, 14 Oct 2021 22:04:30 +0530 Subject: [PATCH] fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests. --- CHANGELOG.md | 4 ++++ riscv-test-suite/rv32i_m/I/src/sll-01.S | 2 +- riscv-test-suite/rv32i_m/I/src/sra-01.S | 2 +- riscv-test-suite/rv32i_m/I/src/srl-01.S | 2 +- riscv-test-suite/rv64i_m/I/src/sll-01.S | 2 +- riscv-test-suite/rv64i_m/I/src/sllw-01.S | 2 +- riscv-test-suite/rv64i_m/I/src/sra-01.S | 2 +- riscv-test-suite/rv64i_m/I/src/sraw-01.S | 2 +- riscv-test-suite/rv64i_m/I/src/srl-01.S | 2 +- riscv-test-suite/rv64i_m/I/src/srlw-01.S | 2 +- 10 files changed, 13 insertions(+), 9 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 151ba26d0..cf6144267 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,4 +1,8 @@ # CHANGELOG + +## [2.5.3] - 2021-10-15 + - fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests. + ## [2.5.2] - 2021-10-14 - update format for aes32 and sm4 instructions - update reference signature for sha256 and sm3 instructions in rv64i_m/K_unratified diff --git a/riscv-test-suite/rv32i_m/I/src/sll-01.S b/riscv-test-suite/rv32i_m/I/src/sll-01.S index 9b0ed636d..be790cd0e 100644 --- a/riscv-test-suite/rv32i_m/I/src/sll-01.S +++ b/riscv-test-suite/rv32i_m/I/src/sll-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32i") +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/I/src/sra-01.S b/riscv-test-suite/rv32i_m/I/src/sra-01.S index 4f34c43a7..0694ae3d1 100644 --- a/riscv-test-suite/rv32i_m/I/src/sra-01.S +++ b/riscv-test-suite/rv32i_m/I/src/sra-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32i") +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv32i_m/I/src/srl-01.S b/riscv-test-suite/rv32i_m/I/src/srl-01.S index 0e98972a9..c4c48ef8c 100644 --- a/riscv-test-suite/rv32i_m/I/src/srl-01.S +++ b/riscv-test-suite/rv32i_m/I/src/srl-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV32i") +RVTEST_ISA("RV32I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv64i_m/I/src/sll-01.S b/riscv-test-suite/rv64i_m/I/src/sll-01.S index 35cfd168d..04773a40b 100644 --- a/riscv-test-suite/rv64i_m/I/src/sll-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sll-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64i") +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv64i_m/I/src/sllw-01.S b/riscv-test-suite/rv64i_m/I/src/sllw-01.S index a0b776707..aafeb271a 100644 --- a/riscv-test-suite/rv64i_m/I/src/sllw-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sllw-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64i") +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv64i_m/I/src/sra-01.S b/riscv-test-suite/rv64i_m/I/src/sra-01.S index c1855d6f9..e613edda5 100644 --- a/riscv-test-suite/rv64i_m/I/src/sra-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sra-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64i") +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv64i_m/I/src/sraw-01.S b/riscv-test-suite/rv64i_m/I/src/sraw-01.S index 5438ba759..7d8345731 100644 --- a/riscv-test-suite/rv64i_m/I/src/sraw-01.S +++ b/riscv-test-suite/rv64i_m/I/src/sraw-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64i") +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv64i_m/I/src/srl-01.S b/riscv-test-suite/rv64i_m/I/src/srl-01.S index 3f4823944..e31ac60a7 100644 --- a/riscv-test-suite/rv64i_m/I/src/srl-01.S +++ b/riscv-test-suite/rv64i_m/I/src/srl-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64i") +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point diff --git a/riscv-test-suite/rv64i_m/I/src/srlw-01.S b/riscv-test-suite/rv64i_m/I/src/srlw-01.S index 5fe37a831..800ffb881 100644 --- a/riscv-test-suite/rv64i_m/I/src/srlw-01.S +++ b/riscv-test-suite/rv64i_m/I/src/srlw-01.S @@ -17,7 +17,7 @@ // #include "model_test.h" #include "arch_test.h" -RVTEST_ISA("RV64i") +RVTEST_ISA("RV64I") .section .text.init .globl rvtest_entry_point