diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c
index 792eb95960877f3..79694a81fd38da0 100644
--- a/soc/espressif/common/loader.c
+++ b/soc/espressif/common/loader.c
@@ -21,9 +21,11 @@
 #include <esp_log.h>
 #include <bootloader_clock.h>
 #include <bootloader_common.h>
-
 #include <esp_cpu.h>
 
+#include <zephyr/linker/linker-defs.h>
+#include <kernel_internal.h>
+
 #if CONFIG_SOC_SERIES_ESP32C6
 #include <soc/hp_apm_reg.h>
 #include <soc/lp_apm_reg.h>
@@ -254,6 +256,26 @@ void __start(void)
 			     ".option norelax\n"
 			     "la gp, __global_pointer$\n"
 			     ".option pop");
+#else /* xtensa */
+
+	extern uint32_t _init_start;
+
+	/* Move the exception vector table to IRAM. */
+	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
+
+	z_bss_zero();
+
+	__asm__ __volatile__ ("" : : "g"(&__bss_start) : "memory");
+
+	/* Disable normal interrupts. */
+	__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
+
+	/* Initialize the architecture CPU pointer.  Some of the
+	 * initialization code wants a valid arch_current_thread() before
+	 * arch_kernel_init() is invoked.
+	 */
+	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
+
 #endif /* CONFIG_RISCV_GP */
 
 #ifndef CONFIG_BOOTLOADER_MCUBOOT
diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c
index ec1fc8c8babeb40..b7488b3e7585998 100644
--- a/soc/espressif/esp32/soc.c
+++ b/soc/espressif/esp32/soc.c
@@ -22,8 +22,6 @@
 #include <string.h>
 #include <zephyr/toolchain.h>
 #include <zephyr/types.h>
-#include <zephyr/linker/linker-defs.h>
-#include <kernel_internal.h>
 
 #include <esp_private/system_internal.h>
 #include <esp32/rom/cache.h>
@@ -56,26 +54,6 @@ extern int esp_appcpu_init(void);
  */
 void IRAM_ATTR __esp_platform_start(void)
 {
-	extern uint32_t _init_start;
-
-	/* Move the exception vector table to IRAM. */
-	__asm__ __volatile__ ("wsr %0, vecbase" : : "r"(&_init_start));
-
-	z_bss_zero();
-
-	__asm__ __volatile__ ("" : : "g"(&__bss_start) : "memory");
-
-	/* Disable normal interrupts. */
-	__asm__ __volatile__ ("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
-
-	/* Initialize the architecture CPU pointer.  Some of the
-	 * initialization code wants a valid _current before
-	 * z_prep_c() is invoked.
-	 */
-	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
-
-	esp_reset_reason_init();
-
 #ifndef CONFIG_MCUBOOT
 	/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check
 	 * on startup sequence related issues in application. Hence disable that
@@ -87,6 +65,8 @@ void IRAM_ATTR __esp_platform_start(void)
 	wdt_hal_disable(&rtc_wdt_ctx);
 	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
 
+	esp_reset_reason_init();
+
 	esp_timer_early_init();
 
 	esp_mspi_pin_init();
diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c
index 02a6d1b4dc6fbb8..ed90a900c6c2529 100644
--- a/soc/espressif/esp32s2/soc.c
+++ b/soc/espressif/esp32s2/soc.c
@@ -50,25 +50,6 @@ extern void z_prep_c(void);
  */
 void __attribute__((section(".iram1"))) __esp_platform_start(void)
 {
-	extern uint32_t _init_start;
-
-	/* Move the exception vector table to IRAM. */
-	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
-
-	/* Zero out BSS */
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
-
-	/* Initialize the architecture CPU pointer.  Some of the
-	 * initialization code wants a valid _current before
-	 * arch_kernel_init() is invoked.
-	 */
-	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
-
-	esp_reset_reason_init();
-
 #ifndef CONFIG_MCUBOOT
 	/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
 	 * related issues in application. Hence disable that as we are about to start
@@ -96,6 +77,8 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 	esp_config_data_cache_mode();
 	esp_rom_Cache_Enable_DCache(0);
 
+	esp_reset_reason_init();
+
 	esp_timer_early_init();
 
 	esp_mspi_pin_init();
diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c
index 763ba341940f005..3232c13f85385e6 100644
--- a/soc/espressif/esp32s3/soc.c
+++ b/soc/espressif/esp32s3/soc.c
@@ -86,21 +86,6 @@ static void IRAM_ATTR esp_errata(void)
  */
 void IRAM_ATTR __esp_platform_start(void)
 {
-	extern uint32_t _init_start;
-
-	/* Move the exception vector table to IRAM. */
-	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
-
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
-
-	/* Initialize the architecture CPU pointer.  Some of the
-	 * initialization code wants a valid _current before
-	 * arch_kernel_init() is invoked.
-	 */
-	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
 
 #ifndef CONFIG_MCUBOOT
 	/* Configure the mode of instruction cache : cache size, cache line size. */