From edf97c7012f6658997aa21dc99fd1b65c60b3fa2 Mon Sep 17 00:00:00 2001 From: teachop Date: Wed, 9 Jul 2014 21:48:25 -0400 Subject: [PATCH 1/2] clock can from 16mhz xtal --- FlexCAN.cpp | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/FlexCAN.cpp b/FlexCAN.cpp index 659b38f..4845853 100644 --- a/FlexCAN.cpp +++ b/FlexCAN.cpp @@ -16,8 +16,9 @@ FlexCAN::FlexCAN(uint32_t baud) CORE_PIN3_CONFIG = PORT_PCR_MUX(2); CORE_PIN4_CONFIG = PORT_PCR_MUX(2);// | PORT_PCR_PE | PORT_PCR_PS; // select clock source + OSC0_CR |= OSC_ERCLKEN; SIM_SCGC6 |= SIM_SCGC6_FLEXCAN0; - FLEXCAN0_CTRL1 |= FLEXCAN_CTRL_CLK_SRC; + FLEXCAN0_CTRL1 &= ~FLEXCAN_CTRL_CLK_SRC; // enable CAN FLEXCAN0_MCR |= FLEXCAN_MCR_FRZ; @@ -40,16 +41,16 @@ FlexCAN::FlexCAN(uint32_t baud) // segment timings from freescale loopback test if ( 250000 == baud ) { FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1) - | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(15)); + | FLEXCAN_CTRL_PSEG1(7) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(3)); } else if ( 500000 == baud ) { FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1) - | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(7)); + | FLEXCAN_CTRL_PSEG1(7) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(1)); } else if ( 1000000 == baud ) { - FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(3) | FLEXCAN_CTRL_RJW(0) - | FLEXCAN_CTRL_PSEG1(0) | FLEXCAN_CTRL_PSEG2(1) | FLEXCAN_CTRL_PRESDIV(5)); + FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(0) + | FLEXCAN_CTRL_PSEG1(1) | FLEXCAN_CTRL_PSEG2(1) | FLEXCAN_CTRL_PRESDIV(1)); } else { // 125000 - FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(2) - | FLEXCAN_CTRL_PSEG1(3) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(31)); + FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1) + | FLEXCAN_CTRL_PSEG1(7) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(7)); } // Default mask is allow everything From e818d40978270b61723dbe61716ff407e01c6737 Mon Sep 17 00:00:00 2001 From: teachop Date: Thu, 10 Jul 2014 17:38:20 -0400 Subject: [PATCH 2/2] remove 48mhz test and references --- FlexCAN.cpp | 4 ++-- FlexCAN.h | 5 ----- README.md | 2 -- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/FlexCAN.cpp b/FlexCAN.cpp index 4845853..35103e8 100644 --- a/FlexCAN.cpp +++ b/FlexCAN.cpp @@ -15,7 +15,7 @@ FlexCAN::FlexCAN(uint32_t baud) // set up the pins, 3=PTA12=CAN0_TX, 4=PTA13=CAN0_RX CORE_PIN3_CONFIG = PORT_PCR_MUX(2); CORE_PIN4_CONFIG = PORT_PCR_MUX(2);// | PORT_PCR_PE | PORT_PCR_PS; - // select clock source + // select clock source 16MHz xtal OSC0_CR |= OSC_ERCLKEN; SIM_SCGC6 |= SIM_SCGC6_FLEXCAN0; FLEXCAN0_CTRL1 &= ~FLEXCAN_CTRL_CLK_SRC; @@ -38,7 +38,7 @@ FlexCAN::FlexCAN(uint32_t baud) //enable RX FIFO FLEXCAN0_MCR |= FLEXCAN_MCR_FEN; - // segment timings from freescale loopback test + // segment splits and clock divisor based on baud rate if ( 250000 == baud ) { FLEXCAN0_CTRL1 = (FLEXCAN_CTRL_PROPSEG(2) | FLEXCAN_CTRL_RJW(1) | FLEXCAN_CTRL_PSEG1(7) | FLEXCAN_CTRL_PSEG2(3) | FLEXCAN_CTRL_PRESDIV(3)); diff --git a/FlexCAN.h b/FlexCAN.h index c2d5ca1..19e92e8 100644 --- a/FlexCAN.h +++ b/FlexCAN.h @@ -7,11 +7,6 @@ #include -// in the short term insure 48MHz bus speed -#if F_BUS != 48000000 -#error "Only CPU speeds 48, 96 and 144 are supported" -#endif - typedef struct CAN_message_t { uint32_t id; // can identifier uint8_t ext; // identifier is extended diff --git a/README.md b/README.md index 982de1f..03c7945 100644 --- a/README.md +++ b/README.md @@ -11,8 +11,6 @@ Note that CAN will normally not work without termination resistors. Supported baud rates are 125000, 250000, 500000, and 1000000 bits per second. If the baud rate is not specified it will default to 125000. -Please note that **only CPU speeds 48, 96 and 144 are supported** presently. - ###CAN Transceiver Options Please add parts you are using successfully with Teensy 3.1 to this list. - TI SN65HVD230D on 3.3V (1MBPS)