Register the read mux select

[7FM]

The output muxes above the 16-word slices (RAM32 and up) selected by the current address, while the slices register their output at the rising edge. A read was only correct if the upper address bits stayed the same in the next cycle. Register the select at the rising edge as well, so the output is the word addressed at that edge (read latency 1).

• MUX2x1/MUX4x1 (sky130, gf180): CLK input and a select register (SELREG); every output mux gets its module's clock
• placeram: place SELREG in front of the select buffers
• clock tree: the select registers load the clock nets, which made the input hold times worse. Stronger root clock buffer (CLKBUF_16) in RAM128/RAM1024/RAM2048, and a root clock buffer in RAM256/RAM512, where the clock pin drove the whole macro directly