Merge pull request #4 from shraddha-chaudhari-imgtec/openwrt-4.4.7

Linux 4.4.7 changes

Documentation/devicetree/bindings/mips/img/pistachio.txt

@@ -12,7 +12,7 @@ A "cpus" node is required.  Required properties:
  - #size-cells: Must be 0.
 A CPU sub-node is also required for at least CPU 0.  Since the topology may
 be probed via CPS, it is not necessary to specify secondary CPUs.  Required
-propertis:
+properties:
  - device_type: Must be "cpu".
  - compatible: Must be "mti,interaptiv".
  - reg: CPU number.

Documentation/devicetree/bindings/misc/img-pdm.txt

@@ -0,0 +1,54 @@
+Imagination Technologies Pulse Density Modulator (PDM) DAC.
+
+Required properties:
+- compatible: Must be "img,pistachio-pdm"
+- clocks: phandle to input PDM clock
+- clock-names: Must include the following entry:
+  - pdm: input clock to pdm block.
+- img,cr-periph: Must contain a phandle to the peripheral control
+  syscon node which contains PDM control registers.
+- #pdm-cells: Must be 2.
+- The first cell is the PDM channel number (valid values: 0, 1, 2, 3)
+- The second cell is 12-bit pulse-in value
+
+Specifying PDM information for devices
+======================================
+
+1. PDM User nodes
+
+PDM properties should be named "pdms". The exact meaning of each pdms property
+is described above.
+
+	pdm-specifier : array of #pdm-cells specifying the given PDM
+						(controller specific)
+
+The following example could be used to describe a PDM-based backlight device:
+
+	pdm: pdm {
+		#pdm-cells = <2>;
+	};
+
+	[...]
+
+	bl: backlight {
+		pdms = <&pdm 2 0>;
+	};
+
+pdm-specifier typically encodes the chip-relative PDM channel number and the
+12-bit pulse-in value.
+
+2. PDM Controller nodes
+
+PDM controller nodes must specify the number of cells used for the specifier
+using the '#pdm-cells' property.
+
+An example PDM controller might look like this:
+
+Example:
+	pdm: pdm@18148000 {
+		compatible = "img,pistachio-pdm";
+		clocks = <&pdm_clk>;
+		clk-names = "pdm";
+		img,cr-periph = <&cr_periph>;
+		#pdm-cells = <2>;
+	};

Documentation/devicetree/bindings/misc/img-scratchpad.txt

@@ -0,0 +1,21 @@
+Imagination Technologies scratchpad driver
+
+Provide syfs read/write access to the scratchpad registers.
+These registers are soft reset protected registers.
+
+Required properties:
+- compatible: Should be "img,pistachio-scratchpad", "syscon"
+- reg: Should contain scratchpad registers location and length
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Should contain "wdt" and "sys";
+- sysfs-mask: 8 bit value should specify the registers to be exposed via sysfs
+
+Examples:
+
+scratchpad@18102120 {
+	compatible = "img,pistachio-scratchpad", "syscon";
+	reg = <0x18102120 0x20>;
+	clocks = <&clk_periph PERIPH_CLK_WD>, <&cr_periph SYS_CLK_WD>;
+	clock-names = "wdt", "sys";
+	sysfs-mask = /bits/ 8 <0xFE>; /*expose all except the first reg */
+};

Documentation/devicetree/bindings/misc/uboot-bootcount.txt

@@ -0,0 +1,40 @@
+U-Boot bootcount driver
+
+This driver implements the Linux kernel half of the boot count feature -
+the boot counter can only be reset after it is clear that the
+application has been started and is running correctly, which usually
+can only be determined by the application code itself. Thus the reset
+of the boot counter must be done by application code, which thus needs
+an appropriate driver.
+
+Required feature by the Carrier Grade Linux Requirements Definition;
+see for example document "Carrier Grade Linux Requirements Definition
+Overview V3.0" at
+
+http://www.linuxfoundation.org/collaborate/workgroups/cgl/requirements#SMM.6.0_Boot_Cycle_Detection
+
+        Description: OSDL CGL specifies that carrier grade Linux
+        shall provide support for detecting a repeating reboot cycle
+        due to recurring failures. This detection should happen in
+        user space before system services are started.
+
+This driver provides read/write access to the U-Boot bootcounter
+through sysfs file.
+
+Required properties:
+
+  - compatible : should be "uboot,bootcount"
+  - reg: the address of the bootcounter
+  - syscon-reg: Specify if reg property is not specified, should specify the syscon reg to be used
+
+Example:
+
+bootcount@1c23000 {
+	compatible = "uboot,bootcount";
+	reg = <0x23060 0x1>;
+};
+
+bootcount {
+	compatible = "uboot,bootcount";
+	syscon-reg = <&scratchpad 0x0>;
+};

Documentation/devicetree/bindings/net/ieee802154/cc2520.txt

@@ -15,7 +15,12 @@ Required properties:
 	- reset-gpio:		GPIO spec for the RESET pin
 Optional properties:
 	- amplified:		include if the CC2520 is connected to a CC2591 amplifier
-
+	- #clock-cells		from common clock binding; shall be set to 0
+				required if extclock-freq is specified
+	- extclock-freq:	frequency setting of external clock generator, should be
+				between 1000000-16000000 (check datasheet for supported values)
+				extclock is disabled if extclock-freq = <0>, if not specified
+				defaults to 1MHz (reset value)
 Example:
 	cc2520@0 {
 		compatible = "ti,cc2520";
@@ -30,4 +35,6 @@ Example:
 		cca-gpio = <&gpio1 16 0>;
 		vreg-gpio = <&gpio0 31 0>;
 		reset-gpio = <&gpio1 12 0>;
+		#clock-cells = <0>;
+		extclock-freq = <16000000>;
 	};

Documentation/devicetree/bindings/phy/pistachio-usb-phy.txt

@@ -15,6 +15,9 @@ Required properties:
 Optional properties:
 --------------------
  - phy-supply: USB VBUS supply.  Must supply 5.0V.
+ - enable-vbus-drive: include if USB block should drive the VBUS on mfio86,
+		      this will override the primary function RPU_L_PLL lock signal
+		      available on this pin.
 
 Example:
 --------
@@ -26,4 +29,5 @@ usb_phy: usb-phy {
 	img,refclk = <REFCLK_CLK_CORE>;
 	img,cr-top = <&cr_top>;
 	#phy-cells = <0>;
+	enable-vbus-drive;
 };

Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt

@@ -134,12 +134,12 @@ mfio80		ddr_debug, mips_trace_data, mips_debug
 mfio81		dreq0, mips_trace_data, eth_debug
 mfio82		dreq1, mips_trace_data, eth_debug
 mfio83		mips_pll_lock, mips_trace_data, usb_debug
-mfio84		sys_pll_lock, mips_trace_data, usb_debug
-mfio85		wifi_pll_lock, mips_trace_data, sdhost_debug
-mfio86		bt_pll_lock, mips_trace_data, sdhost_debug
-mfio87		rpu_v_pll_lock, dreq2, socif_debug
-mfio88		rpu_l_pll_lock, dreq3, socif_debug
-mfio89		audio_pll_lock, dreq4, dreq5
+mfio84		audio_pll_lock, mips_trace_data, usb_debug
+mfio85		rpu_v_pll_lock, mips_trace_data, sdhost_debug
+mfio86		rpu_l_pll_lock, mips_trace_data, sdhost_debug
+mfio87		sys_pll_lock, dreq2, socif_debug
+mfio88		wifi_pll_lock, dreq3, socif_debug
+mfio89		bt_pll_lock, dreq4, dreq5
 tck
 trstn
 tdi

Documentation/devicetree/bindings/reset/img,pistachio-reset.txt

@@ -0,0 +1,54 @@
+Pistachio Reset Controller
+=============================================================================
+
+This binding describes a reset controller device that is used to enable and
+disable individual IP blocks within the Pistachio SoC using "soft reset"
+control bits found in the Pistachio SoC top level registers.
+
+The actual action taken when soft reset is asserted is hardware dependent.
+However, when asserted it may not be possible to access the hardware's
+registers, and following an assert/deassert sequence the hardware's previous
+state may no longer be valid.
+
+Please refer to Documentation/devicetree/bindings/reset/reset.txt
+for common reset controller binding usage.
+
+Required properties:
+
+- compatible: Contains "img,pistachio-reset"
+
+- #reset-cells: Contains 1
+
+Example:
+	cr_periph: clk@18148000 {
+		compatible = "img,pistachio-cr-periph", "syscon", "simple-bus";
+		reg = <0x18148000 0x1000>;
+		clocks = <&clk_periph PERIPH_CLK_SYS>;
+		clock-names = "sys";
+		#clock-cells = <1>;
+
+		pistachio_reset: reset-controller {
+			compatible = "img,pistachio-reset";
+			#reset-cells = <1>;
+		};
+	};
+
+Specifying reset control of devices
+=======================================
+
+Device nodes should specify the reset channel required in their "resets"
+property, containing a phandle to the pistachio reset device node and an
+index specifying which reset to use, as described in
+Documentation/devicetree/bindings/reset/reset.txt.
+
+Example:
+
+	spdif_out: spdif-out@18100d00 {
+		...
+		resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>;
+		reset-names = "rst";
+		...
+	};
+
+Macro definitions for the supported resets can be found in:
+include/dt-bindings/reset-controller/pistachio-resets.h

Documentation/devicetree/bindings/soc/img/img-efuse.txt

@@ -0,0 +1,26 @@
+* Imagination Technologies Generic eFuse controller
+
+Required properties:
+- compatible: Must be "img,pistachio-efuse".
+- reg: Must contain the base address and length of the eFuse registers.
+
+Optional properties:
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clock/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - osc: External oscillator clock
+  - sys: eFuse register interface clock
+
+Example:
+efuse: efuse@18149200 {
+	compatible = "img,pistachio-efuse";
+	reg = <0x18149200 0x200>;
+};
+
+Example with optional clock properties:
+efuse: efuse@18149200 {
+	compatible = "img,pistachio-efuse";
+	reg = <0x18149200 0x200>;
+	clocks = <&osc>, <&system_clk>;
+	clock-names = "osc", "sys";
+};

Documentation/devicetree/bindings/sound/img,i2s-in.txt

@@ -0,0 +1,80 @@
+Imagination Technologies I2S Input Controller
+
+Required Properties:
+
+  - compatible : Compatible list, must contain "img,i2s-in"
+
+  - #sound-dai-cells : Must be equal to 1
+
+  - #sound-platform-cells : Must be equal to 1
+
+  - reg : Offset and length of the register set for the device
+
+  - clocks : Contains an entry for each entry in clock-names
+
+  - clock-names : Must include the following entry:
+	"sys"	The system clock
+
+  - dmas: Contains an entry for each entry in dma-names.
+
+  - dma-names: Must include one or both of the following:
+	"rx"					Shared DMA channel
+	"rxN" for N=0..img,i2s-channels - 1	Per-channel DMA
+
+  - img,i2s-channels : Number of I2S channels instantiated in the I2S in block
+
+  - img,cr-periph : Must contain a phandle to the peripheral control syscon
+                    node which contains the alternate i2s control registers
+
+Optional Properties:
+
+  - img,clock-master : Contains bitmask for clock master configuration. One
+		       bit per i2s channel for channels 0-3. 4/5 cannot be
+		       modified and always use MFIO47/MFIO48. If omitted,
+		       all channels will use MFIO47/MFIO48
+
+	0 -> MFIO47 = bit clock, MFIO48 = left/right clock
+	1 -> MFIO11 = bit clock, MFIO12 = left/right clock
+
+  - img,shared-dma : Contains number of channels to combine for use with the
+		     shared DMA channel. If this is not equal to the value
+		     specified in img,i2s-channels, per-channel dma references
+		     must exist for the remaining channels. If this is equal
+		     to zero, the shared dma channel reference can be ommitted.
+		     The combined channels must share the same bit and
+		     left/right clock. If omitted, all channels will combined
+		     for use with the shared DMA channel
+
+  - interrupts : Contains the I2S in interrupts. Depending on
+	the configuration, there may be no interrupts, one interrupt,
+	or an interrupt per I2S channel
+
+  - resets: Contains a phandle to the I2S in reset signal
+
+  - reset-names: Contains the reset signal name "rst"
+
+Example:
+
+i2s_in: i2s-in@18100800 {
+	compatible = "img,i2s-in";
+	reg = <0x18100800 0x200>;
+	interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&cr_periph SYS_CLK_I2S_IN>;
+	clock-names = "sys";
+	img,i2s-channels = <6>;
+	img,cr-periph = <&cr_periph>;
+	img,clock-master = <0xf>;
+	img,shared-dma = <3>;
+	dmas =  <&mdc 30 0xffffffff 0>,
+		<&mdc 24 0xffffffff 0>,
+		<&mdc 25 0xffffffff 0>,
+		<&mdc 26 0xffffffff 0>,
+		<&mdc 27 0xffffffff 0>,
+		<&mdc 28 0xffffffff 0>,
+		<&mdc 29 0xffffffff 0>;
+	dma-names = "rx", "rx0", "rx1", "rx2",
+		    "rx3", "rx4", "rx5";
+
+	#sound-dai-cells = <1>;
+	#sound-platform-cells = <1>;
+};

Documentation/devicetree/bindings/sound/img,i2s-out.txt

@@ -0,0 +1,49 @@
+Imagination Technologies I2S Output Controller
+
+Required Properties:
+
+  - compatible : Compatible list, must contain "img,i2s-out"
+
+  - #sound-dai-cells : Must be equal to 0
+
+  - reg : Offset and length of the register set for the device
+
+  - clocks : Contains an entry for each entry in clock-names
+
+  - clock-names : Must include the following entries:
+	"sys"	The system clock
+	"ref"	The reference clock
+
+  - dmas: Contains an entry for each entry in dma-names.
+
+  - dma-names: Must include the following entry:
+	"tx"	Single DMA channel used by all active I2S channels
+
+  - img,i2s-channels : Number of I2S channels instantiated in the I2S out block
+
+  - resets: Contains a phandle to the I2S out reset signal
+
+  - reset-names: Contains the reset signal name "rst"
+
+Optional Properties:
+
+  - interrupts : Contains the I2S out interrupts. Depending on
+	the configuration, there may be no interrupts, one interrupt,
+	or an interrupt per I2S channel
+
+Example:
+
+i2s_out: i2s-out@18100A00 {
+	compatible = "img,i2s-out";
+	reg = <0x18100A00 0x200>;
+	interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
+	dmas = <&mdc 23 0xffffffff 0>;
+	dma-names = "tx";
+	clocks = <&cr_periph SYS_CLK_I2S_OUT>,
+		 <&clk_core CLK_I2S>;
+	clock-names = "sys", "ref";
+	img,i2s-channels = <6>;
+	resets = <&pistachio_reset PISTACHIO_RESET_I2S_OUT>;
+	reset-names = "rst";
+	#sound-dai-cells = <0>;
+};