SRAM-CORE

This repository contains a parameterized SRAM control and memory subsystem implemented in Verilog/SystemVerilog for RTL simulation and FPGA-oriented prototyping. The design includes an AXI-like front end, a synchronous SRAM controller, a behavioral SRAM model, and a direct read FSM for low-latency access.

Module descriptions

• AXI_SLAVE.v

  • AXI-style slave interface for write-address, write-data, read-address, and read-data channels.
  • Uses FIFOs to buffer AW, W, AR, R, and B transactions and an arbiter to decide whether the controller should serve a read or write request.
  • Connects to the SRAM controller through request/response handshaking signals.

• controller.v

  • Main SRAM controller for read and write operations.
  • Supports single-word transfers and burst transactions with address incrementing when bmode is enabled.
  • Drives SRAM control signals (ce, oe, wre) and handles request capture, address sequencing, and completion signaling.

• spsram.v

  • Behavioral dual-port SRAM model.
  • Port 1 is used by the primary controller for normal read/write accesses.
  • Port 2 is used by a dedicated read FSM for direct reads without disturbing the main controller data path.

• rd_fsm.v

  • Small direct-read finite-state machine for SRAM port 2.
  • Captures a requested address, asserts oe to the SRAM, and returns data once the memory status flag indicates the read is valid.

• wr_rd_fsm.v

  • Alternate read/write FSM implementation for a parity-aware memory interface.
  • Maintains a read/write transaction flow and supports retry logic when parity checking fails.

• top_module_main.v

  • Top-level integration of the AXI slave, controller, and SRAM memory.
  • Intended as the main system-level wrapper around the SRAM subsystem.

• top_module.v

  • Simpler top-level wrapper used to connect the controller, direct-read FSM, and SRAM model together for functional verification.

• fifo.v

  • Simple synchronous FIFO used to temporarily store AXI transaction data.

• ICG.sv

  • Clock-gating cell used to generate a gated controller clock when the design is active.

• rr_arbiter.v

  • Placeholder arbitration module; not yet fully implemented in this repository snapshot.

Design parameters

The core SRAM subsystem is parameterized for different memory widths and address ranges.

Parameter	Default	Description
ADDRESS_WIDTH	8	Number of address bits; memory depth is 2 ** ADDRESS_WIDTH.
DATA_WIDTH	8	Width of the data bus.
BURST_LENGTH	4	Maximum burst length supported by the AXI and controller interfaces.
ID_WIDTH	2	Transaction ID width for AXI-style channels.
BURST_TYPE	2	Burst type encoding (INCR/fixed-style behavior in the controller interface).

Derived values:

• Memory depth = 256 locations for the default ADDRESS_WIDTH = 8
• Total addressable memory = 2 ** ADDRESS_WIDTH
• Controller interfaces assume active-low reset behavior for the reset signal in the main modules