Electrical Engineering Student | Computer Architecture | RISC-V Hardware Acceleration | Hardware-Software Co-Design | Novel Compute Paradigms
Languages & Systems:
Hardware Description & EDA Tooling:
I'm an Electrical Engineering student (CPGE MPSI/PSI background) transitioning to the advancing to Master's level studies in Electrical Engineering. My work sits at the boundary of hardware design and the compilers/software that target it. I ahve a keen interest for RISC-V hardware accelerators, and really interested in alternative computing paradigms like HDC, and write the tooling (schedulers, RTL emitters, EDA tools in general) needed to actually get a custom datapath from an algorithm into silicon.
I got here through device physics simulating quantum transport and memristive crossbars taught me why a piece of hardware behaves the way it does before I started asking how to make it faster. That's the thread running through everything below: understand the physical or mathematical structure of a problem, then design the smallest, most efficient piece of hardware that solves it.
- Designing and verifying RISC-V coprocessors (RoCC / CV-X-IF) for domain-specific acceleration.
- Building HWExplore, a Julia-to-RTL hardware acceleration framework for RISC-V.
- Nanofabrication Engineering Intern at Alice & Bob, working hands-on with the cleanroom processes that put silicon designs into the physical world, and EDA tools.
- Preparing for advanced coursework in Computer Architecture and microelectronics.
- Computer Architecture & Hardware Acceleration custom coprocessors, RoCC/CV-X-IF integration, dataflow-graph-to-RTL compilation.
- RISC-V open ISA extension design, accelerator dispatch, Chipyard/X-HEEP SoC integration.
- Novel Computing Paradigms Hyperdimensional Computing, neuromorphic/memristive architectures, and other post-CMOS/post-von-Neumann directions.
- Electronic Design Automation the tooling layer (schedulers, emitters, layout engines) between an algorithm and a synthesizable design.
- Emerging Device Physics quantum transport, memristive switching, and hardware for post-quantum cryptography.
HWExplore —A Hardware Acceleration Framework for RISC-V
Julia SystemVerilog RISC-V CV-X-IF Verilator
An open-source framework that turns a computation described in Julia into a library of hand-tuned IP blocks which are tuned into a pipelined, CV-X-IF-compliant coprocessor that plugs into the X-HEEP RISC-V microcontroller. The goal is to make writing a custom RISC-V accelerator look less like hand-scheduling pipeline stages from scratch and more like describing the math.
- A dataflow IR (
HWGraph) with a multi-cycle-aware ASAP scheduler that correctly chains operations of different latencies (e.g.,MULvsADD). - A Verilog emitter that produces correctly pipelined SystemVerilog with automatic register insertion and a standardized
done_ohandshake. - A primitive library of hand-written IP (SIMD MAC, saturating arithmetic, Barrett reduction for modular/NTT-style math) that shares the same interface as auto-generated datapaths.
- An auto-generated dispatcher so both compiled and hand-optimized accelerators route through one CV-X-IF shell — independently Verilator-verified.
- Actively working toward full-system simulation on X-HEEP and a PPA (power/performance/area) benchmarking harness.
hyperdim-rocc RoCC Accelerator for Hyperdimensional Computing
Chisel/Scala Chipyard RISC-V RoCC
A custom Rocket Custom Coprocessor built in the Chipyard framework that accelerates Hyperdimensional Computing an alternative, brain-inspired compute paradigm that represents and manipulates information as very-high-dimensional binary vectors instead of scalars.
- Computes Hamming distance between memory-resident hypervectors in hardware.
- A single instruction classifies a query hypervector against an entire associative memory of class vectors, streaming data directly from the L1 data cache.
- Runtime-configurable vector length via a dedicated instruction, rather than a compile-time constant.
- Verified with bare-metal RISC-V test programs on Chipyard's Verilator simulator.
The projects below are where I built the device-level and tooling intuition that now feeds into the architecture work above.
| Domain | Project | What it does |
|---|---|---|
| Quantum Transport | NEGF Quantum Transport Simulator | Non-Equilibrium Green's Function solver modeling electron tunneling in Resonant Tunneling Diodes |
| Neuromorphic Devices | Memristive Crossbar Analysis | Simulation of HP-type memristors to analyze IR-drop and sneak-path currents in crossbar arrays |
| Neuromorphic / FPGA | Spike LIF-FPGA | SystemVerilog Leaky Integrate-and-Fire neuron on FPGA, benchmarked against a Julia software model |
| Circuit Simulator Tooling | Jyce.jl + XyceSolver | Julia bindings (via CxxWrap) for Sandia's Xyce parallel circuit simulator, with Verilog-A plugin support |
| EDA Tooling | Gdstk.jl | Julia wrapper for gdstk, exposing GDSII/OASIS layout geometry and boolean operations for chip layout |
| RF Engineering | 2.4 GHz CMOS LNA Design | Inductively-degenerated cascode LNA design and noise-figure analysis |
Working hands-on in semiconductor cleanroom environments on fabrication processes, automated optical inspection, and characterization workflows for superconducting quantum computing hardware. This is the physical counterpart to the architecture work above a direct look at what it actually takes to turn a design into working silicon, and the process/yield constraints that architecture decisions eventually have to respect.
- 2nd Place Hackathon 2025 with ANFR, Paris (Hybrid physics-data radio propagation model)
- AI Coding Competition American University of Sharjah (AUS/ASCC), UAE
- First Slingshot Coding Competition Participant
Please reach out :D