[victor-ab]

Motivation

Under a fixed-point plan, each leaf value is an i128: 16 bytes, the next largest part of a loaded model after its nodes and rank tables. A finite f64's fixed-point value is its odd significand, below 2^53, shifted left, so 8 bytes hold it exactly.

Design

layout: store fixed leaves in eight bytes

• LeafValues::Fixed holds a FixedLeaf, an i64 per leaf: the signed odd significand shifted left 8 bits, and the shift in the low byte; zero is canonical. Its i128 value is rebuilt exactly where a leaf is added, single-row and grouped.
• Every Plan::Fixed model qualifies, float32 models included: significands are below 2^53 and shifts are 0 to 123 for nonempty models (src/exact/mod.rs). Wide plans keep their limbs, and the accumulators stay 128-bit or wide.

Evidence

• On the private model, the loaded model's heap is 9% lower than with [memory] layout: exceptions take 6 bytes, with 16-bit feature-relative slots and a 32-bit fallback #67 (38% of 3.2.2's; malloc in use after loading 32% of 3.2.2's). Outputs are bitwise equal to 3.2.2's on synthetic rows and on the generated requests.
• Latency, predict_fixed per request on the generated requests, one thread, Apple M4 Pro: p50 change from [memory] layout: exceptions take 6 bytes, with 16-bit feature-relative slots and a 32-bit fallback #67, median of four paired rounds (A B B A, 1 s per cell), with the rounds' range:

	1 candidate	32	512
this PR vs #67	+0.7% (+0.7 to +2.0)	within noise (−7.6 to +2.6)	within noise (−6.4 to +1.5)

On AVX-512 (GCP c4-standard-8, Intel Xeon Platinum 8581C, SMT off, all-core turbo, one pinned core; six paired rounds), for the served requests and for groups of 128 to 1,024 rows (max_group_width 1024): like any group of 65 to 1,024 rows, these take Handle carriers and reach list_avx512:

	1 candidate	32	512	128 rows	512 rows	1,024 rows
this PR vs #67	+1.7% (+1.5 to +2.4)	+2.0% (+1.1 to +2.4)	within noise (−1.8 to +2.6)	within noise (−0.2 to +0.5)	+1.6% (+1.2 to +2.0)	within noise (−0.8 to +1.0)

Where the rounds disagree in sign, only their range is given.

• The decode is a shift and a sign-extended shift by a variable amount, about a dozen instructions per leaf on AArch64, inlined into the leaf passes.
• Tests: every shift, signed zeros, integers, the floating-point extremes and random finite values round-trip at exact scales; the import and research expectations count 8 bytes per fixed leaf.
• cargo test --release --features research passes; clippy (workspace, research, library alone) and fmt.

[ukaratay]

Approving. The packing is exact: the odd significand is below 2^53, and odd << shift fits an i128 by construction, since it came from one.