Spec: https://docs.riscv.org/reference/isa/v20260120/unpriv/scalar-crypto.html#zknh
This is an extension for speeding up operations on SHA2-family hashing algos. It has a bunch of operations related to calculating components of the hashing algorithm which software can then use to perform the complete hashing process for example for SHA256 or SHA512.
This is split into the following steps:
- Decoder module (to reside in
src/ext/zknh/decoder.sv and to be named ext__zkbh__decoder); this implements the decoding mechanism of the extension and produces a signal specifying the type of operation to perform
- Logic module (to reside in
src/ext/zknh/logic.sv and to be named ext__zkbh__logic); this implements the actual semantics of the operation per specification (see "Operation" section of each instruction); it will accept the logic selector from the decoder specifying which instruction to execute
- Integrate the decoder and logic modules into the corresponding stages, gated by
UTOSS_RISCV__ENABLE_ZKNH_EXT macro which needs to be introduced into the makefile for both sims and de1-soc synth
- Test the extension by enabling Zbkb via RISCOF to make sure it runs the arch-tests.
Generally, the microarchitecutre here will be simialr to that of B's subextensions, so check those out for inspiration.
Spec: https://docs.riscv.org/reference/isa/v20260120/unpriv/scalar-crypto.html#zknh
This is an extension for speeding up operations on SHA2-family hashing algos. It has a bunch of operations related to calculating components of the hashing algorithm which software can then use to perform the complete hashing process for example for SHA256 or SHA512.
This is split into the following steps:
src/ext/zknh/decoder.svand to be namedext__zkbh__decoder); this implements the decoding mechanism of the extension and produces a signal specifying the type of operation to performsrc/ext/zknh/logic.svand to be namedext__zkbh__logic); this implements the actual semantics of the operation per specification (see "Operation" section of each instruction); it will accept the logic selector from the decoder specifying which instruction to executeUTOSS_RISCV__ENABLE_ZKNH_EXTmacro which needs to be introduced into the makefile for both sims and de1-soc synthGenerally, the microarchitecutre here will be simialr to that of B's subextensions, so check those out for inspiration.