OmpSs-2-at-FPGA release 3.1.1

bsc-pm-ompss-at-fpga · Aug 1, 2024 · 5519be8 · 5519be8
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diff --git a/Changelog.md b/Changelog.md
@@ -1,9 +1,9 @@
 # Release 3.1.1
 
-2024-07-30
+2024-07-31
 
 * ait
-  * Version 7.5.4
+  * Version 7.5.5
   * Fixed dangling instrumentation ports
   * Minor fixes on constraints files
 * ovni

diff --git a/README.md b/README.md
@@ -15,7 +15,7 @@ This repository uses submodules to link against the different OmpSs-2@FPGA tools
 ```
 
 To obtain further information about each tool, visit the README of each tool.
-For general information, visit the [OmpSs-2@FPGA User Guide](https://pm.bsc.es/ftp/ompss-2-at-fpga/doc/user-guide-3.1.1-rc1/index.html#ompss-2-fpga-user-guide).
+For general information, visit the [OmpSs-2@FPGA User Guide](https://pm.bsc.es/ftp/ompss-2-at-fpga/doc/user-guide-3.1.1/index.html#ompss-2-fpga-user-guide).
 
 
 ### Build docker image

diff --git a/ait b/ait
+1 −1		ait/backend/xilinx/IPs/bsc_ompss_addrInterleaver.v
+1 −1		ait/backend/xilinx/IPs/bsc_ompss_axis_subset_converter.v
+1 −1		ait/backend/xilinx/IPs/bsc_ompss_axis_tid_demux.v
+1 −1		ait/backend/xilinx/IPs/bsc_ompss_hsToStreamAdapter.v
+1 −1		ait/backend/xilinx/IPs/bsc_ompss_hwcounter.v
+1 −1		ait/backend/xilinx/IPs/bsc_ompss_streamToHsAdapter.v
+20 −0		ait/backend/xilinx/board/alveo_u200/procs.tcl
+20 −0		ait/backend/xilinx/board/alveo_u280/procs.tcl
+20 −0		ait/backend/xilinx/board/alveo_u280_hbm/procs.tcl
+20 −0		ait/backend/xilinx/board/alveo_u55c/procs.tcl
+1 −1		ait/backend/xilinx/board/simulation/procs.tcl
+1 −1		ait/backend/xilinx/driver.py
+1 −1		ait/backend/xilinx/info.py
+1 −1		ait/backend/xilinx/steps/HLS.py
+1 −1		ait/backend/xilinx/steps/bitstream.py
+1 −1		ait/backend/xilinx/steps/boot.py
+1 −1		ait/backend/xilinx/steps/design.py
+1 −1		ait/backend/xilinx/steps/implementation.py
+1 −1		ait/backend/xilinx/steps/synthesis.py
+1 −1		ait/backend/xilinx/tcl/scripts/axi_datapath.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/axis_datapath.tcl
+6 −4		ait/backend/xilinx/tcl/scripts/board.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/generate_bitstream.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/generate_design.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/hwr_central_interconnect.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/hwr_dist_interconnect.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/implement_design.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/synthesize_design.tcl
+1 −1		ait/backend/xilinx/tcl/scripts/utils.tcl
+1 −1		ait/backend/xilinx/utils/checkers.py
+1 −1		ait/backend/xilinx/utils/parser.py
+2 −2		ait/frontend/config.py
+1 −1		ait/frontend/core.py
+1 −1		ait/frontend/parser.py
+1 −1		ait/frontend/utils.py
+1 −1		test/test_parser.py