Add 4-byte alignment check on pc in JAL/JALR instructions

[mininny]

Description

The RISC-V specifications indicate the following in section "2.5.1. Unconditional Jumps".

The JAL and JALR instructions will generate an instruction-address-misaligned exception if the target
address is not aligned to a four-byte boundary.

However, the three implementations (fast, slow, solidity) succeed when a unconditional jump instruction (JAL or JALR) sets a program counter pc not aligned on 4 bytes.

The jump opcodes (0x67 and 0x6F) implementation should raise an exception when the new program counter pc is not aligned on 4 bytes.

[codecov-commenter]

Codecov Report

Attention: Patch coverage is 50.00000% with 12 lines in your changes missing coverage. Please review.

Project coverage is 61.78%. Comparing base (8ff9318) to head (83efd3a).

Files with missing lines	Patch %	Lines
rvgo/fast/vm.go	50.00%	4 Missing and 2 partials ⚠️
rvgo/slow/vm.go	50.00%	4 Missing and 2 partials ⚠️

Additional details and impacted files

@@            Coverage Diff             @@
##           master      #97      +/-   ##
==========================================
- Coverage   61.89%   61.78%   -0.11%     
==========================================
  Files          27       27              
  Lines        4091     4111      +20     
==========================================
+ Hits         2532     2540       +8     
- Misses       1427     1435       +8     
- Partials      132      136       +4     

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