Version 1 of the project.
A - Single components - 17 tests
00 - DIRECT CONNECTION: OK
PASSED
01 - CLOCK: OK
PASSED
02 - TRUE: OK
PASSED
03 - FALSE: OK
PASSED
04 - AND GATE (4081): OK
PASSED
05 - OR GATE (4071): OK
PASSED
06 - NAND GATE (4011): OK
PASSED
07 - NOR GATE (4001): OK
PASSED
08 - XOR GATE (4030): OK
PASSED
09 - NOT GATE (4069): OK
PASSED
10 - DECODER (4514): KO
Invalid exit status 1
11 - ADDER (4008): KO
Invalid exit status 1
12 - COUNTER (4040): KO
Invalid exit status 1
13 - JOHNSON (4017): KO
Invalid exit status 1
14 - SHIFT (4094): KO
Invalid exit status 1
15 - D LATCH (4013): KO
Invalid exit status 1
16 - TERMINAL (4013): KO
Invalid exit status 1
B - Combinatory logic - 7 tests
01 - 5 INPUT AND GATE: OK
PASSED
02 - 5 INPUT NAND GATE: OK
PASSED
03 - 5 INPUT OR GATE: OK
PASSED
04 - 5 INPUT NOR GATE: OK
PASSED
05 - MANDION: OK
PASSED
06 - ALTERED COUNTER: KO
Invalid exit status 1
07 - ROM DUMP: KO
Invalid exit status 1
C - Sequential logic - 2 tests
01 - ONE BIT RAM: KO
Invalid exit status 1
02 - XORED DATA ROM DUMPER: KO
Invalid exit status 1