rockchip: backport latest gate link patches

Signed-off-by: Tianling Shen <[email protected]>
lkiuyu · Jan 15, 2025 · 112b21d · 112b21d
1 parent 272391c
commit 112b21d
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Showing 9 changed files with 165 additions and 164 deletions.
diff --git a/...linux/rockchip/patches-6.6/030-12-v6.14-clk-rockchip-support-clocks-registered-late.patch b/...linux/rockchip/patches-6.6/030-12-v6.14-clk-rockchip-support-clocks-registered-late.patch
@@ -0,0 +1,106 @@
+From 9e89f02da718bc912f7f253b58804d4a52efed30 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <[email protected]>
+Date: Wed, 11 Dec 2024 17:58:50 +0100
+Subject: [PATCH] clk: rockchip: support clocks registered late
+
+When some clocks are registered late and some clocks are registered
+early we need to make sure the late registered clocks report probe defer
+until the final registration has happened.
+
+But we do not want to keep reporting probe defer after the late
+registration has happened. Also not all Rockchip SoCs have late
+registered clocks and may not need to report probe defer at all.
+
+This restructures code a bit, so that there is a new function
+rockchip_clk_init_early(), which should be used for initializing the CRU
+structure on SoCs making use of late initialization in addition to the
+early init. These platforms should call rockchip_clk_finalize()
+once all clocks have been registered.
+
+Signed-off-by: Sebastian Reichel <[email protected]>
+[added EXPORT_SYMBOL_GPL(rockchip_clk_finalize) to match the early function]
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Heiko Stuebner <[email protected]>
+---
+ drivers/clk/rockchip/clk.c | 36 ++++++++++++++++++++++++++++++++----
+ drivers/clk/rockchip/clk.h |  3 +++
+ 2 files changed, 35 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -359,14 +359,17 @@ static struct clk *rockchip_clk_register
+ 	return hw->clk;
+ }
+
+-struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+-						void __iomem *base,
+-						unsigned long nr_clks)
++static struct rockchip_clk_provider *rockchip_clk_init_base(
++		struct device_node *np, void __iomem *base,
++		unsigned long nr_clks, bool has_late_clocks)
+ {
+ 	struct rockchip_clk_provider *ctx;
+ 	struct clk **clk_table;
++	struct clk *default_clk_val;
+ 	int i;
+
++	default_clk_val = ERR_PTR(has_late_clocks ? -EPROBE_DEFER : -ENOENT);
++
+ 	ctx = kzalloc(sizeof(struct rockchip_clk_provider), GFP_KERNEL);
+ 	if (!ctx)
+ 		return ERR_PTR(-ENOMEM);
+@@ -376,7 +379,7 @@ struct rockchip_clk_provider *rockchip_c
+ 		goto err_free;
+
+ 	for (i = 0; i < nr_clks; ++i)
+-		clk_table[i] = ERR_PTR(-ENOENT);
++		clk_table[i] = default_clk_val;
+
+ 	ctx->reg_base = base;
+ 	ctx->clk_data.clks = clk_table;
+@@ -393,8 +396,33 @@ err_free:
+ 	kfree(ctx);
+ 	return ERR_PTR(-ENOMEM);
+ }
++
++struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
++						void __iomem *base,
++						unsigned long nr_clks)
++{
++	return rockchip_clk_init_base(np, base, nr_clks, false);
++}
+ EXPORT_SYMBOL_GPL(rockchip_clk_init);
+
++struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
++						      void __iomem *base,
++						      unsigned long nr_clks)
++{
++	return rockchip_clk_init_base(np, base, nr_clks, true);
++}
++EXPORT_SYMBOL_GPL(rockchip_clk_init_early);
++
++void rockchip_clk_finalize(struct rockchip_clk_provider *ctx)
++{
++	int i;
++
++	for (i = 0; i < ctx->clk_data.clk_num; ++i)
++		if (ctx->clk_data.clks[i] == ERR_PTR(-EPROBE_DEFER))
++			ctx->clk_data.clks[i] = ERR_PTR(-ENOENT);
++}
++EXPORT_SYMBOL_GPL(rockchip_clk_finalize);
++
+ void rockchip_clk_of_add_provider(struct device_node *np,
+ 				  struct rockchip_clk_provider *ctx)
+ {
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -972,6 +972,9 @@ struct rockchip_clk_branch {
+
+ struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
+ 			void __iomem *base, unsigned long nr_clks);
++struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
++			void __iomem *base, unsigned long nr_clks);
++void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
+ void rockchip_clk_of_add_provider(struct device_node *np,
+ 				struct rockchip_clk_provider *ctx);
+ unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
diff --git a/...hip-rk3588-register-GATE_LINK-later.patch → ...hip-rk3588-register-GATE_LINK-later.patch b/...hip-rk3588-register-GATE_LINK-later.patch → ...hip-rk3588-register-GATE_LINK-later.patch
@@ -1,23 +1,7 @@
+From 33af96244a66f855baa43d424844bb437c79c30c Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <[email protected]>
-To: Michael Turquette <[email protected]>,
-	Stephen Boyd <[email protected]>,
-	[email protected]
-Cc: Elaine Zhang <[email protected]>,
-	Kever Yang <[email protected]>,
-	Heiko Stuebner <[email protected]>,
-	Rob Herring <[email protected]>,
-	Krzysztof Kozlowski <[email protected]>,
-	Conor Dooley <[email protected]>,
-	[email protected], [email protected],
-	Michal Tomek <[email protected]>, Ilya K <[email protected]>,
-	Chad LeClair <[email protected]>,
-	[email protected], [email protected],
-	Sebastian Reichel <[email protected]>,
-	[email protected]
-Subject: [PATCH v9 3/7] clk: rockchip: rk3588: register GATE_LINK later
-Date: Mon, 25 Mar 2024 20:33:34 +0100	[thread overview]
-Message-ID: <[email protected]> (raw)
-In-Reply-To: <[email protected]>
+Date: Wed, 11 Dec 2024 17:58:51 +0100
+Subject: [PATCH] clk: rockchip: rk3588: register GATE_LINK later
 
 The proper GATE_LINK implementation will use runtime PM to handle the
 linked gate clocks, which requires device context. Currently all clocks
@@ -33,9 +17,11 @@ are not needed early either, they have also been moved to the probe
 routine.
 
 Signed-off-by: Sebastian Reichel <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Heiko Stuebner <[email protected]>
 ---
- drivers/clk/rockchip/clk-rk3588.c | 64 +++++++++++++++++++++++++++----
- 1 file changed, 56 insertions(+), 8 deletions(-)
+ drivers/clk/rockchip/clk-rk3588.c | 66 +++++++++++++++++++++++++++----
+ 1 file changed, 58 insertions(+), 8 deletions(-)
 
 --- a/drivers/clk/rockchip/clk-rk3588.c
 +++ b/drivers/clk/rockchip/clk-rk3588.c
@@ -67,7 +53,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  	GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
  	GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
  	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
-@@ -2453,14 +2457,18 @@ static struct rockchip_clk_branch rk3588
+@@ -2453,26 +2457,31 @@ static struct rockchip_clk_branch rk3588
  	GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", HCLK_VO1, CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
  };
 
@@ -90,15 +76,21 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  	reg_base = of_iomap(np, 0);
  	if (!reg_base) {
  		pr_err("%s: could not map cru region\n", __func__);
-@@ -2473,6 +2481,7 @@ static void __init rk3588_clk_init(struc
+ 		return;
+ 	}
+
+-	ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
++	ctx = rockchip_clk_init_early(np, reg_base, clk_nr_clks);
+ 	if (IS_ERR(ctx)) {
+ 		pr_err("%s: rockchip clk init failed\n", __func__);
  		iounmap(reg_base);
  		return;
  	}
 +	early_ctx = ctx;
 
  	rockchip_clk_register_plls(ctx, rk3588_pll_clks,
  				   ARRAY_SIZE(rk3588_pll_clks),
-@@ -2491,14 +2500,53 @@ static void __init rk3588_clk_init(struc
+@@ -2491,14 +2500,55 @@ static void __init rk3588_clk_init(struc
  			&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
  			ARRAY_SIZE(rk3588_cpub1clk_rates));
 
@@ -119,7 +111,8 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  				       ARRAY_SIZE(rk3588_clk_branches));
 
 -	rk3588_rst_init(np, reg_base);
--
++	rockchip_clk_finalize(ctx);
+
 +	rk3588_rst_init(np, ctx->reg_base);
  	rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
 

diff --git a/...chip-expose-rockchip_clk_set_lookup.patch → ...chip-expose-rockchip_clk_set_lookup.patch b/...chip-expose-rockchip_clk_set_lookup.patch → ...chip-expose-rockchip_clk_set_lookup.patch
@@ -1,30 +1,16 @@
+From fe0fb6675fa48cade97d8bcd46226479c4a704df Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <[email protected]>
-To: Michael Turquette <[email protected]>,
-	Stephen Boyd <[email protected]>,
-	[email protected]
-Cc: Elaine Zhang <[email protected]>,
-	Kever Yang <[email protected]>,
-	Heiko Stuebner <[email protected]>,
-	Rob Herring <[email protected]>,
-	Krzysztof Kozlowski <[email protected]>,
-	Conor Dooley <[email protected]>,
-	[email protected], [email protected],
-	Michal Tomek <[email protected]>, Ilya K <[email protected]>,
-	Chad LeClair <[email protected]>,
-	[email protected], [email protected],
-	Sebastian Reichel <[email protected]>,
-	[email protected]
-Subject: [PATCH v9 4/7] clk: rockchip: expose rockchip_clk_set_lookup
-Date: Mon, 25 Mar 2024 20:33:35 +0100	[thread overview]
-Message-ID: <[email protected]> (raw)
-In-Reply-To: <[email protected]>
+Date: Wed, 11 Dec 2024 17:58:52 +0100
+Subject: [PATCH] clk: rockchip: expose rockchip_clk_set_lookup
 
 Move rockchip_clk_add_lookup to clk.h, so that it can be used
 by sub-devices with their own driver. These might also have to
 do a lookup, so rename the function to rockchip_clk_set_lookup
-and add a matching rockchip_clk_add_lookup.
+and add a matching rockchip_clk_get_lookup.
 
 Signed-off-by: Sebastian Reichel <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Heiko Stuebner <[email protected]>
 ---
  drivers/clk/rockchip/clk.c | 14 ++++----------
  drivers/clk/rockchip/clk.h | 12 ++++++++++++
@@ -54,7 +40,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
 
  		/* notifier on the fraction divider to catch rate changes */
  		if (frac->mux_frac_idx >= 0) {
-@@ -424,7 +418,7 @@ void rockchip_clk_register_plls(struct r
+@@ -452,7 +446,7 @@ void rockchip_clk_register_plls(struct r
  			continue;
  		}
 
@@ -63,7 +49,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  	}
  }
  EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
-@@ -586,7 +580,7 @@ void rockchip_clk_register_branches(stru
+@@ -614,7 +608,7 @@ void rockchip_clk_register_branches(stru
  			continue;
  		}
 
@@ -72,7 +58,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  	}
  }
  EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
-@@ -610,7 +604,7 @@ void rockchip_clk_register_armclk(struct
+@@ -638,7 +632,7 @@ void rockchip_clk_register_armclk(struct
  		return;
  	}
 
@@ -101,4 +87,4 @@ Signed-off-by: Sebastian Reichel <[email protected]>
 +
  struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
  			void __iomem *base, unsigned long nr_clks);
- void rockchip_clk_of_add_provider(struct device_node *np,
+ struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
diff --git a/...implement-linked-gate-clock-support.patch → ...implement-linked-gate-clock-support.patch b/...implement-linked-gate-clock-support.patch → ...implement-linked-gate-clock-support.patch
@@ -1,23 +1,7 @@
+From c62fa612cfa66ab58ab215e5afc95c43c613b513 Mon Sep 17 00:00:00 2001
 From: Sebastian Reichel <[email protected]>
-To: Michael Turquette <[email protected]>,
-	Stephen Boyd <[email protected]>,
-	[email protected]
-Cc: Elaine Zhang <[email protected]>,
-	Kever Yang <[email protected]>,
-	Heiko Stuebner <[email protected]>,
-	Rob Herring <[email protected]>,
-	Krzysztof Kozlowski <[email protected]>,
-	Conor Dooley <[email protected]>,
-	[email protected], [email protected],
-	Michal Tomek <[email protected]>, Ilya K <[email protected]>,
-	Chad LeClair <[email protected]>,
-	[email protected], [email protected],
-	Sebastian Reichel <[email protected]>,
-	[email protected]
-Subject: [PATCH v9 6/7] clk: rockchip: implement linked gate clock support
-Date: Mon, 25 Mar 2024 20:33:37 +0100	[thread overview]
-Message-ID: <[email protected]> (raw)
-In-Reply-To: <[email protected]>
+Date: Wed, 11 Dec 2024 17:58:53 +0100
+Subject: [PATCH] clk: rockchip: implement linked gate clock support
 
 Recent Rockchip SoCs have a new hardware block called Native Interface
 Unit (NIU), which gates clocks to devices behind them. These clock
@@ -36,13 +20,15 @@ to use the correct runtime PM operations. Thus the complete handling
 of these clocks has been moved into its own driver.
 
 Signed-off-by: Sebastian Reichel <[email protected]>
+Link: https://lore.kernel.org/r/[email protected]
+Signed-off-by: Heiko Stuebner <[email protected]>
 ---
  drivers/clk/rockchip/Makefile     |  1 +
- drivers/clk/rockchip/clk-rk3588.c | 23 +------
- drivers/clk/rockchip/clk.c        | 52 ++++++++++++++++
- drivers/clk/rockchip/clk.h        | 25 ++++++++
- drivers/clk/rockchip/gate-link.c  | 99 +++++++++++++++++++++++++++++++
- 5 files changed, 179 insertions(+), 21 deletions(-)
+ drivers/clk/rockchip/clk-rk3588.c | 23 +--------
+ drivers/clk/rockchip/clk.c        | 52 +++++++++++++++++++
+ drivers/clk/rockchip/clk.h        | 25 +++++++++
+ drivers/clk/rockchip/gate-link.c  | 85 +++++++++++++++++++++++++++++++
+ 5 files changed, 165 insertions(+), 21 deletions(-)
  create mode 100644 drivers/clk/rockchip/gate-link.c
 
 --- a/drivers/clk/rockchip/Makefile
@@ -92,8 +78,8 @@ Signed-off-by: Sebastian Reichel <[email protected]>
 +	rockchip_clk_register_late_branches(dev, ctx, rk3588_clk_branches,
 +					    ARRAY_SIZE(rk3588_clk_branches));
 
- 	rk3588_rst_init(np, ctx->reg_base);
- 	rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
+ 	rockchip_clk_finalize(ctx);
+
 --- a/drivers/clk/rockchip/clk.c
 +++ b/drivers/clk/rockchip/clk.c
 @@ -19,6 +19,7 @@
@@ -104,7 +90,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  #include <linux/regmap.h>
  #include <linux/reboot.h>
 
-@@ -440,6 +441,29 @@ unsigned long rockchip_clk_find_max_clk_
+@@ -468,6 +469,29 @@ unsigned long rockchip_clk_find_max_clk_
  }
  EXPORT_SYMBOL_GPL(rockchip_clk_find_max_clk_id);
 
@@ -134,7 +120,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
  				    struct rockchip_clk_branch *list,
  				    unsigned int nr_clk)
-@@ -565,6 +589,9 @@ void rockchip_clk_register_branches(stru
+@@ -593,6 +617,9 @@ void rockchip_clk_register_branches(stru
  				list->div_width, list->div_flags,
  				ctx->reg_base, &ctx->lock);
  			break;
@@ -144,7 +130,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  		}
 
  		/* none of the cases above matched */
-@@ -585,6 +612,31 @@ void rockchip_clk_register_branches(stru
+@@ -613,6 +640,31 @@ void rockchip_clk_register_branches(stru
  }
  EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
 
@@ -226,8 +212,8 @@ Signed-off-by: Sebastian Reichel <[email protected]>
 +
  struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
  			void __iomem *base, unsigned long nr_clks);
- void rockchip_clk_of_add_provider(struct device_node *np,
-@@ -991,6 +1012,10 @@ unsigned long rockchip_clk_find_max_clk_
+ struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
+@@ -994,6 +1015,10 @@ unsigned long rockchip_clk_find_max_clk_
  void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
  				    struct rockchip_clk_branch *list,
  				    unsigned int nr_clk);
@@ -240,7 +226,7 @@ Signed-off-by: Sebastian Reichel <[email protected]>
  				unsigned int nr_pll, int grf_lock_offset);
 --- /dev/null
 +++ b/drivers/clk/rockchip/gate-link.c
-@@ -0,0 +1,99 @@
+@@ -0,0 +1,85 @@
 +// SPDX-License-Identifier: GPL-2.0-or-later
 +/*
 + * Copyright (c) 2024 Collabora Ltd.
@@ -308,30 +294,16 @@ Signed-off-by: Sebastian Reichel <[email protected]>
 +	return ret;
 +}
 +
-+static void rk_clk_gate_link_remove(struct platform_device *pdev)
-+{
-+	struct rockchip_gate_link_platdata *pdata;
-+	struct device *dev = &pdev->dev;
-+	struct clk *clk, *linked_clk;
-+
-+	pdata = dev_get_platdata(dev);
-+	clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->id);
-+	linked_clk = rockchip_clk_get_lookup(pdata->ctx, pdata->clkbr->linked_clk_id);
-+	rockchip_clk_set_lookup(pdata->ctx, ERR_PTR(-ENODEV), pdata->clkbr->id);
-+	clk_unregister_gate(clk);
-+	pm_clk_remove_clk(dev, linked_clk);
-+}
-+
 +static const struct dev_pm_ops rk_clk_gate_link_pm_ops = {
 +	SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
 +};
 +
-+struct platform_driver rk_clk_gate_link_driver = {
++static struct platform_driver rk_clk_gate_link_driver = {
 +	.probe		= rk_clk_gate_link_probe,
-+	.remove_new	= rk_clk_gate_link_remove,
 +	.driver		= {
 +		.name	= "rockchip-gate-link-clk",
 +		.pm = &rk_clk_gate_link_pm_ops,
++		.suppress_bind_attrs = true,
 +	},
 +};
 +