Bug 1850864 - [riscv]wasm: Generalize load/store instructions for mul…

…tiple memories. r=jseward Depends on D187164 Differential Revision: https://phabricator.services.mozilla.com/D187165 UltraBlame original commit: 98f0129136a137644c8fa17d85f655c7d98abeb1
marco-c · Oct 16, 2023 · b7daa97 · b7daa97
1 parent ac3f235
commit b7daa97
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Showing 2 changed files with 22 additions and 11 deletions.
diff --git a/js/src/jit/riscv64/LIR-riscv64.h b/js/src/jit/riscv64/LIR-riscv64.h
@@ -1461,6 +1461,22 @@ getInt64Operand
 ;
 }
 const
+LAllocation
+*
+memoryBase
+(
+)
+{
+return
+getOperand
+(
+1
++
+INT64_PIECES
+)
+;
+}
+const
 MWasmAtomicExchangeHeap
 *
 mir

diff --git a/js/src/wasm/WasmBCMemory.cpp b/js/src/wasm/WasmBCMemory.cpp
@@ -2996,12 +2996,6 @@ temp
 elif
 defined
 (
-JS_CODEGEN_MIPS64
-)
-|
-|
-defined
-(
 JS_CODEGEN_RISCV64
 )
 return
@@ -3010,6 +3004,7 @@ executeLoad
 access
 check
 instance
+memoryBase
 RegI32
 (
 ptr
@@ -7151,7 +7146,7 @@ const
 MemoryAccessDesc
 &
 access
-BaseIndex
+Address
 srcAddr
 AtomicOp
 op
@@ -8274,7 +8269,7 @@ const
 MemoryAccessDesc
 &
 access
-BaseIndex
+Address
 srcAddr
 AtomicOp
 op
@@ -9597,7 +9592,7 @@ const
 MemoryAccessDesc
 &
 access
-BaseIndex
+Address
 srcAddr
 RegI32
 rv
@@ -11780,7 +11775,7 @@ const
 MemoryAccessDesc
 &
 access
-BaseIndex
+Address
 srcAddr
 RegI32
 rexpect
@@ -13161,7 +13156,7 @@ const
 MemoryAccessDesc
 &
 access
-BaseIndex
+Address
 srcAddr
 RegI64
 rexpect