Fix register field widths - #46
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i509VCB merged 2 commits intoAug 31, 2026
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The SVD gave these three a single bit where IMASK and RIS got eight, so only interrupt 0 of the group was reachable through them. hw_cpuss.h masks all five with 0xFF.
GEN_EVENT1 masks DIO16 to DIO31 at bits 16 to 31, but both event blocks shared a 16-bit fieldset based at bit 0, so the upper half was reachable only at the wrong offset.
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Four conflicts, all against changes this branch already carried: cpuss_v1 and gpio_v1 are mspm0-rs#46 coming back. The branch has the same widths under the cleanup pass, which merges the five interrupt fieldsets and drops the trivial enums, so the branch side was kept. Flattening both revisions to register offset and field bit-ranges shows no difference: 15 registers in cpuss_v1, 62 in gpio_v1. ./d takes the Darwin job count, which supersedes the plain nproc here. GENERATE_PERIPHERALS takes both entries.
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Two widths that are narrower than the hardware, so a driver written against them addresses the wrong bits.
No new peripherals, just the two corrections.
This is the first of a series replacing #44.