Merge pull request #217 from riscv-non-isa/fix-rvtest-case-strings

fix the lower case `i` in the `RVTEST_CASE` macros used in the shift …
riscv-non-isa · Oct 15, 2021 · aebb356 · aebb356
2 parents 1070548 + 7f99888
commit aebb356
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Showing 10 changed files with 13 additions and 9 deletions.
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -1,4 +1,8 @@
 # CHANGELOG
+
+## [2.5.3] - 2021-10-15
+  - fix the lower case `i` in the `RVTEST_CASE` macros used in the shift operation tests.
+
 ## [2.5.2] - 2021-10-14
   - update format for aes32 and sm4 instructions
   - update reference signature for sha256 and sm3 instructions in rv64i_m/K_unratified

diff --git a/riscv-test-suite/rv32i_m/I/src/sll-01.S b/riscv-test-suite/rv32i_m/I/src/sll-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32i")
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/I/src/sra-01.S b/riscv-test-suite/rv32i_m/I/src/sra-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32i")
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv32i_m/I/src/srl-01.S b/riscv-test-suite/rv32i_m/I/src/srl-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV32i")
+RVTEST_ISA("RV32I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv64i_m/I/src/sll-01.S b/riscv-test-suite/rv64i_m/I/src/sll-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64i")
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv64i_m/I/src/sllw-01.S b/riscv-test-suite/rv64i_m/I/src/sllw-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64i")
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv64i_m/I/src/sra-01.S b/riscv-test-suite/rv64i_m/I/src/sra-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64i")
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv64i_m/I/src/sraw-01.S b/riscv-test-suite/rv64i_m/I/src/sraw-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64i")
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv64i_m/I/src/srl-01.S b/riscv-test-suite/rv64i_m/I/src/srl-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64i")
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point

diff --git a/riscv-test-suite/rv64i_m/I/src/srlw-01.S b/riscv-test-suite/rv64i_m/I/src/srlw-01.S
@@ -17,7 +17,7 @@
 // 
 #include "model_test.h"
 #include "arch_test.h"
-RVTEST_ISA("RV64i")
+RVTEST_ISA("RV64I")
 
 .section .text.init
 .globl rvtest_entry_point