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AxiSpiMaster - Fix bug in shadow RAM for multi-chip configurations #1205

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AxiSpiMaster - Fix bug in shadow RAM for multi-chip configurations #1205

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c3551b8
Fix shadow ram for multi-chip configurations
bengineerd Oct 7, 2024
641e11b
Merge remote-tracking branch 'origin/pre-release' into axi-spi-master
ruck314 Oct 10, 2024
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35 changes: 19 additions & 16 deletions protocols/spi/rtl/AxiSpiMaster.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -55,8 +55,8 @@ entity AxiSpiMaster is
axiWriteMaster : in AxiLiteWriteMasterType;
axiWriteSlave : out AxiLiteWriteSlaveType;
-- Copy of the shadow memory (SHADOW_EN_G=true)
shadowAddr : in slv(ADDRESS_SIZE_G-1 downto 0) := (others => '0');
shadowData : out slv(DATA_SIZE_G-1 downto 0) := (others => '0');
shadowAddr : in slv(log2(SPI_NUM_CHIPS_G)+ADDRESS_SIZE_G-1 downto 0) := (others => '0');
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@bengineerd Should you use BitSize (instead of log2()) here?

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As it turns out neither log2 nor bitSize are correct. We want the function to return 0 when given SPI_NUM_CHIPS_G=1. Otherwise shadowAddr will be one bit larger than it was before and break builds. I will fix it.

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Unless we just want to update the one and only application that uses shadowAddr.
https://github.com/slaclab/amc-carrier-core/blob/21ce13174561512fc1ec0e2fb1d071eb8db88381/AppHardware/RtmCryoDet/rtl/RtmCryoDet.vhd#L527

shadowData : out slv(DATA_SIZE_G-1 downto 0) := (others => '0');
-- SPI Interface
coreSclk : out sl;
coreSDin : in sl;
Expand All @@ -77,7 +77,8 @@ architecture rtl of AxiSpiMaster is
type StateType is (WAIT_AXI_TXN_S, WAIT_CYCLE_S, WAIT_CYCLE_SHADOW_S, WAIT_SPI_TXN_DONE_S, SHADOW_READ_DONE_S);


signal memData : slv(DATA_SIZE_G-1 downto 0) := (others => '0');
signal memData : slv(DATA_SIZE_G-1 downto 0) := (others => '0');
signal memAddr : slv(ADDRESS_SIZE_G+CHIP_BITS_C-1 downto 0) := (others => '0');

-- Registers
type RegType is record
Expand Down Expand Up @@ -105,26 +106,27 @@ architecture rtl of AxiSpiMaster is
begin

SHADOW_RAM_GEN : if (SHADOW_EN_G) generate
memAddr <= r.chipSel & r.wrData(DATA_SIZE_G+ADDRESS_SIZE_G-1 downto DATA_SIZE_G);
U_DualPortRam_1 : entity surf.DualPortRam
generic map (
TPD_G => TPD_G,
MEMORY_TYPE_G => SHADOW_MEM_TYPE_G,
REG_EN_G => false,
DATA_WIDTH_G => DATA_SIZE_G,
ADDR_WIDTH_G => ADDRESS_SIZE_G)
ADDR_WIDTH_G => ADDRESS_SIZE_G+CHIP_BITS_C)
port map (
clka => axiClk, -- [in]
ena => '1', -- [in]
wea => r.wrEn, -- [in]
rsta => axiRst, -- [in]
addra => r.wrData(DATA_SIZE_G+ADDRESS_SIZE_G-1 downto DATA_SIZE_G), -- [in]
dina => r.wrData(DATA_SIZE_G-1 downto 0), -- [in]
douta => memData, -- [out]
clkb => axiClk, -- [in]
enb => '1', -- [in]
rstb => axiRst, -- [in]
addrb => shadowAddr, -- [in]
doutb => shadowData); -- [out]
clka => axiClk, -- [in]
ena => '1', -- [in]
wea => r.wrEn, -- [in]
rsta => axiRst, -- [in]
addra => memAddr, -- [in]
dina => r.wrData(DATA_SIZE_G-1 downto 0), -- [in]
douta => memData, -- [out]
clkb => axiClk, -- [in]
enb => '1', -- [in]
rstb => axiRst, -- [in]
addrb => shadowAddr, -- [in]
doutb => shadowData); -- [out]

end generate SHADOW_RAM_GEN;

Expand All @@ -147,6 +149,7 @@ begin
if (ADDRESS_SIZE_G > 0) then
v.wrData(DATA_SIZE_G+ADDRESS_SIZE_G-1 downto DATA_SIZE_G) := axiReadMaster.araddr(2+ADDRESS_SIZE_G-1 downto 2); -- setup memAddr
end if;
v.chipSel := axiReadMaster.araddr(CHIP_BITS_C+ADDRESS_SIZE_G+1 downto 2+ADDRESS_SIZE_G);
elsif (MODE_G = "WO") then
axiSlaveReadResponse(v.axiReadSlave, AXI_RESP_DECERR_C);
else
Expand Down
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