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mohasnik / Network-On-Chip

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RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer units, routing units, switch allocators, switches, routers, and nodes, along with comprehensive high-level testing scenarios. Developed as part of a Core-Based Embedded System Design course.

verilog systemverilog verilog-hdl system-design network-on-chip rtl-tests rtl-de
  • Updated Jul 12, 2024
  • SystemVerilog

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