GitHub - trivialmips/TrivialMIPS: MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support · GitHub

Name		Name	Last commit message	Last commit date
doc		doc
software @ 63cb05a		software @ 63cb05a
src		src
testbench		testbench
vivado		vivado
.gitlab-ci.yml		.gitlab-ci.yml
.gitmodules		.gitmodules

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MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

cpu fpga fpga-soc mips systemverilog xilinx

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