Repository navigation
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
A capacitor with a short ground-plane drop can receive a false length error when another branch of the ground net is attributed to the same source trace. On the complete captured RVboy board, C_SOC_54's 0.645 mm drop was reported as 13.51 mm. Its direct connection is 2.245 mm including the conservative 1.6 mm via allowance, below the existing 5 mm limit.
For one-port-to-net constraints, recognize direct single-layer drops only when they start at the actual source port and reach an emitted via whose annulus contacts the requested net's filled pour. Respect layer spans, pour holes, drill holes, and reversed route order. Other route shapes retain the aggregate check; genuine overlength drops still fail. This changes validation, not copper or constraints.
The repro preserves the complete captured input and crops only the rendered viewport around the affected area.
The latest complete native build exposed the same false positive within a single continuous route: C_RTC_OUT reaches GND after 1.122 mm of top copper, but its route continues across inner1 to another ground pad. Measure the prefix up to the first verified plane-contacting via, in either route orientation. This gives 2.722 mm including the via allowance, instead of 8.097 mm. A 2.7 mm limit still fails, and removing the pour restores the aggregate violation.
Validation: 10 focused tests / 39 assertions pass, including both complete-board fixtures, missing via/pour, wrong net/layer, displaced source port, pour hole, copper inside the drill, genuine overlength, reversed continuous routes, two-port and fragmented trace checks. TypeScript, package build, focused Biome formatting, and git diff checks pass. All seven CI workflows pass on
2d005cd: full tests, TypeScript, formatting, dependency check, build, packed consumer and package preview. Its only change from the installedc4b0d42artifact is a type guard in the visual test; runtime source is identical. The fresh RVboy native rebuild is running with that verified runtime.