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Pepijn de Vos edited this page Nov 19, 2024 · 5 revisions

DL

The DL primitive is a commonly used latch with an active-high control signal G. It has three ports: D for input data, Q for output data, and G for control signal input. The initial value of the DL primitive is 1'b0 by default, and can be set to any other value using the INIT parameter in its instantiation.

This device is not yet supported in Apicula

Ports

Port Size Direction
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DL #(
    .INIT(INIT)
) dl_inst (
    .D(D),
    .G(G),
    .Q(Q)
);

DLC

The Gowin DLC primitive is a latch with the function of clear. It has three ports: D (data input), CLEAR (asynchronous clear, active-high), and G (control signal, active-high). The primitive also has an output port Q (data output).

This device is not yet supported in Apicula

Ports

Port Size Direction
CLEAR 1 input
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLC #(
    .INIT(INIT)
) dlc_inst (
    .CLEAR(CLEAR),
    .D(D),
    .G(G),
    .Q(Q)
);

DLCE

The DLCE (Data Latch with Asynchronous Clear and Latch Enable) primitive is a latch that has the function of enable control and asynchronous clear. The control signal G is active-high, indicating that it must be high to activate the latch. This means that data can only be latched when the G signal is high, and the CLEAR signal is used for an asynchronous reset, where clearing the latch overrides any other operation.

This device is not yet supported in Apicula

Ports

Port Size Direction
CLEAR 1 input
D 1 input
G 1 input
GE 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLCE #(
    .INIT(INIT)
) dlce_inst (
    .CLEAR(CLEAR),
    .D(D),
    .G(G),
    .GE(GE),
    .Q(Q)
);

DLE

The DLE (Data Latch with Latch Enable) primitive enables or disables data from being stored in a latch, depending on the active-high control signal G. When G is high, the latch can store input data D; when G is low, the latch remains unchanged, retaining its previous value.

This device is not yet supported in Apicula

Ports

Port Size Direction
CE 1 input
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLE #(
    .INIT(INIT)
) dle_inst (
    .CE(CE),
    .D(D),
    .G(G),
    .Q(Q)
);

DLL

This device is not yet supported in Apicula

Ports

Port Size Direction
CLKIN 1 input
LOCK 1 output
RESET 1 input
STEP 8 output
STOP 1 input
UPDNCNTL 1 input

Parameters

Parameter Default Value
CODESCAL 000
DIV_SEL 0 (0b0)
DLL_FORCE 0 (0b00000000000000000000000000000000)
SCAL_EN true

Verilog Instantiation

DLL #(
    .CODESCAL(CODESCAL),
    .DIV_SEL(DIV_SEL),
    .DLL_FORCE(DLL_FORCE),
    .SCAL_EN(SCAL_EN)
) dll_inst (
    .CLKIN(CLKIN),
    .LOCK(LOCK),
    .RESET(RESET),
    .STEP(STEP),
    .STOP(STOP),
    .UPDNCNTL(UPDNCNTL)
);

DLLDLY

The DLLDLY primitive is a clock delay module that adjusts the input clock according to the CSTEP or DLLSTEP signal, generating the corresponding phase delay to get the delayed output based on CLKIN. The delay step size of CSTEP/DLLSTEP is about 12.5ps, and delay adjustment supports static, dynamic, and adaptive modes.

This device is not yet supported in Apicula

Ports

Port Size Direction
CLKIN 1 input
CLKOUT 1 output
CSTEP 8 input
DLLSTEP 8 input
FLAG 1 output
LOADN 1 input
MOVE 1 input

Parameters

Parameter Default Value
ADAPT_EN FALSE
DLY_ADJ 0 (0b00000000000000000000000000000000)
DLY_SIGN 0 (0b0)
DYN_DLY_EN FALSE
STEP_SEL 0 (0b0)

Verilog Instantiation

DLLDLY #(
    .ADAPT_EN(ADAPT_EN),
    .DLY_ADJ(DLY_ADJ),
    .DLY_SIGN(DLY_SIGN),
    .DYN_DLY_EN(DYN_DLY_EN),
    .STEP_SEL(STEP_SEL)
) dlldly_inst (
    .CLKIN(CLKIN),
    .CLKOUT(CLKOUT),
    .CSTEP(CSTEP),
    .DLLSTEP(DLLSTEP),
    .FLAG(FLAG),
    .LOADN(LOADN),
    .MOVE(MOVE)
);

DLN

The Gowin DLN primitive is a latch with the control signal active-low, meaning its input (G) is used in an inverted manner. This implies that the gate is normally high and becomes low to enable the latch, which stores data at inputs D. The output (Q) of this latch reflects the stored data.

This device is not yet supported in Apicula

Ports

Port Size Direction
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLN #(
    .INIT(INIT)
) dln_inst (
    .D(D),
    .G(G),
    .Q(Q)
);

DLNC

The DLNC (Data Latch with Asynchronous Clear and Inverted Gate) primitive has a function of clear, and its control signal G is active-low.

This device is not yet supported in Apicula

Ports

Port Size Direction
CLEAR 1 input
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLNC #(
    .INIT(INIT)
) dlnc_inst (
    .CLEAR(CLEAR),
    .D(D),
    .G(G),
    .Q(Q)
);

DLNCE

The DLNCE (Data Latch with Asynchronous Clear, Latch Enable, and Inverted Gate) primitive is a latch that enables control and clear functionality. It takes in input data D, an asynchronous clear signal CLEAR (active-high), a control signal G (active-low), a clock enable signal CE, and outputs the stored data Q. The initial value of the DLNCE is 0 by default.

This device is not yet supported in Apicula

Ports

Port Size Direction
CE 1 input
CLEAR 1 input
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLNCE #(
    .INIT(INIT)
) dlnce_inst (
    .CE(CE),
    .CLEAR(CLEAR),
    .D(D),
    .G(G),
    .Q(Q)
);

DLNE

The DLNE primitive is a latch with enable control, where the control signal G is active-low. It takes in data D, clock enable CE, and outputs Q, with an initial value of 1'b0. The G input can be used to control the latch's behavior, but its specific functionality beyond being active-low is not specified.

This device is not yet supported in Apicula

Ports

Port Size Direction
CE 1 input
D 1 input
G 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 0 (0b0)

Verilog Instantiation

DLNE #(
    .INIT(INIT)
) dlne_inst (
    .CE(CE),
    .D(D),
    .G(G),
    .Q(Q)
);

DLNP

The DLNP primitive has the function of asynchronous preset, and control signal G is active-low.

This device is not yet supported in Apicula

Ports

Port Size Direction
D 1 input
G 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DLNP #(
    .INIT(INIT)
) dlnp_inst (
    .D(D),
    .G(G),
    .PRESET(PRESET),
    .Q(Q)
);

DLNPE

The DLNPE (Data Latch with Asynchronous Preset, Latch Enable, and Inverted Gate) primitive is a latch that provides enable control and preset functionality. It has an active-low control signal G and an asynchronous preset input PRESET, which is active-high. The primitive also features a clock enable input CE, and its output Q provides the data output.

This device is not yet supported in Apicula

Ports

Port Size Direction
CE 1 input
D 1 input
G 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DLNPE #(
    .INIT(INIT)
) dlnpe_inst (
    .CE(CE),
    .D(D),
    .G(G),
    .PRESET(PRESET),
    .Q(Q)
);

DLP

The Data Latch with Asynchronous Preset (DLP) is a latch that can be preset asynchronously, meaning its output (Q) can be set to the value of the data input (D) immediately, without waiting for a clock signal. This is achieved through the active-high control signal G and the asynchronous preset input (PRESET). The DLP primitive has four ports: D (data), PRESET (asynchronous preset), G (control signal), and Q (output data).

This device is not yet supported in Apicula

Ports

Port Size Direction
D 1 input
G 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DLP #(
    .INIT(INIT)
) dlp_inst (
    .D(D),
    .G(G),
    .PRESET(PRESET),
    .Q(Q)
);

DLPE

The DLPE (Data Latch with Asynchronous Preset and Latch Enable) primitive is a latch that provides enable control and preset functions. It has an active-high control signal G, which enables or disables the latch. The DLPE also features an asynchronous preset function, where a high signal on the PRESET input can set the output Q to its initial value, regardless of the state of the D input.

This device is not yet supported in Apicula

Ports

Port Size Direction
D 1 input
G 1 input
GE 1 input
PRESET 1 input
Q 1 output

Parameters

Parameter Default Value
INIT 1 (0b1)

Verilog Instantiation

DLPE #(
    .INIT(INIT)
) dlpe_inst (
    .D(D),
    .G(G),
    .GE(GE),
    .PRESET(PRESET),
    .Q(Q)
);
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