EMCU

The Gowin EMCU primitive supports various functions, including two UARTs, two Timers, a Watchdog, 16-bit GPIO, two additional UARTs, JTAGs, six User Interrupt interfaces, AHB Flash read interface, AHB Sram read/write interface, two AHB bus extension interfaces, and one APB bus extension interface.

This device is supported in Apicula.

Ports

Port	Size	Direction
APBTARGEXP2PADDR	12	output
APBTARGEXP2PENABLE	1	output
APBTARGEXP2PPROT	3	output
APBTARGEXP2PRDATA	32	input
APBTARGEXP2PREADY	1	input
APBTARGEXP2PSEL	1	output
APBTARGEXP2PSLVERR	1	input
APBTARGEXP2PSTRB	4	output
APBTARGEXP2PWDATA	32	output
APBTARGEXP2PWRITE	1	output
DAPJTAGNSW	1	output
DAPNTDOEN	1	output
DAPNTRST	1	input
DAPSWCLKTCK	1	input
DAPSWDITMS	1	input
DAPTDI	1	input
DAPTDO	1	output
FCLK	1	input
FLASHERR	1	input
FLASHINT	1	input
GPINT	5	input
INITEXP0EXREQ	1	input
INITEXP0EXRESP	1	output
INITEXP0HADDR	32	input
INITEXP0HAUSER	1	input
INITEXP0HBURST	3	input
INITEXP0HMASTER	4	input
INITEXP0HMASTLOCK	1	input
INITEXP0HPROT	4	input
INITEXP0HRDATA	32	output
INITEXP0HREADY	1	output
INITEXP0HRESP	1	output
INITEXP0HRUSER	3	output
INITEXP0HSEL	1	input
INITEXP0HSIZE	3	input
INITEXP0HTRANS	2	input
INITEXP0HWDATA	32	input
INITEXP0HWRITE	1	input
INITEXP0HWUSER	4	input
INITEXP0MEMATTR	2	input
INTMONITOR	1	output
IOEXPINPUTI	16	input
IOEXPOUTPUTENO	16	output
IOEXPOUTPUTO	16	output
MTXHRESETN	1	output
MTXREMAP	4	input
PORESETN	1	input
RTCSRCCLK	1	input
SRAM0ADDR	13	output
SRAM0CS	1	output
SRAM0RDATA	32	input
SRAM0WDATA	32	output
SRAM0WREN	4	output
SYSRESETN	1	input
TARGEXP0EXREQ	1	output
TARGEXP0EXRESP	1	input
TARGEXP0HADDR	32	output
TARGEXP0HAUSER	1	output
TARGEXP0HBURST	3	output
TARGEXP0HMASTER	4	output
TARGEXP0HMASTLOCK	1	output
TARGEXP0HPROT	4	output
TARGEXP0HRDATA	32	input
TARGEXP0HREADYMUX	1	output
TARGEXP0HREADYOUT	1	input
TARGEXP0HRESP	1	input
TARGEXP0HRUSER	3	input
TARGEXP0HSEL	1	output
TARGEXP0HSIZE	3	output
TARGEXP0HTRANS	2	output
TARGEXP0HWDATA	32	output
TARGEXP0HWRITE	1	output
TARGEXP0HWUSER	4	output
TARGEXP0MEMATTR	2	output
TARGFLASH0EXRESP	1	input
TARGFLASH0HADDR	29	output
TARGFLASH0HBURST	3	output
TARGFLASH0HRDATA	32	input
TARGFLASH0HREADYMUX	1	output
TARGFLASH0HREADYOUT	1	input
TARGFLASH0HRESP	1	input
TARGFLASH0HRUSER	3	input
TARGFLASH0HSEL	1	output
TARGFLASH0HSIZE	3	output
TARGFLASH0HTRANS	2	output
TPIUTRACECLK	1	output
TPIUTRACEDATA	4	output
UART0BAUDTICK	1	output
UART0RXDI	1	input
UART0TXDO	1	output
UART1BAUDTICK	1	output
UART1RXDI	1	input
UART1TXDO	1	output

Verilog Instantiation

EMCU emcu_inst (
    .APBTARGEXP2PADDR(APBTARGEXP2PADDR),
    .APBTARGEXP2PENABLE(APBTARGEXP2PENABLE),
    .APBTARGEXP2PPROT(APBTARGEXP2PPROT),
    .APBTARGEXP2PRDATA(APBTARGEXP2PRDATA),
    .APBTARGEXP2PREADY(APBTARGEXP2PREADY),
    .APBTARGEXP2PSEL(APBTARGEXP2PSEL),
    .APBTARGEXP2PSLVERR(APBTARGEXP2PSLVERR),
    .APBTARGEXP2PSTRB(APBTARGEXP2PSTRB),
    .APBTARGEXP2PWDATA(APBTARGEXP2PWDATA),
    .APBTARGEXP2PWRITE(APBTARGEXP2PWRITE),
    .DAPJTAGNSW(DAPJTAGNSW),
    .DAPNTDOEN(DAPNTDOEN),
    .DAPNTRST(DAPNTRST),
    .DAPSWCLKTCK(DAPSWCLKTCK),
    .DAPSWDITMS(DAPSWDITMS),
    .DAPTDI(DAPTDI),
    .DAPTDO(DAPTDO),
    .FCLK(FCLK),
    .FLASHERR(FLASHERR),
    .FLASHINT(FLASHINT),
    .GPINT(GPINT),
    .INITEXP0EXREQ(INITEXP0EXREQ),
    .INITEXP0EXRESP(INITEXP0EXRESP),
    .INITEXP0HADDR(INITEXP0HADDR),
    .INITEXP0HAUSER(INITEXP0HAUSER),
    .INITEXP0HBURST(INITEXP0HBURST),
    .INITEXP0HMASTER(INITEXP0HMASTER),
    .INITEXP0HMASTLOCK(INITEXP0HMASTLOCK),
    .INITEXP0HPROT(INITEXP0HPROT),
    .INITEXP0HRDATA(INITEXP0HRDATA),
    .INITEXP0HREADY(INITEXP0HREADY),
    .INITEXP0HRESP(INITEXP0HRESP),
    .INITEXP0HRUSER(INITEXP0HRUSER),
    .INITEXP0HSEL(INITEXP0HSEL),
    .INITEXP0HSIZE(INITEXP0HSIZE),
    .INITEXP0HTRANS(INITEXP0HTRANS),
    .INITEXP0HWDATA(INITEXP0HWDATA),
    .INITEXP0HWRITE(INITEXP0HWRITE),
    .INITEXP0HWUSER(INITEXP0HWUSER),
    .INITEXP0MEMATTR(INITEXP0MEMATTR),
    .INTMONITOR(INTMONITOR),
    .IOEXPINPUTI(IOEXPINPUTI),
    .IOEXPOUTPUTENO(IOEXPOUTPUTENO),
    .IOEXPOUTPUTO(IOEXPOUTPUTO),
    .MTXHRESETN(MTXHRESETN),
    .MTXREMAP(MTXREMAP),
    .PORESETN(PORESETN),
    .RTCSRCCLK(RTCSRCCLK),
    .SRAM0ADDR(SRAM0ADDR),
    .SRAM0CS(SRAM0CS),
    .SRAM0RDATA(SRAM0RDATA),
    .SRAM0WDATA(SRAM0WDATA),
    .SRAM0WREN(SRAM0WREN),
    .SYSRESETN(SYSRESETN),
    .TARGEXP0EXREQ(TARGEXP0EXREQ),
    .TARGEXP0EXRESP(TARGEXP0EXRESP),
    .TARGEXP0HADDR(TARGEXP0HADDR),
    .TARGEXP0HAUSER(TARGEXP0HAUSER),
    .TARGEXP0HBURST(TARGEXP0HBURST),
    .TARGEXP0HMASTER(TARGEXP0HMASTER),
    .TARGEXP0HMASTLOCK(TARGEXP0HMASTLOCK),
    .TARGEXP0HPROT(TARGEXP0HPROT),
    .TARGEXP0HRDATA(TARGEXP0HRDATA),
    .TARGEXP0HREADYMUX(TARGEXP0HREADYMUX),
    .TARGEXP0HREADYOUT(TARGEXP0HREADYOUT),
    .TARGEXP0HRESP(TARGEXP0HRESP),
    .TARGEXP0HRUSER(TARGEXP0HRUSER),
    .TARGEXP0HSEL(TARGEXP0HSEL),
    .TARGEXP0HSIZE(TARGEXP0HSIZE),
    .TARGEXP0HTRANS(TARGEXP0HTRANS),
    .TARGEXP0HWDATA(TARGEXP0HWDATA),
    .TARGEXP0HWRITE(TARGEXP0HWRITE),
    .TARGEXP0HWUSER(TARGEXP0HWUSER),
    .TARGEXP0MEMATTR(TARGEXP0MEMATTR),
    .TARGFLASH0EXRESP(TARGFLASH0EXRESP),
    .TARGFLASH0HADDR(TARGFLASH0HADDR),
    .TARGFLASH0HBURST(TARGFLASH0HBURST),
    .TARGFLASH0HRDATA(TARGFLASH0HRDATA),
    .TARGFLASH0HREADYMUX(TARGFLASH0HREADYMUX),
    .TARGFLASH0HREADYOUT(TARGFLASH0HREADYOUT),
    .TARGFLASH0HRESP(TARGFLASH0HRESP),
    .TARGFLASH0HRUSER(TARGFLASH0HRUSER),
    .TARGFLASH0HSEL(TARGFLASH0HSEL),
    .TARGFLASH0HSIZE(TARGFLASH0HSIZE),
    .TARGFLASH0HTRANS(TARGFLASH0HTRANS),
    .TPIUTRACECLK(TPIUTRACECLK),
    .TPIUTRACEDATA(TPIUTRACEDATA),
    .UART0BAUDTICK(UART0BAUDTICK),
    .UART0RXDI(UART0RXDI),
    .UART0TXDO(UART0TXDO),
    .UART1BAUDTICK(UART1BAUDTICK),
    .UART1RXDI(UART1RXDI),
    .UART1TXDO(UART1TXDO)
);