IDDR

IDDR

The Input Double Data Rate (IDDR) primitive, also known as the DLPE, provides output data at the same clock edge in DDR mode. It has a logic diagram consisting of four D flip-flops (DFFN, DFF, DFF1, and DFF2), each with a similar structure. The input "D" is registered by each DFF, and the outputs "Q0", "Q1", etc., are provided to FPGA logic at the same clock edge.

This device is supported in Apicula

Ports

Port	Size	Direction
CLK	1	input
D	1	input
Q0	1	output
Q1	1	output

Parameters

Parameter	Default Value
Q0_INIT	0 (0b0)
Q1_INIT	0 (0b0)

Verilog Instantiation

IDDR #(
    .Q0_INIT(Q0_INIT),
    .Q1_INIT(Q1_INIT)
) iddr_inst (
    .CLK(CLK),
    .D(D),
    .Q0(Q0),
    .Q1(Q1)
);

IDDRC

The IDDRC primitive provides a dual data rate input with asynchronous clear functionality. It has two output signals, Q0 and Q1, which are clocked at the same edge as the input clock signal (CLK). The primitive also features an asynchronous reset input signal (CLEAR) that can be used to clear the outputs. The IDDRC primitive is similar in functionality to the IDDR primitive, but with the added feature of asynchronous clearing.

This device is supported in Apicula

Ports

Port	Size	Direction
CLEAR	1	input
CLK	1	input
D	1	input
Q0	1	output
Q1	1	output

Parameters

Parameter	Default Value
Q0_INIT	0 (0b0)
Q1_INIT	0 (0b0)

Verilog Instantiation

IDDRC #(
    .Q0_INIT(Q0_INIT),
    .Q1_INIT(Q1_INIT)
) iddrc_inst (
    .CLEAR(CLEAR),
    .CLK(CLK),
    .D(D),
    .Q0(Q0),
    .Q1(Q1)
);

IDDR_MEM

The IDDR_MEM primitive realizes double data rate input with memory. It output data is provided to FPGA logic at the same clock edge, requiring use with DQS. ICLK connects the DQSR90 of DQS output signals and sends data to IDDR_MEM according to the ICLK clock edge. The frequency relation between PCLK and ICLK is PCLK = ICLK/ff, where ff is determined by the DLLSTEP value of DQS.

This device is not yet supported in Apicula

Ports

Port	Size	Direction
D	1	input
ICLK	1	input
PCLK	1	input
Q0	1	output
Q1	1	output
RADDR	3	input
RESET	1	input
WADDR	3	input

Verilog Instantiation

IDDR_MEM iddr_mem_inst (
    .D(D),
    .ICLK(ICLK),
    .PCLK(PCLK),
    .Q0(Q0),
    .Q1(Q1),
    .RADDR(RADDR),
    .RESET(RESET),
    .WADDR(WADDR)
);