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Nextpnr‐Himbaechel Gowin
Pepijn de Vos edited this page Nov 12, 2024
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This guide covers the important command-line options for using nextpnr-himbaechel with Gowin FPGAs.
nextpnr-himbaechel --json input.json --write output.json --device <device-part> --vopt cst=<board>.cst [options]
-
--json <file>
: Input JSON design file from Yosys -
--write <file>
: Output JSON file for the placed and routed design -
--device <part>
: Target FPGA part number (e.g., GW1N-LV1QN48C6/I5) -
--vopt cst=<file>
: Specify the constraint (.cst) file for pin mappings (Required)- All top-level ports must be assigned in the CST file
- Unassigned top-level ports will cause an error
- CST files are typically provided with board documentation
-
--vopt family=<family>
: Specify the FPGA family (Required for certain devices)
Board | Device | Family |
---|---|---|
Tang Nano 20K | GW2AR-LV18QN88C8/I7 | GW2A-18C |
Tang Primer 20K | GW2A-LV18PG256C8/I7 | GW2A-18 |
Tang Nano 9K | GW1NR-LV9QN88PC6/I5 | GW1N-9C |
SZFPGA | GW1NR-LV9LQ144PC6/I5 | GW1N-9 |
Trenz TEC0117 | GW1NR-UV9QN88C6/I5 | GW1N-9 |
nextpnr-himbaechel --json design.json \
--write output.json \
--device $DEVICE \
--vopt family=$FAMILY \
--vopt cst=$BOARD.cst
Board | Device |
---|---|
Tang Nano | GW1N-LV1QN48C6/I5 |
Tang Nano 1K | GW1NZ-LV1QN48C6/I5 |
Tang Nano 4K | GW1NSR-LV4CQN48PC7/I6 |
Runber | GW1N-UV4LQ144C6/I5 |
nextpnr-himbaechel --json design.json \
--write output.json \
--device $DEVICE \
--vopt cst=$BOARD.cst
The --vopt family=<family>
option is required for certain device families where Gowin has produced silicon variants with identical part numbers. The presence of a 'C' in the device's date code indicates a silicon variant that requires explicit family specification.
For example, GW2A and GW1N-9 devices may require different family options based on silicon variants:
-
GW2A Series:
# For non-C variant --vopt family=GW2A-18 # For C variant --vopt family=GW2A-18C
-
GW1N-9 Series:
# For non-C variant --vopt family=GW1N-9 # For C variant --vopt family=GW1N-9C
-
--placer <algorithm>
: Choose placer algorithm (sa, heap; default: heap) -
--router <algorithm>
: Choose router algorithm (router1, router2; default: router1)
-
--placed-svg <file>
: Generate SVG visualization of placement -
--routed-svg <file>
: Generate SVG visualization of routing -
--report <file>
: Write timing and utilization report in JSON format
-
--pack-only
: Only pack the design without placement/routing -
--no-route
: Skip routing stage -
--no-place
: Skip placement stage
-
Missing Family Option: If you get an error message about needing to specify the family for GW2A or GW1N-9 series, check your device's marking for a 'C' variant and add the appropriate family option.
-
Missing or Incorrect CST File:
- Each top-level port in your design MUST be assigned to a physical pin in the CST file
- Unassigned ports will cause errors
- Make sure you're using the correct constraints file for your board
- CST files are typically provided with board documentation or example projects
- The chipdb (internal device database) is automatically selected based on the device and family options.
- For the most accurate results, ensure you're using the latest version of nextpnr-himbaechel.
- Reference your board's documentation for the correct CST file and pin assignments.