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OSIDES64
Pepijn de Vos edited this page Nov 17, 2024
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The OSIDES64 primitive performs 1-bit serial input to 64-bit parallel output oversampling serial-to-parallel conversion using two I/O logs (IOLs), achieving 1:64 oversampling with asynchronous reset functionality. It does not support the CALIB function for adjusting the order of output data, and it takes four samples in the same fclk cycle, unlike normal serial-to-parallel mode which performs only two samples on the rising and falling edges of fclk in one fclk cycle.
This device is not yet supported in Apicula
Port | Size | Direction |
---|---|---|
D | 1 | input |
DF0 | 1 | output |
DF1 | 1 | output |
DF2 | 1 | output |
DF3 | 1 | output |
DLYSTEP0 | 8 | input |
DLYSTEP1 | 8 | input |
DLYSTEP2 | 8 | input |
DLYSTEP3 | 8 | input |
FCLKN | 1 | input |
FCLKP | 1 | input |
FCLKQN | 1 | input |
FCLKQP | 1 | input |
PCLK | 1 | input |
Q | 64 | output |
RESET | 1 | input |
SDTAP0 | 1 | input |
SDTAP1 | 1 | input |
SDTAP2 | 1 | input |
SDTAP3 | 1 | input |
VALUE0 | 1 | input |
VALUE1 | 1 | input |
VALUE2 | 1 | input |
VALUE3 | 1 | input |
Parameter | Default Value |
---|---|
ADAPT_EN_0 | FALSE |
ADAPT_EN_1 | FALSE |
ADAPT_EN_2 | FALSE |
ADAPT_EN_3 | FALSE |
C_STATIC_DLY_0 | 0 (0b00000000000000000000000000000000) |
C_STATIC_DLY_1 | 0 (0b00000000000000000000000000000000) |
C_STATIC_DLY_2 | 0 (0b00000000000000000000000000000000) |
C_STATIC_DLY_3 | 0 (0b00000000000000000000000000000000) |
DYN_DLY_EN_0 | FALSE |
DYN_DLY_EN_1 | FALSE |
DYN_DLY_EN_2 | FALSE |
DYN_DLY_EN_3 | FALSE |
OSIDES64 #(
.ADAPT_EN_0(ADAPT_EN_0),
.ADAPT_EN_1(ADAPT_EN_1),
.ADAPT_EN_2(ADAPT_EN_2),
.ADAPT_EN_3(ADAPT_EN_3),
.C_STATIC_DLY_0(C_STATIC_DLY_0),
.C_STATIC_DLY_1(C_STATIC_DLY_1),
.C_STATIC_DLY_2(C_STATIC_DLY_2),
.C_STATIC_DLY_3(C_STATIC_DLY_3),
.DYN_DLY_EN_0(DYN_DLY_EN_0),
.DYN_DLY_EN_1(DYN_DLY_EN_1),
.DYN_DLY_EN_2(DYN_DLY_EN_2),
.DYN_DLY_EN_3(DYN_DLY_EN_3)
) osides64_inst (
.D(D),
.DF0(DF0),
.DF1(DF1),
.DF2(DF2),
.DF3(DF3),
.DLYSTEP0(DLYSTEP0),
.DLYSTEP1(DLYSTEP1),
.DLYSTEP2(DLYSTEP2),
.DLYSTEP3(DLYSTEP3),
.FCLKN(FCLKN),
.FCLKP(FCLKP),
.FCLKQN(FCLKQN),
.FCLKQP(FCLKQP),
.PCLK(PCLK),
.Q(Q),
.RESET(RESET),
.SDTAP0(SDTAP0),
.SDTAP1(SDTAP1),
.SDTAP2(SDTAP2),
.SDTAP3(SDTAP3),
.VALUE0(VALUE0),
.VALUE1(VALUE1),
.VALUE2(VALUE2),
.VALUE3(VALUE3)
);